four-quadrant CMOS analog multiplier in current mode A new high speed and low power Current Mode Analog Circuit Design lker YA LIDERE

Transcription

1 A new high speed and low power four-quadrant CMOS analog multiplier in current mode lker YA LIDERE Current Mode Analog Circuit Design

2 CONTENT 1. INTRODUCTION 2. CIRCUIT DESCRIPTION 2.1. Current-mode Squarer Circuit 2.2. Multiplier Circuit 2.3. Divider Circuit 3. PERFORMANCE ANALYSIS 3.1. Error Due To Body Effect 3.2. Input Range and I/O Resistance 4. CONCLUSION 2

3 ABSTRACT In [1], a new CMOS current-mode fourquadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is used as the basic building block. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. 3

4 ABSTRACT The simulation results of analog multiplier demonstrate a linearity error of 1.1%, 1% a THD of 0.97% in 1MHz, a 3dB bandwidth of 41.8MHz and a maximum power consumption o of 0.34mW. 4

5 INTRODUCTION The four-quadrant multiplier has many applications in automatic gain controlling, phase locked loop, modulation, detection, frequency translation, square rooting of signals, s, neural networks, fuzzy integrated ed systems. 5

6 INTRODUCTION Power consumption, linearity and the accuracy parameters are the key parameters in the design of high-performance mixed- signal integrated circuit. i Linearity, speed, supply voltage and power dissipation are the main goals of the design. 6

7 INTRODUCTION Several techniques for reducing power consumption in CMOS analog multiplier circuits have recently been proposed[1]. They use floating gate MOS [2 4], bulkdriven MOS [5], subthreshold mode [6,7] or class-ab mode [8,9]. They suffer for not being highly hl precise and not having low power and high speed. 7

8 INTRODUCTION In [1], a low-power, high-speed four-quadrant current mode analog multiplier circuit uses dual translinear loops is proposed. The circuit it is based on the square-law characteristics of an MOS transistor operated in the saturation region. In addition, the dual translinear loops allow the design of the analog multiplier circuit,which exhibits wide bandwidth, high dynamic range and high speed[10,11]. 8

9 CURRENT-MODE SQUARER CIRCUIT The current mode squarer circuit is based on the dual translinear loop. This circuit is used to realize the multiplier circuit. The drain-to- source current(i DS ) of an MOS transistor operated ed in the saturation region is given by: 9

10 10

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12 MULTIPLIER CIRCUIT The principle of operation of the proposed multiplier is based on the square-difference identity: 12

13 13

14 MULTIPLIER CIRCUIT The multiplier is based on the squaring circuit which has two dual translinear loops. The first loop (M 1 -M 4 ) provides a (X+Y) input to the squarer function, (X+Y) 2 and the second loop (M 5 -M 8 ) provides a (X Y) input to the squarer function, (X Y) 2. 14

15 MULTIPLIER CIRCUIT I B =10 A The analog multiplier circuit is simulated using HSPICE with level 49 model (BSIM3v3) of 0.35 m CMOS technology, and the supply voltage is 3.3V. 3V 15

16 SIMULATION RESULTS 16

17 SIMULATION RESULTS 17

18 SIMULATION RESULTS 18

19 THD 19

20 DIVIDER CIRCUIT By keeping the current I (or I Y Y) constant, X the output current of the multiplier circuit ill b ti l t I /I ( I /I ) d will be proportional to I Y /I B (or I X /I B ) and the divider circuit can be obtained. However, care must be taken as I B cannot be reduced below a minimum value in order to guarantee the proper biasing of the transistors. 20

21 DIVIDER CIRCUIT 21

22 ERROR DUE TO BODY EFFECT In an MOS transistor, as the source-tosubstrate voltage V SB increases, the threshold voltage V T will also increase. This is the body effect, and can be characterized by: where V t0 is the zero-bias threshold voltage, is the body effect coefficient i and b is the bulk potential. 22

23 ERROR DUE TO BODY EFFECT To avoid body effect, the cascaded MOS transistors are placed in separated wells, and V SB will be zero. Thus, these i ill h bi h h ld transistors will have zero-bias threshold voltage. In M and M transistors bulk is 2 4 s s connected to the source, hence V SB =0 and V t =V t0. 23

24 ERROR DUE TO BODY EFFECT But for M 1 and M 3, V SB 0. Considering this mismatch between M 1 and M 3 transistors we can write Where is the mismatch term between V t1, V t3. 24

25 ERROR DUE TO BODY EFFECT 25

26 ERROR DUE TO BODY EFFECT It can be seen that the mismatch error between threshold voltages is dispensable. Because 26

27 ERROR DUE TO BODY EFFECT Ignoring terms containing 27

28 ERROR DUE TO BODY EFFECT The term V 2 shows very small error. The advantage of using the function (X+Y) 2 (X Y) 2 in the multiplier li circuit it is to cancel the offset and body effect errors by eliminating the second term in I OUT. 28

29 INPUT RANGE AND I/O RES STANCE The input current range of the multiplier is restricted by dual translinear loop, M 1 -M 4 and M 5 -M 8, operating in saturation region. If we assume that the MOS transistors M 1 - M 4 operate in saturation region: 29

30 INPUT RANGE AND I/O RES STANCE Assuming I in =XI B we obtain X or namely maximum current value with which the multiplier circuit can work correctly. 30

31 INPUT RANGE AND I/O RES STANCE Squaring both sides and eliminating I B we obtain X=0, X=±2, where X=+2 is acceptable: I in 2I B. In the multiplier li circuit, it maximum input current is: I inmax = I X + I Y. Therefore I in will be maximum if 31

32 INPUT RANGE AND I/O RES STANCE Assuming input ports are SUM and SUB, the input and output impedances are: 32

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34 CONCLUSION A four-quadrant CMOS multiplier based on a new squaring circuit was proposed. The performance of the multiplier li was simulated using HSPICE software. The advantages of the proposed analog multiplier li circuit it over previous circuits it are given as high speed, high bandwidth and low-power consumption[1]. 34

35 CONCLUSION The multiplier can be used in analog VLSI circuit for low-power and high-speed applications i such as IF variable gain amplifiers, adaptive filters, phase locked loops, neural networks and integrated fuzzy systems. 35

36 CONCLUSION 36

37 References: [1] Ali Naderi, AbdollahKhoei, h Khayrollah h Hadidi, Hadi Ghasemzadeh, h A new high speed and low power four-quadrantcmosanalog multiplier in current mode, Int. J. Electron. Commun. (AEÜ) 63 (2009) [2] Mehrvarz HR, Kwok CY. A novel multi-input floating-gate MOS four-quadrant analog multiplier. IEEE J Solid-State Circuits 1997; [3] Chen J-J, J, Liu S-I, Hwang Y-S. Low-voltage single power supply four-quadrant multiplier using floating-gate MOSFETs. IEE Proc -Circuits Devices Syst 1998;145: [4] Vlassis S, Siskos S. Analogue squarer and multiplier based on floating-gate gate MOS transistors. Electron Lett 1998;32: [5] Blalock BJ, Jackson SA. A 1.2-V CMOS four-quadrant analog multiplier. In: Southwest symposium on mixed-signal i design (SSMSD 99), p [6] Coue D, Wilson G. A four-quadrant subthreshold mode multiplier for analog neural-network applications. IEEE Trans Neural Networks 1996;7:

38 References: [7] Chang C-C, Liu S-I. Weak inversion four-quadrant multiplier and twoquadrant divider. Electron Lett 1996;34: [8] Oliaei O, Loumeau P. Four-quadrant class AB CMOS current multiplier. Electron Lett 1996;32: [9] Wawryn K. AB class current mode multipliers for programmable neural networks. Electron Lett 1996;32: [10] Fabre A. New formulation to describe translinear mixed cells accurately. Proc Inst Elect Eng 1994;141(pt. G): [11] SurakampontornW, Kumwachara K. A dual translinear-based true RMSto-DC converter. IEEE Trans Instrument Meas 1998;47:

39 Thanks 39