On the design of low- voltage, low- power CMOS analog multipliers for RF applications

Transcription

1 C.J. Debono, F. Maloberti, J. Micallef: "On the design of low-voltage, low-power CMOS analog multipliers for RF applications"; IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, Apr 00, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 168 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL 00 power dissipations of the proposed class-ab buffer amplifier, which is loaded with a large-size capacitor of 680 pf with the input of a step-wise (0.54 V) for a 97.8 KHz scanning frequency, are only 1 and mw for charging and discharging, respectively. Experimental prototype output buffer implemented in the TSMC 0.6-m CMOS technology had demonstrated that the circuit draws only 30 A static current and exhibited settling times of 1.6 s and 1 s for rise and fall edges for the proposed circuit under a 680 pf capacitance load. The settling time for the rise edge is improved from 175 s of the conventional buffer amplifier to 1.6 s of the proposed buffer. The input swing is 3.85 V. The measured data do show that the proposed output buffer circuit is very suitable for the application in the flat panel as the display driver. On the Design of Low-Voltage, Low-Power CMOS Analog Multipliers for RF Applications Carl James Debono, Franco Maloberti, and Joseph Micallef Abstract Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1. V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs. Index Terms Analog multiplier, CMOS RF, low power, low voltage. REFERENCES [1] Y. Takahashi et al., Multimedia projector using pixel a-si TFT-LCD s and a high-speed analogue driver LSI, Displays: Technology & Application, vol. 13, no. 1, pp. 5 30, Jan [] C.-C. Wang, J.-C. Wu, and C.-M. Huang, Data line driver design for a color FED, in Proc. 9th Int. Vacuum Microelectronics Conf., St. Petersburg, FL, July 1996, pp [3] P.-C. Yu and J.-C. Wu, A Class-B output buffer for flat-panel-display column driver, IEEE J. Solid-State Circuits, vol. 34, pp , Jan [4] B. W. Lee and B. J. Sheu, A high-speed CMOS amplifier with dynamic frequency compensation, in Proc. IEEE CICC 1990, New York, May 1990, pp [5] H. Khorramabadi, A CMOS line driver with 80 db linearity for ISDN application, in Proc Symp. VLSI Circuits Dig. Tech. Papers, June 1991, pp [6] H. Parzhuber and W. Steinhagen, An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads, IEEE J. Solid- State Circuit, vol. 6, pp , Oct I. INTRODUCTION Continuous growth in the demand for portable wireless systems has driven recent efforts to increase integration levels in RF transceivers [1]. The integrability and power consumption of the digital part of a communications transceiver will further improve with the downscaling of technologies. The bottleneck for further advancements is the analog front-end electronics []. In order to reduce the power consumption, architectures that require smaller currents must be developed. One approach is to use structures that function at a lower supply voltage. Operation at 1. V is difficult to achieve with bipolar technologies since the base-to-emitter voltage is 0.7 V and the base-to-collector junction must be reverse biased. By contrast the MOS transistor allows the drain-to-source voltage to be lower than the gate-to-source voltage. Therefore, if the saturation voltage is kept at a few hundred millivolts there is enough room for some output dynamic range. This implies that low-voltage, low-power analog structures can be developed using CMOS technology. The downconversion mixer is one of the indispensable analog blocks in a receiver, where its main function is that of frequency translation of the incoming RF signal to an intermediate frequency for further processing. Various authors have tackled the problem of designing lowvoltage CMOS RF mixer architectures that permit satisfactory operation at frequencies higher that 900 MHz [3] [11]. Mixers based on the Gilbert cell topology [3] [6] all require stacking of a current source, the RF input pair, the local oscillator quad and the output loads, thus limiting the minimum supply voltage required by the circuit. The mixer proposed in [7] also requires a high bias voltage due to the stacking of transistors. The passive mixers proposed in [8], [9] have a better linearity than active mixer designs but require a high supply voltage required for the digital part in [8] and for the stacking in the opamp in [9]. The passive mixer proposed in [10] operates at a lower voltage than [8], [9] but it still uses transistor stacking limiting the minimum supply voltage. A different approach that requires only ground-connected transistors operating in saturation for the mixer core was taken in [11]. The minimum supply voltage of this approach is limited by the output buffer /0$ IEEE Manuscript received January 1, 001; revised August 19, 001. This work was funded under the Fourth Italian-Maltese Financial Protocol. C. J. Debono is with the Department of Electronics, University of Pavia, 7100 Pavia, Italy and also with the Department of Microelectronics, University of Malta, Msida MSD06, Malta ( carl@ele.unipv.it; cjdebo@eng.um.edu.mt). F. Maloberti is with the Department of Electronics, University of Pavia, 7100 Pavia, Italy ( franco@ele.unipv.it). J. Micallef is with the Department of Microelectronics, University of Malta, Msida MSD06, Malta ( jjmica@eng.um.edu.mt). Publisher Item Identifier S (0)

3 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL This paper first discusses design strategies for achieving low-voltage operation. Then, two low-power circuits capable of performing the analog multiplication of two differential input signals with low-signal distortion, operating from a 1. V supply, will be presented. The circuits exploit the quadratic relation between the current and the voltage of the MOS transistor in saturation. The most noticeable feature of these proposed structures is their low-voltage operation. They can operate at a supply voltage of 1. V while sustaining high linearity making them suitable for battery operated portable systems. The multipliers were designed for a 900 MHz application in a standard double-poly 0.6-m and a 0.35-m CMOS process, respectively. The principle of operation of both designs is described in Section II. In Section III the circuit realizations are presented. The nonlinearity effects and the measurement results follow in Sections IV and V, respectively, while a conclusion is given in Section VI. II. PRINCIPLE OF OPERATION Fig. 1. Block diagram of first multiplier. Utilizing architectures that require low current can reduce the power dissipation of a multiplier. Moreover, developing low-voltage analog structures that perform the required function can help reducing this current. Conventional multipliers use differential pairs and exploit the relationship between the differential output current and the product of the input voltage and the bias current. Using the input voltage as one input and the bias current as the second one a multiplier is achieved. Unfortunately a differential pair requires a V GS at the input plus a saturation voltage to operate properly. This can be a limit when we want to reduce to a minimum the supply voltage. Solutions that use transistors whose source is directly connected to ground permit us to spare a saturation voltage and allows a lower supply voltage. The basic idea used in the two examples is to convert two differential input voltages into currents, process these currents, and finally reconvert the output currents into a differential voltage. The proposed structures achieve this current processing by exploiting transistors operating in saturation. The first design to be discussed consists of the three stages shown in Fig. 1 [1]. The first stage consists of four identical adders that produce the sum of their respective inputs and an offset. This offset is required to bias the following stage. The second stage consists of two combiners [11] that convert their input voltages into currents, which are then added in resistors to output the required differential voltage. The final stage consists of buffers that are required to provide a 50 output matching. Assuming ideal circuits the differential structure will cancel all the harmonic components leaving only a constant multiplied by the differential input voltages. In the second design [13] a signal current is injected at a common node of a voltage-to-current converter controlled by another signal. This modulating current produces terms that are proportional to the multiplication of the two differential input signals together with other even ordered harmonics. The currents are then converted into voltages across resistors. Assuming ideal components the differential structure will then cancel all these unwanted harmonics leaving an output that is proportional to the required multiplication signal. III. CIRCUIT REALIZATION A. First Multiplier The schematic diagram of the adder circuit is shown in Fig.. The transistors M3 (M3a), M4 (M4a), and M5 (M5a) function as a linear V I converter giving an output current, I 01 (I 0 ), proportional to the input voltage V 1 (V ). These currents are then added in resistor R out providing an output voltage proportional to the sum of the input voltages together with a dc offset. Fig.. Adder circuit. In order to obtain low-voltage operation transistors M3 (M3a) and M 5 (M 5a) are biased in the saturation region while M 4 (M 4a) is biased in triode region of operation. This arrangement achieves suitable linearity by compensating for the nonlinear effects of transistor M5 (M 5a). This leaves some voltage headroom across R out. Transistors M 1 and M, where M 1 operates in saturation and M operates in triode region of operation, control the biasing of these transistors. The width/length ratios and the values of the resistors are given in Table I. The capacitors C1 and C are 1 pf coupling capacitors. The multiplier core consists of two identical combiners [11] and is shown in Fig. 3. Each combiner is composed of two NMOS transistors operating in the saturation region injecting their current in a load resistor. Assuming that V GS0 0 V th = V ov0 = A, where V GS0 and V ov0 are the quiescent VGS and the quiescent overdrive voltage, respectively, the input of the four NMOS transistors are proportional to VGS1 0 V th = V1 + V + A (1) V GS 0 V th = V 1 0 V + A () V GS3 0 V th = 0V 1 + V + A (3) VGS4 0 V th = 0V1 0 V + A: (4) Thus, assuming that the four transistors have the same size and the transconductance parameters, K, are equal, the current in transistor M1 is given by I D1 = KW L V 1 + V + A +V 1 V +(V 1 + V )A : (5)

4 170 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL 00 TABLE I COMPONENT VALUES OF THE ADDERS Fig. 3. Multiplier core. Similarly the currents in the other three transistors can be obtained by replacing the input voltage with the respective voltage from () (4). These currents are then added in the respective resistors making up the core to produce the required output voltage. Assuming perfect matching of the components used, this voltage is given by Vout = R[(I D1 + I D4 ) 0 (I D + I D3 )] = 4KW L RV 1V : (6) Thus, the multiplication operation has been proved mathematically. The width/length ratios of the core transistors are 50/0.6 and the values of the resistors are 1 k. The final stage of the mixer consists of a buffer. The circuit consists of a source follower and a tail current source. This stage is required to match the output of the multiplier to a 50 termination. An LC network is also inserted at the inputs of the multiplier to match the inputs to 50 terminations. Fig. 4. Schematic diagram of V I converter. B. Second Multiplier The schematic diagram of the V I converter circuit is shown in Fig. 4. The differential input swing of the structure is limited by the threshold voltage of the core transistors M 1 and M, the voltage drop across the resistors R 1 and R, and the drain-to-source voltage of the current sources M 6 and M 7. This results in a narrow differential input window for low voltage applications. In order to increase the input swing, transistors M 6 and M 7 are biased in the triode region and R 1 and R are chosen such that the drain-to-source voltages of M 1 and M are close to the supply. Transistors M 1 and M are biased to operate in the saturation region. M 4 and M 5 are common-source followers and produce currents I 01 and I 0 depending on their respective gate-to-source voltages. Thus, the currents I 01 and I 0 are proportional to the input voltages V 1 and V, respectively. The terminals V 1 and V represent the local oscillator inputs, V LO+ and V LO0, respectively. An additional signal is required to produce the multiplication with the RF input. This signal is produced by injecting a current proportional to the RF input voltage at the sources of transistors M 1 and M. The schematic diagram of the modified circuit is shown in Fig. 5. The RF current source is implemented using the follower M 3. The complete mixer, shown in Fig. 6, is made up of two voltage-tocurrent converters that are parallelly connected with a pair of voltage followers [14]. The source of the follower M 3 (M 10) and the sources of Fig. 5. Schematic of V I converter with RF current source. the transistors M 1 and M (M 8 and M 9) are connected together. Thus the LO differential current is added with a single ended RF current at this common node. The width/length ratios of the transistors and the values of the resistors used in this design are given in Table II. Assuming that the threshold voltages of all the NMOS transistors are the same and K n1 is the transconductance parameter, KW=L,ofM 1,

5 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL Fig. 6. Schematic diagram of mixer. Fig. 7. Chip micrograph of first multiplier. TABLE II COMPONENT VALUES OF THE MIXER The current passing through transistor M 4, I 01, is given by: I 01 = Kn4 R 1(I 0 I 1) 0 V th (13) where K n4 is the transconductance parameter of M 4, and is equal to K M4 W=L. Similarly, the currents passing through M 5, M 11, and M 1 (I 0, I 03 and I 04) can be found by replacing the gate-to-source voltage with the respective input voltages. The currents I 01, I 04 and I 0, I 03 are added in resistors R 01 and R 0, respectively, giving an output voltage equal to V out = R 01[(I 01 + I 04) 0 (I 0 + I 03)] (14) M, M 3, M 8, M 9, and M 10, then the currents I 1, I, I 3, and I 4 are given by I 1 = K n1 (VLO+ 0 VRF +) p + I M3K n1(v LO+ 0 V RF +) +I M3 (7) I K n1 = (VLO0 0 VRF +) p + I M3K n1(v LO0 0 V RF +) +I M3 (8) I K n1 3 = (VLO+ 0 VRF0) p + I M10 K n1 (V LO+ 0 V RF0) +I M10 (9) I K n1 4 = (VLO0 0 VRF0) p + I M10 K n1 (V LO0 0 V RF0) +I M10 : (10) Assuming that R 1 = R, the voltages V x and V y, shown in Fig. 6, can be found using the following equations: I 1 0 I = V dd 0 V x R 1 0 V dd 0 V y R 1 = V y 0 V x R 1 : (11) But, since the circuit is symmetric the voltage V x = 0V y giving: V y = R 1 (I 1 0 I ) R 1 (I and; V x = 0 I 1 ) : (1) where R 01 = R 0. Assuming that the transistors M 4, M 5, M 11 and M 1 are equal having the same parameters and the components are perfectly matched equation (14) yields: V out =0R 01 R 1 K n1 K n4 (V LO+ 0 V LO0)(V RF + 0 V RF0): (15) Thus, the resulting output is the multiplication of the two differential inputs together with a constant. IV. NONLINEARITY EFFECTS The multiplication function results from the assumption of a perfect square-law MOS characteristic and fully matched devices. Any variation from this condition will produce harmonic components in the output response. Linearity error results from mobility reduction, channel-length modulation and the body effect. The first two effects depend on the quality of the process being utilized, while connecting the bulks to the sources of the transistors reduces the body effect. The CMOS technology used in these examples does not allow for different p-wells for the NMOS devices. However, in the first case the source of the core transistors is connected to ground, while in the second case the source voltages of the input transistors are close to the ground node hence, connecting the bulk node to ground does not result in a large body effect. The accuracy of the output depends on the matching of the components. The variation in the value of the transistors transconductance parameters is approximately 0.% and that of the W=L ratio is also approximately 0.% in this technology. Also there is a mismatch in the values of the resistors of approximately 0.4%. This leads to a mismatch accuracy of approximately 0.5% and can be neglected. These

6 17 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL 00 mismatches have also an effect on the conversion gain of the circuit and as a consequence influence the noise figure of the circuit. V. MEASUREMENT RESULTS For both designs the measurements were performed using a 1. V supply and an 800 MHz, 010 dbm local oscillator signal supplied by an HP 8648C signal generator. The 900 MHz RF signal was generated using a Rhode & Schwarz SMIQ and the output signal was measured using a Rhode & Schwarz spectrum analyzer having the noise figure measurement option. The single-ended to differential inputs and the differential to single-ended output were obtained by using RF transformers with one of the inputs connected to ground. A. First Multiplier The circuit was fabricated using a standard double-poly, doublemetal 0.6 m CMOS process, and the chip micrograph with active area 48 m 400 m is shown in Fig. 7. The chip was directly bonded on the test board using aluminum bondwires and the only external components were transformers at each port of the mixer to change the signals from single-ended to differential. The 50 port matching was provided on-chip. The measured power consumption under the conditions stated above was 9.6 mw. The output spectrum for a 00 dbm RF input is illustrated in Fig. 8. It shows that the third harmonic signal, at 300 MHz, lies more than 45 db below the fundamental output signal, at 100 MHz. Keeping the local oscillator input constant at 010 dbm the RF input signal power was varied between 040 dbm and 0 dbm. For each input the fundamental and third harmonic output power were measured and plotted on the graph shown in Fig. 9. The ideal paths of these signals were interpolated and the result indicates that the circuit has an input referred IP3 of.5 dbm and a 1-dB compression point of 08 dbm. The conversion gain and noise figure of the mixer were measured using the spectrum analyzer and the FS-K3 option together with a noise source. The results are shown in Fig. 10 and indicate that the conversion gain of the circuit is 1.9 db while its noise figure is 18.6 db. B. Second Multiplier The circuit was fabricated using standard double-poly, triple-metal 0.35 m CMOS process and the chip micrograph having active area 330 m 33 m is shown in Fig. 11. The chip was directly bonded on the test board as discussed for the example above. The 50 port matching was provided on-chip. The circuit dissipates 1.8 mw when operated under the stated conditions. The spectrum of the output signal for a 00 dbm RF input is illustrated in Fig. 1. It shows that the third harmonic signal, at 300 MHz, lies more than 47 db below the fundamental output signal, at 100 MHz. The local oscillator input signal was kept constant at 010 dbm while the RF input signal power was varied between 045 dbm and 0 dbm. As the RF input was varied the fundamental and third harmonic output power were noted and plotted on the graph shown in Fig. 13. The ideal paths of these two signals were interpolated and the result indicates that the circuit has an input referred IP3 of 1. dbm and a 1-dB compression point of 08 dbm. The conversion gain and noise figure of this mixer were also measured. The results, shown in Fig. 14, indicate that the conversion gain of the circuit is 0.5 db while its noise figure is 4.3 db. Fig. 8. Fig. 9. Fig. 10. Output spectrum. Input referred IP3. Conversion gain and noise figure. VI. CONCLUSION A design approach for low-voltage, low-power mixer designs together with two examples have been presented. The measurement results indicate that both circuits have a good linearity even at these low voltages. Also, these results are comparable to the measured results of a similar approach proposed in [11], where a supply voltage of 3 V was used. Both designs occupy a small chip area making them very feasible analog multipliers in various implementations.

7 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL Fig. 11. Chip micrograph of second multiplier. Fig. 14. Conversion gain and noise figure. Fig. 1. Output spectrum. and for the circuit to operate at 1. V this range lies between 600 mv. The advantages of this structure with respect to [11] are that it has a lower power dissipation and a lower noise figure. The minimum supply voltage of the second example is limited by the threshold voltage of the input pair, the drain-to-source voltages of the current sources and the voltage across the resistors of the V I converters. For the 0.35-m CMOS technology used the threshold voltage is 0.6 V and as a result a minimum supply voltage of 1. V is required for correct operation. The advantage of this circuit over the other example is that it has a lower third harmonic component but this was achieved at the expense of a higher power dissipation and noise figure. The higher power consumption is required to guarantee linear operation of the circuit, while the higher noise figure is due to the smaller conversion gain of the circuit. The circuit also presents a better output dynamic range that has a maximum of 6300 mv, and a smaller chip area. Therefore, a proper tradeoff permits the improvement of the linearity at the expenses of higher noise figure and power dissipation. ACKNOWLEDGMENT The authors would like to thank ST Microelectronics Pavia for bonding the prototypes. Fig. 13. Input referred IP3. The supply voltage limitation of the first example is given by the adder circuits, since these require a gate-to-source voltage, a saturation voltage and some margin across the output resistance. The threshold voltage for the 0.6-m CMOS technology used is 0.75 V thus imposing a limit of 1. V supply for the circuit to function correctly. Also the output dynamic range of the circuit is limited by the core of the mixer REFERENCES [1] A. Rofougaran, J. Y. Chang, M. Rofougaran, and A. A. Abidi, A 1 GHz CMOS RF front-end IC for direct-conversion wireless receiver, IEEE J. Solid-State Circuits, vol. 31, pp , July [] J. Crols and M. Steyaert, CMOS Wireless Transceiver Design, The Netherlands: Kluwer, [3] P. J. Sullivan, B. A. Xavier, and W. H. Ku, Low voltage performance of a microwave CMOS Gilbert cell mixer, IEEE J. Solid-State Circuits, vol. 3, pp , [4] L. A. MacEachern, E. Abou-Allam, L. Wang, and T. Manku, Low voltage mixer biasing using monolithic integrated transformer de-coupling, in Proc. IEEE Int. Symp. Circuits Syst., vol., 1999, pp [5] T. K.-K. Kan, K.-C. Mak, D. Ma, and H. C. Luong, A -V 900-MHz CMOS Mixer for GSM receivers, in Proc. IEEE Int. Symp. Circuits Syst., 000, pp [6] P. J. Sullivan, B. A. Xavier, and W. H. Ku, Doubly balanced dual-gate CMOS mixer, IEEE J. Solid-State Circuits, vol. 34, pp , [7] A. N. Karanicolas, A.7-V 900-MHz CMOS LNA and mixer, IEEE J. Solid-State Circuits, vol. 31, pp , [8] T. Vasseaux, B. Huyart, P. Loumeau, and J. F. Naviner, A track&hold mixer for direct-conversion by subsampling, in Proc. IEEE Int. Symp. Circuits Syst., vol. 4, 1999, pp [9] J. Crols and M. S. J. Steyaert, A 1.5 GHz highly linear CMOS downconversion mixer, IEEE J. Solid-State Circuits, vol. 30, pp , 1995.

8 174 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO., APRIL 00 [10] A. R. Shahani, D. K. Shaeffer, and T. H. Lee, A 1-mW wide dynamic range CMOS front-end for a portable GPS receiver, IEEE J. Solid-State Circuits, vol. 3, pp , [11] S.-Y. Hsaio and C.-Y. Wu, A parallel structure for CMOS four-quadrant analog multipliers and its application to a -GHz RF downconversion mixer, IEEE J. Solid-State Circuits, vol. 33, pp , [1] C. J. Debono, F. Maloberti, and J. Micallef, A low-voltage CMOS multiplier for RF applications, in Proc. 000 Int. Symp. Low-Power Electron. Design, 000, pp [13], A low-voltage CMOS multiplier and its application to a 900 MHz RF downconversion mixer, in Proc. 7th IEEE Int. Conf. Electron., Circuits Syst., vol. 1, Dec. 000, pp [14] C.-H. Lin and M. Ismail, A 1.8 V low-power CMOS high-speed four quadrant multiplier with rail-to-rail differential input, in Proc. 5th IEEE Int. Conf. Electron., Circuits Syst., Sept. 1998, pp