A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application

Transcription

1 A ow ower igh Speed Class-B Buffer Amplifier for Flat anel Display Application Chih-Wen u Department of lectrical ngeerg, National Chi Nan University cwlu@ncnu.edu.tw Chung en ee Department of lectronics ngeerg, National Chiao Tung University cllee@cc.nctu.edu.tw Abstract A low power, high speed, but with a large put dynamic range and output swg class-b output buffer circuit which is suitable for the flat-panel display application is proposed. The buffer draws little current durg static but has a large drivg capability durg transients. t has been demonstrated with the TSMC.6µm CMOS technology. 1. ntroduction With the evolution of compact, light-weighted, low power and high quality display, there is a big demand of developg the low power consumg, high efficiency, and high-speed buffer circuit. The circuit should occupy a small die area, consume mimal power, have a settlg time smaller than the horizontal time, and a capability of offerg high current resolution which can accommodate up to 56 gray levels. For a V of full scale, each gray level corresponds to 16 mv [1-]. Some output buffers were proposed and demonstrated recent years. For examples, Yu et al [5] proposed a class-b output buffer for flat-panel-display column driver, for which a comparator was used the negative feedback path to elimate the quiescent current the output stage; ee et al [6] proposed a dynamic bias technique, to crease the bias current of the differential put stage of a two-stage amplifier when the put voltage difference is large; and Khorramabadi [7] also proposed a class-b amplifier which had a better power efficiency but with a large output transistor. n this work, a class-b CMOS output buffer circuit is proposed. The circuit achieves the large drivg capability by employg a simple but elegant comparator circuit to sense the transients of the put to turn on push-pull transistors, which are statically off when no put is applied. This creases the speed of the circuit without creasg too much static power consumption. The circuit also features a wide put voltage range, a large output swg.. The roposed Class-B Buffer Fig. 1 shows the proposed class-b buffer circuit. As a buffer, the output is connected to the vertg put (-) and the put signal is applied to the non-vertg termal (+). This buffer consists of a differential stage (M-M8), two comparators (M9-M1) and a rail-to-rail push-pull output stage (M13-M1). The differential pair M5-M6, which is biased by the constant current source M1-M, is loaded by the diode-connected transistors M7 and M8. The comparators are used to sense and amplify the voltage difference of two puts. Then the output of the comparators turn on/off the push-pull transistors. The aspect ratios of M9 and M11 are chosen to be the same as those of M7 and M8. owever, the W/ of M1 is chosen to be a little bit larger than half of M but M1 a little bit smaller than half of M, i.e., M1 M M3 + 1 W = 1 1 W = 1 M5 M7 M8 M W + W M6 M9 M1 M11 M1 V DD =5V V SS Fig. 1 The proposed class-b buffer amplifier. R1 R C1 C (1) () M13 output M1 roceedgs of the First nternational Workshop on lectronic Design, Test and Applications (DTA ) / $17.

2 n the stable state with no put, the output voltage equals to the put voltage. The currents flowg M5, M6, M7, M8, M9 and M11 are all /. Then, the currents flowg M1 and M1 are also /. owever, sce the aspect ratio of M1 is designed to be greater than half of M, this will make M1 go out of the saturation region and be the triode region. As a result, the gate voltage of M1 will be forced to be close to the value of V SS. M1 will then stay at off. For the comparator M11-M1, similarly, M11 will be the triode region. The gate voltage of M13 will be forced to be close to the value of V DD. M13 will also stay at off. That is: when no put is applied, M13 and M1 are cut off from the output. When there is an put, i.e., the put voltage of the non-vertg termal is raised, say, by a step voltage V 1, the current M5 will be creased to + V1 but the current M6 will be decreased to V1, where g m is the transconductance of M5 and M6. That is: id5 = + V1 (3) id6 = V1 () where g m = µ ncox (5) 5 µ n and C ox are the electron mobility the n channel and the gate oxide capacitance per unit area respectively. The current M6 is mirrored by M8, M9 and M11 to the two comparators M9-M1. Sce i D6 is decreased, M1 will still stay the triode region. M1 will than still stay at off. owever, if i D6 is smaller than, ie.: V1 > g m (6) where 1 W = µ ncox ( VGS Vtn ), (7) transistor M11 will go to the saturation region and its dra voltage, i.e., the gate voltage of M13 will decrease to turn on M13. M13 starts to the output node. The larger V 1 is, the more M13 is turned on. Sce the gate voltage of M13 can be decreased to a really low and M13 can be turned to fully on to the output by a maximal speed. ence, the output transistors M13-M1 can be designed to be of smaller sizes than the conventional buffer. When the output voltage reaches the level that the voltage difference between the put and output is less than / g m, VSG13 will be reduced and M13 begs to stop chargg the output node. The smaller voltage difference is, the more M13 is turned off. Similarly, when the put voltage of the non-vertertg termal is reduced by a step voltage V 1 from the stable state, M13 will still stay at off. f V 1 is greater than / g m, M1 will go to the saturation region and M1 starts to dis the output node. Also, when the output voltage reaches the level that the voltage difference between the put and output is less than / g m, M1 begs to stop dischargg output node. ence, with the consideration of the offset voltage, the operation of this buffer can be summarized as follows: 1. When V + Vout VOS, M13 will the output node.. When V + Vout VOS, M1 will dis the output node. 3. When V + V out VOS, both output transistors stay at off. where V OS is the put offset voltage of the buffer. Sce M13 and M1 are off at the stable state, they draws no static current, thus does not consume static power. ence, this circuit is low power while still can mata a relatively high-speed. 3. valuation of ower Consumption There are two components the power dissipated the amplifier. They are: the static dissipation, which is due to the dc bias current from the power supply and the dynamic dissipation due to the chargg and dischargg of the load capacitance [8]. For this circuit, the static energy dissipation durg a period can be expressed as V bias DD static = (8) f where bias is the total dc bias currents for the whole circuit and f is the frequency. The amplifier always consumes this static dissipation. For the dynamic dissipation, durg transitions, as the load capacitance is d, s are transferred from V DD through the output MOS transistor M13 to the load. ower dissipation this MOS transistor is given by roceedgs of the First nternational Workshop on lectronic Design, Test and Applications (DTA ) / $17.

3 ch arg e = ) i DD dv (9) = ( VDD V ) C The energy dissipated this MOS device as the output s from V to V is = V V = C V DD 1 ) C ) (1) As the output diss to a lower value, the power is dissipated the output NMOS transistor M1. This power dissipation is disch arg e = V i = V C dv (11) The energy dissipated as the output diss from V to V is given by dis = V V 1 = C dis ) (1) µa. The maximum dynamic power consumption is 18 mw while the static power is only 35 µw. The dynamic power consumption depends on the value of the output voltage swg. The maximum value occurs when the image on a column of the display is alternatg black-and-white and pixel by pixel. owever, when the image on a column is at a constant gray level, the dynamic power is zero. The horizontal frequency ranges from 31.5 to 97.8 Kz [3]. The power dissipation of the buffer can be estimated from equations (13), (1) and (15) for a period. Fig. 3 shows the maximum power consumption versus the frequency with a V output voltage swg (.8 ~.8 V) for the chargg and dischargg steps, respectively for the circuit. t can be seen that the power consumptions of the proposed buffer amplifier depend on the frequency. owever, they are only.833 and.997 mw for chargg and dischargg respectively durg one period even for the frequency up to 1 Kz. Fig shows the power consumption versus the output voltage swg for a 97.8 Kz frequency for the proposed buffer. The solid le is the power dissipation as the output voltage is d from.8 V while the dash le is the one disd to.8 V. t can be seen that the power dissipation depends on the output voltage swg. The total energy dissipated the amplifier as the output s from V to V durg one period is therefore = V + C V 1 ) C ( V ) V bias DD tot, charg e DD f (13) When the output diss, the total dissipated energy durg one period is tot, discharg e ( V V biasvdd 1 = + C ) (1) f The total average power dissipated one buffer amplifier durg one period is = f (15) tot tot Fig. shows the simulated results of the power supply currents for this buffer, which is loaded with a large size capacitor of 68 pf with a step-wise put of.8 V ~.8 V. Curve (a) is the current supplied from V DD and curve (b) is the current drawn from V SS. The maximum transient current is 3.6 ma. owever, the static current is only 7 Fig. The simulated results of power supply currents for the proposed buffer amplifier. Curve (a) is the current supplied from V DD and curve (b) is the current drawn from V SS.. xperimental Results The proposed output buffer amplifier was fabricated usg the TSMC.6-µm CMOS technology. The die photograph of the output buffer is shown Fig 5. Fig. 6 shows the measured results of the output with the put of a large dynamic range (.8 ~.8 V) of a 1 Kz triangular wave of the buffer amplifier loaded with a 5 V supply and a large size capacitor of 68pF (not cludg parasitic capacitances of the pad and the test circuit). The roceedgs of the First nternational Workshop on lectronic Design, Test and Applications (DTA ) / $17.

4 lower trace is the put waveform and the upper one is the measured output waveform. t can be seen that the output basically follows the put. The step response of the buffer with a 1 Kz square wave is shown Fig. 7, where the lower trace is the put waveform and the upper one is the measured output waveform. The put voltage range is.8~.8 V. The settlg times for the outputs to settle to with.% of the fal voltage are 1.8 and 1. µs for the risg and fallg edges, respectively. These values are low as compared with those of [3]. n order to show the small signal performance of the amplifier, Fig. 8 is the small signal step response of a mv step waveform of the circuit. The lower trace is the put waveform and the upper one is the measured output waveform. The output waveform follows exactly the same as the put waveform with a small offset voltage of 5 mv. The total static current is 7 µa. Maximum ower Dissipation (mw) dis Scanng Frequency (Kz) Fig. 3 The maximum power consumption versus the frequencies for a V output voltage swg (.8 ~.8 V) for the chargg and dischargg steps of the proposed buffer. proposed class-b buffer amplifier, which is loaded with a large size capacitor of 68 pf with the put of a step-wise (.8 ~.8 V) durg one period for a 97.8 Kz frequency, are only.833 and.997 mw for chargg and dischargg respectively. xperimental prototype output buffer implemented the TSMC.6-µm CMOS technology had demonstrated that the circuit draws only 7 µa static current, and exhibited settlg times of 1.8 µs and 1. µs for rise and fall edges under a 68 pf capacitance load. The put swg is V. The measured data do show that the proposed output buffer circuit is very suitable for the application the flat panel as the display driver. ower Dissipation (mw) dis. 1 3 Output Voltage Swg (V) Fig. The power consumption versus the output voltage swg for a 97.8 Kz frequency for the proposed buffer. The solid le is the power dissipation as the output voltage is d from.8 V while the dash le is the one disd to.8 V. 5. Conclusion n this paper, we have proposed and demonstrated a low power consumption, high speed, large output swg, and wide put voltage range class-b output buffer circuit which is very suitable for the flat-panel display application for drivg the large column le capacitance. The drivg capabilities of the circuit are achieved by addg comparators which sense the risg and/or fallg edges of the put waveform to turn on a push/pull transistor to /dis the output load. The push-pull transistors stay at off when there is no put applied, thus drawg no static power. The theoretical power dissipations of the Fig. 5 The die photograph of the proposed output buffer. roceedgs of the First nternational Workshop on lectronic Design, Test and Applications (DTA ) / $17.

5 Output Voltage (V/div) Output Voltage (mv/div) Time (µs/div) Fig. 6 The measured result of the proposed output buffer under a 1 Kz triangular put waveform of an amplitude of.8 V to.8 V under a 68 pf capacitance load. The lower trace is the put waveform. Time (µs/div) Fig. 8 The small signal step response of the proposed output buffer. The amplitude of the step put is mv. The lower trace is the put waveform. 6. References Output Voltage (V/div) Time (µs/div) Fig. 7 The output step response of the proposed output buffer with a 1 Kz square wave put under a 68 pf capacitance load. The lower trace is the put waveform and the upper one is the measured output waveform. [1] Y. Takahashi et al., Multimedia projector usg 7 8 pixel a-si TFT-CD s and a high-speed analogue driver S, Displays: Technology & Application, Vol. 13, No. 1, pp. 5-3, Jan., 199. [] C.-C. Wang, J.-C. Wu and C.-M. uang, Data le driver design for a color FD, roc. 9 th nt. Vacuum Microelectronics Conf., St. etersburg, F, July pp , [3] Fan You, S..K. mbabi and dgar Sanchez-Sencio, A 1.5 V Class AB Output Buffer Digest of Technical papers, SD, Monterey, CA, USA, pp , []. arzhuber and W. Stehagen, An adaptive biasg one-stage CMOS operational amplifier for drivg high capacitive loads, Journal of Solid-State Circuit, Vol. 6, pp , 1991 [5] ang-cheng Yu and Ji-Chuan Wu, A Class-B Output Buffer for Flat-anel-Display Column Driver, Journal of Solid-State Circuits, Vol. 3, No.1, Jan. pp , [6] B. W. ee and B. J. Sheu, A high-speed CMOS amplifier with dynamic frequency compensation, roc. CCC 199, New York, May 199, pp [7]. Khorramabadi, A CMOS le driver with 8 db learity for SDN application, 1991 Symp. VS Circuits Dig. Tech. apers, June pp , [8] Donald A. Neamen, lectronic Circuit Analysis and Design, Second dition, ublished by McGraw-ill, pp , 1. roceedgs of the First nternational Workshop on lectronic Design, Test and Applications (DTA ) / $17.