WITH continuous downscaling of the CMOS technology,

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 5, MAY Look-Up Table Approach for RF Circuit Simulation Using a Novel Measurement Technique Saurabh N. Agarwal, Anuranjan Jha, Student Member, IEEE, D. Vinay Kumar, Member, IEEE, Juzer Vasi, Fellow, IEEE, Mahesh B. Patil, and Subhash C. Rustagi, Senior Member, IEEE Abstract A simple and novel measurement technique to obtain three-port network-parameters of MOS transistors from two-port measurements on a single test structure is presented. The measured data is used in the form of a lookup table (LUT) for RF circuit simulation. It is shown that simulation results obtained with the LUT approach for a 2.4-GHz low-noise amplifier match very well with measurements, thus demonstrating the usefulness of the LUT approach. It is also shown that, for high frequencies, it is important to use the tables of -parameters actually measured rather than those interpolated from low-frequency measurements. This is illustrated with a tuned amplifier simulation example. Index Terms Circuit simulation, lookup table (LUT), modeling, MOSFETs, RF CMOS, three-port measurement. I. INTRODUCTION WITH continuous downscaling of the CMOS technology, the cutoff frequency of the MOSFET has reached the gigahertz regime, making it suitable for RF applications [1]. Advances in CMOS technology have enabled fabrication of passive elements like on-chip inductors, MIM capacitors for which accurate models have been developed [2]. To correctly predict the circuit behavior and to reduce design cycles, it is necessary to have compact MOSFET models which are accurate in the RF frequency range. Most of the compact models for the MOSFET are based on the quasi-static (QS) approximation. However, when the operating frequency is close to the device cutoff frequency, the QS assumption fails to accurately predict the device behavior [3] [5]. Several models have been proposed for the MOS device in the RF range [5] [7] to account for the non-qs (NQS) effects. These models predict the performance of the circuit with reasonable accuracy at high frequencies [8] but often require time-consuming and complicated optimization routines. Apart from NQS effects, extrinsic effects such as parasitic capacitances and inductances can no longer be ignored at high frequencies. This makes analytical modeling difficult. The lookup table (LUT) approach has been an attractive alternative for circuit simulation [9], and efficient interpolation algorithms have been developed for implementation of the LUT approach in circuit simulators (e.g., see [10]). In the LUT approach, the exact behavior of the device is accounted for without any approximations, and thus the long and difficult compact model development phase is avoided. For a complete LUT descripton of a MOS transistor, the device must be considered as a three-port device, and three-port microwave characteristics of the device must be obtained. Techniques to obtain three-port microwave characteristics from two-port measurements have been reported in the literature [11] [16]. However, these approaches require different test structures and often involve complicated analysis. Characterization involving different test structures introduces device-level variations in the measurements. In addition, the terminating impedance interferes with the dc-biasing of the device [13], [15]. The purpose of this paper is to: 1) demonstrate extraction of three-port characteristics of the MOS transistor from two-port measurements using a simple technique and 2) demonstrate the application of the LUT approach for analysis of MOS transistor circuits at RF. The paper is organized as follows. Section II presents a novel technique to obtain three-port -or -parameters using a twoport network analyzer and only one test structure. Section III presents the LUT approach for both small-and large-signal analysis. Simulation results using the LUT model are presented and compared with measurements. Section IV presents a simulation example to demonstrate the importance of using the actual high-frequency data in the LUT approach. Manuscript received August 9, 2004; revised February 4, This work was supported by a joint project between Indian Institute of Technology, Bombay, and the Institute of Microelectronics (IME), Singapore. The review of this paper was arranged by Editor R. Shrivastava. S. N. Agarwal was with the Electrical Engineering Department, Indian Institute of Technology Bombay, Mumbai , India. He is now with McKinsey and Company, Inc., New Delhi, India. A. Jha is with the Department of Electrical Engineering, Columbia University, New York, NY USA. D. Vinay Kumar, J. Vasi, and M. B. Patil are with the Electrical Engineering Department, Indian Institute of Technology Bombay, Mumbai , India ( mbpatil@ee.iitb.ac.in). S. C. Rustagi is with the Institute of Microelectronics, Science Park II, Singapore Digital Object Identifier /TED II. THEORY AND MEASUREMENT Any n-port network is fully characterized by its n-port-parameters like,,, and which are inter-convertible. At RF, the two-port -parameters are easily and accurately measured using a network analyzer. For, a multiport network analyzer can be used to characterize the network; however, it is not commonly available. Techniques have been reported to obtain n-port-parameters from two-port -parameters [11] [16]. In [15], three-port -parameters of a dual-gate FET were obtained by assembling twoport -parameters of special test structures. These two-port -parameters directly correspond to the entries of the characteristic /$ IEEE

2 974 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 5, MAY 2005 Fig. 1. (a) Measurement configurations GD, GS and SD. A large capacitance ac shorts the third port. (b) Three-port y-parameter matrix of a four-terminal MOSFET with bulk terminal as the common ground parameter matrix as the third port of the test structures has been terminated using the 50 characteristic impedance. This procedure has some inherent drawbacks. In the RF regime, where the deembedding of shunt parasitics is needed, the use of different device structures in the measurement can give incorrect results. More importantly, the 50 termination at the third port interferes with the DC biasing of the device, especially when the drain of the FET is terminated [13], [15]. This is not a problem if passive devices like power dividers and couplers are characterized. Here, we describe a general scheme to obtain three-port-parameters from a suitable set of two-port measurements. Our approach is much simpler and more cost-effective as compared to previously published work. The method is especially attractive for active devices since it does not interfere with biasing of the devices. A. -Parameters For any n-terminal device, the the following property [4]: -parameter matrix has where the subscripts correspond to the terminals of the device. The MOSFET, being a four-terminal device, has a total of 16 -parameters. Because of (1), we need to find only nine of these to completely characterize the device. Defining the bulk node as the common terminal (ground), a MOSFET then has three ports: gate bulk, drain bulk, and source bulk. The nine small-signal (1) -parameters associated with these three ports of the MOSFET are defined by where and stand for source, drain, gate, and bulk terminals, respectively. Let the port source bulk be ac-shorted externally with a suitably large capacitor and the signal set to zero. We define this as the GD configuration and use it to find the following two-port -parameters These-parameters are obtained from two-port -parameters using a two-port network analyzer. Similarly, by making and zero, we define GS and SD configurations, respectively. Fig. 1(a) illustrates these configurations. The two-port -parameters associated with the GS and SD configurations are given by We finally obtain the 3 3 matrix simply by assembling the two-port -parameters as shown in Fig. 1(b). This technique requires only a single device to be measured in three two-port configurations. The external ac short is achieved by using a ground/power/ground (GPG) probe which provides about 120-pF shunt capacitance at the port terminals. Note that (2) (3) (4) (5)

3 AGARWAL et al.: LUT APPROACH FOR RF CIRCUIT SIMULATION 975 III. LOW-FREQUENCY LUT-LF At low frequencies, the device can be assumed to be operating in the quasi-static regime, and the following equation holds for terminal currents: (7) Fig. 2. C as obtained from GD and GS configurations in linear and saturation regions at 1.1 GHz (V = 0:0 V). Fig. 3. Quasi-static transconductance obtained from GD, GS configurations and dc characteristics at 1.1 GHz (V =0:2 and 3.2 V, V =0:0 V). the bias source at the third port would also serve as an ac short but the cable used to provide bias at the third port cannot be calibrated by the two-port network analyzer. The GPG probe helps in bringing the ac short to the device port. The three-port -parameters are deembedded using a one-step technique [17]. In order to get the 3 3 -parameters of the shunt parasitics, the same procedure is followed for an open structure. One-step deembedding method then gives where is the deembedded -parameter matrix and is assembled from,, and. B. Validation of the Measurement Technique We have carried out -parameter characterization of m technology nmos devices. Some representative results are shown in Figs. 2 and 3. It may be seen from the figures that different measurement configurations yield consistent results, as expected. In Fig. 2, from the GD configuration matches well with that from the GS configuration. Device characteristics and symmetry with respect to bulk terminal offer another tool for data verification. For example, at low frequencies, the slope of the dc transfer characteristics must be the same as the small-signal transconductance which can be obtained from the real part of. Also, for any drain bias, the transconductances and obtained from the GD and GS configurations must be equal and opposite in sign as shown in Fig. 3. Some other validation tests of this type can be found in [18]. (6) where can be gate, drain, bulk, or source. and are functions only of the instantaneous terminal voltages, and they can be obtained directly from the measured -parameters. These constitute the low-frequency LUT for the device which can be directly used for small-signal analysis. For large-signal analysis, we need as a function of the terminal voltages which can be obtained by integration [19], [20] as illustrated in Section III-A. Note that, since the measured data is available only at discrete values of bias voltages, suitable interpolation schemes need to be employed for circuit simulation. We have used the interpolation scheme described in [10] and implemented the LUT model in the public-domain circuit simulator SEQUEL [21]. A. Terminal Charge Extraction Although the focus of this work is on small-signal analysis, it is instructive to observe that the terminal charges required for large-signal analysis can be obtained simply by integration of the measured -parameters. The imaginary part of the -parameters gives the capacitance:. Since, we can compute the terminal charges by integrating the -parameters along suitable integration paths. For example, the gate charge can be obtained by integration along the following equivalent paths: (8) (9) Fig. 4 shows obtained by numerical integration of the measured -parameters along these two paths. The two results are in excellent agreement and thus provide a good additional

4 976 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 5, MAY 2005 Fig. 4. Gate terminal charge obtained by integration along two different paths (see text) in linear and saturation regimes. Fig. 6. Measured and simulated y-parameters for the low-noise amplifier of Fig. 5 for two bias conditions. (a) V =2:5 V, and (b) V =3:0 V. The y axis values correspond to 20log(y), where y is in A/V. Fig. 5. Schematic of low-noise amplifier used for circuit simulation. Single boxes represent spiral inductors and double boxes represent MOM capacitors. check on the measured results. We have also verified that the variation of the various terminal charges with respect to the bias voltages is in qualitative agreement with that predicted by device simulation. Further comments and results on large-signal analysis using the LUT approach could be found in [20]. B. Application of LUT-LF Approach The lookup tables of -parameters can be used to simulate small-signal performance of transistor circuits directly. As an example, we consider a 2.4-GHz low-noise amplifier (LNA) circuit shown schematically in Fig. 5. The lookup tables used for transistors M1 and M2 were extracted using the measurement technique described in Section II with V, V, and V as the grid spacings. The spiral inductors and MOM capacitors were modeled using ICCAP. For transistors in the current source circuit, BSIM3 models were used. Two-port -parameters of the LNA circuit were measured and converted into -parameters. After that, a one-step deembedding was performed. The deembedded -parameters are shown in Fig. 6(a) and (b) along with the simulated -parameters for different bias conditions. A good agreement is found between the measured and simulated results. This example brings out the usefulness of the LUT approach for simulation of RF circuits. IV. HIGH-FREQUENCY SMALL-SIGNAL LUT APPROACH (LUT-HF) In the LUT-LF approach, the non-quasi-static (NQS) effects in the device as well as parasitic effects due to lead inductances

5 AGARWAL et al.: LUT APPROACH FOR RF CIRCUIT SIMULATION 977 Fig. 7. Normalized error in various y-parameters in (a) linear region (V = 1:6 V, V =0:2 V) and (b) saturation region (V =1:6 V, V =3:0 V). etc. are not included. This limits the range of validity of the LUT-LF approach. Fig. 7 shows the plots of normalized error in -parameters i.e., the difference between -parameters measured at a given frequency and its low-frequency (0.6 GHz) value. We see that, for frequencies above 3 GHz, the error goes beyond 10%. For the 2.4-GHz LNA described in Section III, the LUT-LF approach is adequate; however, at higher operating frequencies, the LUT-LF approach would not be appropriate. For high-frequency applications, it is clear that -parameters measured at the frequency of interest must be used directly rather than values extrapolated from low-frequency measurements. At low frequencies, where NQS effects and parasitic effects are negligible, the real and imaginary parts of -parameters can be shown to be independent of frequency [4]. However, at high frequencies, the frequency dependence must be accounted for by generating multiple LUTs corresponding to different frequencies. In this work, we have used steps of 0.5 GHz in the frequency axis. The dc operating bias for the device is caluculated using the LUT-LF approach. For the small-signal ac analysis, the device has been modeled as a table of terminal voltages and all capacitances and conductances ( -parameters) of the device. The defining equations for the terminal current is [4] (10) where can be gate, drain, source, or bulk. The terms and are the conductance and capacitance between the nodes x and i of the MOS device. These quantities are bias- and frequency-dependent, and represents the small-signal voltage at the terminal of the four-terminal MOS device. We will call this the Fig. 8. Gain versus frequency for the tuned amplifier circuit for (a) f = 1GHz and (b) f =8GHz. LUT-HF approach. Note that, a suitable interpolation scheme must be employed in this approach to compute the LUT entries at frequencies other than the measurement frequencies. This additional interpolation with respect to frequency is not required in the LUT-LF approach of Section III where the entries are independent of frequency. The LUT-HF approach thus requires more computer memory as compared to the LUT-LF approach. A. Circuit Simulation Example: Tuned Amplifier To illustrate the need for using the more complex LUT-HF approach, we consider a tuned amplifier circuit (inset, Fig. 8(a)) tuned at two different frequencies. This circuit was simulated using the measured MOSFET lookup tables with both LUT-LF and LUT-HF approaches. The results obtained from the two approaches are shown in Fig. 8. The results are in good agreement at a tuning frequency of 1 GHz. However, for a tuning frequency of 8 GHz, the LUT-LF results deviate significantly from the LUT-HF results. This discrepancy is expected since the LUT-LF approach does not account for frequency dependence of the -parameters which, as illustrated in Fig. 7, show significant deviation beyond 3 GHz. The simulation results presented here using the measured -parameters are in qualitative agreement with a more detailed study using 2-D device simulations [22]. V. CONCLUSION We have presented a practical and accurate technique for measurement of three-port network-parameters for a MOS

6 978 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 5, MAY 2005 transistor using two-port measurements. The measured -parameters in the form of lookup tables were used for simulation of a low-noise amplifier circuit, and excellent agreement was demonstrated between the simulated and measured performance. It was emphasized that, at high frequencies, several lookup tables need to be employed, each corresponding to a different frequency, in order to predict the circuit performance accurately. The need for the LUT-HF approach was clearly demonstrated with a tuned amplifier simulation example. [19] W. M. Coughran, W. Fichtner, and E. Grosse, Extracting transistor charges from device simulations by gradient fitting, IEEE Trans. Comput.-Aided Des., vol. 8, pp , Apr [20] D. V. Kumar, N. R. Mohapatra, M. B. Patil, and V. R. Rao, Application of look-up table approach to high- gate dielectric MOS transistor circuits, in Tech. Proc. 16th Int. Conf. VLSI Design, Jan [21] SEQUEL Users Manual. [22] S. N. Agarwal, RF modeling of submicron CMOS transistors, Indian Inst. Technol., Bombay, Jun REFERENCES [1] A. Ajjikuttira et al., A fully integrated CMOS RFIC for bluetooth applications, in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp [2] T. H. Lee, CMOS RF: No longer an oxymoron, in Proc. IEEE Gallium Arsenide Integrated Circuit Symp., Anaheim, CA, Oct. 1997, pp [3] BSIM3v3 Users Manual, Univ. California, Berkeley, CA, [4] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, [5] A. S. Porret, J. M. Sallese, and C. C. Enz, A compact nonquasi-static extension of a charge-based MOS model, IEEE Trans. Electron Devices, vol. 48, no. 8, pp , Aug [6] A. Roy, J. Vasi, and M. Patil, A new approach to model nonquasistatic (NQS) effects for MOSFETs part II: small-signal analysis, IEEE Trans. Electron Devices, vol. 12, pp , Dec [7] S. Jen, C. C. Enz, D. R. Phelke, M. Schroter, and B. J. Sheu, Accurate modeling and-parameter extraction for MOS transistors valid upto 10 GHz, IEEE Trans. Electron Devices, vol. 46, no. 11, pp , Nov [8] P. Bendix, Detailed comparison of the SP2001, EKV, and BSIM3 models, in Proc. 5th Int. Conf. Modeling Simulation Microsystems, Apr. 2002, p [9] T. Shima, T. Suguwara, S. Moriyama, and H. Yamada, Three-dimensional table look-up MOSFET model for precise circuit simulation, IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp , Jun [10] P. B. L. Meijer, Fast and smooth highly nonlinear multidimensional table models for device modeling, IEEE Trans. Circuits Syst., vol. 37, no. 3, pp , Mar [11] J. C. Tippet and R. A. Speciale, A rigorous technique for measuring the scattering matrix of a multiport device with a two-port network analyzer, IEEE Trans. Microw. Theory Tech.., vol. 82, no. 5, pp , May [12] Y. Satoda and G. E. Bodway, Three-port scattering-parameters for microwave transistor measurement, IEEE J. Solid-State Circuits, vol. 3, no. 3, pp , Sep [13] L. Selmi and D. B. Estreich, An accurate system for automated on-wafer characterization of three-port devices, in Proc. Gallium Arsenide Integrated Circuit (GaAs IC) Symp. 1990, Oct. 1990, pp [14] M. Davidovitz, Reconstruction of the S-matrix for a 3-port using measurements at only two ports, IEEE Microw. Guided Wave Lett., vol. 5, no. 10, pp , Oct [15] U. Lott, W. Baumberger, and U. Gisiger, Three-port RF characterization of foundry dual-gate FETs using two-port test structures with on-chip loading resistors, in Proc. IEEE Int. Conf. Microelectronic Test Structures, vol. 8, Mar. 1995, pp [16] S. V. den Bosch and L. Martens, Approximation of state functions in measurement-based transistor model, IEEE Trans. Microw. Theory Tech., vol. 47, no. 1, pp , Jan [17] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Verleijen, An improved de-embedding technique for on-wafer high-frequency characterization, in Proc. IEEE Bipolar Circuits Technology Meeting, 1991, pp [18] A. Jha, J. M. Vasi, S. C. Rustagi, and M. B. Patil, A novel method to obtain 3-port network parameters using 2-port measurements, in Proc. IEEE Int. Conf. Microelectronics Test Structures, Mar. 2004, pp Saurabh N. Agarwal received the B. Tech. degree in electrical engineering and the M. Tech. degree in microelectronics from the Indian Institute of Technology (IIT), Bombay, India, in 2004, under the dualdegree program. He was working on RF CMOS Modeling under the joint collaboration between IIT Bombay and the Institute of Microelectronics, Singapore. Since August, 2004, he has been with McKinsey & Company, Inc., New Delhi, India. Anuranjan Jha (S 00) received the B.Tech. and M.Tech. degrees in microelectronics from the Indian Institute of Technology (IIT) Bombay, India, in He is currently pursuing the Ph.D. degree in electrical engineering at Columbia University, New York. During the summer and winter of 2002, he was with the Institute of Microelectronics, Singapore where he worked on the RF characterization of MOSFETs. In 2004, he was an Intern at Motorola Laboratories, Plantation, FL where he was involved in the design of VCOs for frac-n PLLs. His research interests include MOS device physics and analog/rf circuit design. D. Vinay Kumar (S 02 M 05) received the B.E degree in electronics and communication engineering from Osmania University, Hyderabad, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Bombay, Mumbai, India, in 1999 and 2000, respectively. He is currently pursuing the Ph.D. degree at IIT. His current interests are in the areas of semiconductor device modeling and circuit simulation. He worked on LUT-based modeling of MOS devices, and non-quasi-static effects in MOS devices and circuits. Juzer Vasi (SM 96 F 04) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology (IIT), Bombay, India, in 1969 and the Ph.D. degree from The Johns Hopkins University (JHU), Baltimore, MD, in He was with JHU and the IIT, Delhi, before moving to the IIT, Bombay, in 1981, where he is currently a Professor. He was Head of the Electrical Engineering Department from 1992 to His research interests are in the area of CMOS devices, technology, and design. He has worked on MOS insulators, radiation effects in MOS devices, degradation and reliability of MOS devices, and modeling and simulation of MOS devices. Dr. Vasi is a Fellow of IETE, a Fellow of the Indian National Academy of Engineering, and a Distinguished Lecturer of the IEEE Electron Devices Society.

7 AGARWAL et al.: LUT APPROACH FOR RF CIRCUIT SIMULATION 979 Mahesh B. Patil received the B.Tech. degree from the Indian Institute of Technology (IIT), Bombay, India, in 1984, the M.S. degree from the University of Southern California at Los Angeles in 1987, and the Ph.D. degree from the University of Illinois, Urbana-Champaign, in 1992, all in electrical engineering. He was a Visiting Researcher with the Central Research Laboratories, Hitachi, Tokyo, Japan, in From 1994 to 1999, he was a Faculty Member with the Electrical Engineering Department, IIT, Kanpur. He is currently on the faculty of the Electrical Engineering Department at IIT, Bombay. His research interests include device modeling and simulation, and circuit simulation. Subhash C. Rustagi (SM 00) received the M.Sc. and Ph.D. degrees in physics from Kurukshetra University, Haryana, India, in 1975 and 1981, respectively. He joined the Centre for Applied Research in Electronics, Indian Institute of Technology, Delhi, India, in He moved to the Integrated Circuits and System Laboratory, Institute of Microelectronics, Singapore, as Member of Technical Staff in April, 1999, where he is in charge of the device modeling group. He has published about 30 papers in refereed journals and conferences. His research interests include device modeling and characterization, RF model and test chip development, RF ESD, and characterization of the substrate noise.