Holistic Lithography. Christophe Fouquet. Executive Vice President, Applications. 24 November 2014
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1 Holistic Lithography Christophe Fouquet Executive Vice President, Applications 24
2 Holistic Lithography Introduction Customer Problem: Beyond 20nm node scanner and non scanner contributions must be addressed to meet patterning performance requirements Slide 3 ASML Holistic Lithography: ASML provides a unique and comprehensive holistic capability via integration of scanner with computational lithography, metrology sensors feeding into scanner knobs to control the process The scanner is the only manufacturing tool processing and controlling the wafer at field / die level Customer benefits: Increased collaboration and technical intimacy with ASML experts & solutions enable faster and better ramp Yield is improved, rework & cycle time are reduced ASML business opportunity Holistic lithography revenue opportunity of 1B within next 3 years (>20% per year), at very good margins
3 10 nm Customer problem: scanner and non scanner contributors to patterning performance must be addressed example Overlay Scanner Overlay Error Contribution Other Overlay Error Contributors Slide 4 wafer 7 wafer 1 (S2F) XYSMO_DCOSAT1_ _0305 (S2F) ovx ovy Max m+3s sd Wafer alignment Etch fingerprint NXT-C:1970 Champion data ( nm) NXE:3300 Champion data ( nm) 10 nm 99.7%F x: 0.65 nm y: 0.56 nm 10 nm 99.7% x: 0.9 nm y: 0.7 nm CMP fingerprint Metrology accuracy NXT-C:1970 & NXE: Scanner OVERLAY < 2nm On product OVERLAY > 6nm
4 ASML holistic lithography: links the scanner to YieldStar metrology and computational lithography design context Slide 5 NXT - Immersion NXE - EUV 1.Advanced lithography capability 4. Process Window Enlargement 5. Process Window Control 3- Computational Lithography Design context 6. Process window detection 2- YieldStar Metrology and Control SW
5 Why ASML?: Scanner is the only tool processing and Slide 6 controlling the wafer at field level
6 Interfaces (knobs) actuators Why ASML?: Multiple scanner knobs enable in-line optimization of patterning performance Slide 7 FlexRay illuminator I Illumination D Dose O Overlay L Lens FlexRay illuminator Dose manipulator Reticle stage Even Fingers Odd Fingers Grey Filter Optical Centerline Y Z X F Focus Wafer stage
7 On product overlay Customer benefits: Adoption of holistic lithography at 20nm node enables customers to meet patterning requirements Slide 8 Other overlay contribution Scanner overlay contribution 8 L28 28nm node Overlay Requirement 7 6 Rework & Yield X 5 4 L20 20nm node Overlay Requirement Holistic Lithography Rework & Yield Scanner improvement Reference: 28nm node 20nm node scanner improvement only 20nm node Holistic lithography
8 Customer Engagements MEMORY Increasing Customers Logic ASML is working intimately with its customers to deliver Slide 9 patterning requirement through our expert support Customer Technology Nodes Customer A O F O CD O F CD O F CD Node Transition 0x Customer B O O F O F D Node Transition 1x Node Transition 0x Customer C O O F CD O F Pa Node transition 1x Node transition 0x Customer D Customer E O CD O F Pa D O F Pa CD Node transition 1x Node transition 0x Increased Scope O CD O F CD D O Pa F D Node transition 2x Node transition 1x Node transition 0x Customer F O O O F O F Node transition D1X Customer G O O O F Node transition D2X Node transition D1x Node transition D1y Customer H O O CD O Pa O F Node transition D2X Node transition D1x Node transition D1y CD= Imaging (CDU) D= Defectivity F= Focus, O = Overlay, Pa = Patterning (Computational lithography), Node transition = multiple competencies for entire node
9 Scanner OVL stability ASML will build and implement holistic lithography infrastructure over the next 5 years 1 Standalone YieldStar Slide 10 Ramp Volume Test wafers Overlay, Focus (Low frequency, dense data) Scanner stable +- 1nm over 12 months Time Metrology Control
10 ASML will build and implement holistic lithography infrastructure over the next 5 years 2 Standalone YieldStar Integrated YieldStar Slide 11 Ramp Volume Test wafers Overlay, Focus (Low frequency, dense data) Product wafers Overlay, Focus &CD after Lithography (High frequency, sparse data) 20% overlay improvement 20% focus improvement
11 Next ASML will build and implement holistic lithography infrastructure over the next 5 years Standalone YieldStar Integrated YieldStar Ramp Slide 12 Volume Standalone YieldStar ETCH Test wafers Overlay, Focus (Low frequency, dense data) Product wafers Overlay, Focus &CD after Lithography (High frequency, sparse data) CD After Etch (High frequency, sparse data) Litho Comp Server Process window optimizer Metrology Control
12 So far: BRION computational lithography continues to Slide 13 extend process window, also using scanners interfaces
13 Now: Computational lithography enters wafer fab to Slide 14 provide design context to metrology
14 and control software Process window optimization With subsequent SEM based verification and Scanner focus optimization Slide 15 Simulated & through SMO optimized die based Process Window Map Measured actual product wafer Defocus Map Patterning defect map prediction trough PW/DM maps convolution Defect Focus optimization using scanner knobs X = Defect prediction based followed by verification Tachyon Scanner & YieldStar Metrology Scanner
15 Nuisance Rate (%) Capture Rate (%) Good prospects Process Window Optimization Capturing more defects vs. POR Inspection as verified by SEM 100 Slide PWO PWO 20 0 Feature type evaluated
16 ASML holistic lithography: links the scanner to YieldStar metrology and computational lithography design context Slide 17 Scanner performance with control knobs & interfaces to enable correction of errors outside of scanner Modeling capability via computational lithography with unique design/scanner knowledge 4. Process Window Enlargement NXT - Immersion 1.Advanced lithography capability Process control loops seamlessly integrated with scanner control capability to deliver ultimate on product performance NXE - EUV 5. Process Window Control Metrology provides accurate (design aware) volume data to enable correction capability 3- Computational Lithography Design context 6. Process window detection 2- YieldStar Metrology and Control SW
17 Slide 18
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