Why Scaling? CPU speed Chip size R, C CPU can increase speed by reducing occupying area.

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1 Why Scaling? Higher density : Integration of more transistors onto a smaller chip : reducing the occupying area and production cost Higher Performance : Higher current drive : smaller metal to metal capacitance and resistance : reduced gate delay Lower voltage, lower power : Longer battery for portable electronic devices CPU speed 1 RC Chip size R, C CPU can increase speed by reducing occupying area.

2 Silicon Processing for VLSI Era Vol 3. The submicron MOSFET Constant Electric Field, Voltage & Electrostatic Scaling (by Dennard et al. in 1974) In this approach, a successful larger device structure is selected (e.g. from the previous generation of Ics) and all its dimensions and voltages are reduced by a constant scaling factor λ (>1). The new device dimensions are then L =L/ λ, tox =tox/ λ, W =W/ λ, V =V/ λ. With this approach, operating speed increase, component density increases, and power density remains constant. Unfortunately, the Vth is reduced to Vth/λ, which makes the subthreshold current larger at Vgs=0. The worst shortcoming, however, is that the power supply voltage must be reduced by the same factor as channel length. This is not compatible with circuit requirements such as noise margin, current driving capability etc. In addition, current density also increases by the scaling factor (a condition that aggravates electromigration failure in metal interconnect lines). Thus, this method has not been adopted in its original form.

3 Scaling theory Ideal scaling: Reduce W,L by a factor of a Reduce the threshold voltage and supply voltage by a factor of a Increasing all of the doping levels by a (W, L, tox, VDD, VTH, etc, are scaled down by a factor a) Id is reduced by a, but gm remains the same. As scaling into submicron region, short channel effects (SCE) prevent further scaling. (for example, Vth, Vdd, Id is not scaled properly due to SCE and other circuit related issues)

4 FinFETs and other Multi-Gate Transistors, Springer

5 IRDS roadmap,

6 IRDS roadmap,

7 Recess Channel Array Transistor (RCAT) / Vertical Channel Transistor (VCT) Floating-Gate (FG) / Charge-Trapping (CT) ITRS roadmap

8 Non-Volatile Memory MS635 Emerging Non-Volatile Memories 8 Emerging Non-Volatile Memory report, 2017 edition by Yole Development

9 Short Channel MOSFET MS635 If gate lengths < 2 um, MOSFETs began to exhibit the following strange phenomena not predicted by long-channel MOSFET. Drain current in saturation I dsat show far less increase as L is decreased. Reducing t ox yields a considerably greater increase in I dsat. (This benefit provides even a greater impetus for making t ox as thin as possible.) Increased off state leakage caused by lower Vt as L is decreased & punchthrough leakage

10 Short Channel Effect Short Channel MOSFET Threshold voltage lowering DIBL (drain induced barrier lowering) Subthreshold swing Hot carrier effects In short channel MOSFETs, -V T reduction, DIBL, punchthrough, bad subthreshold swing are the primary phenomena -The combination of short channel and high electric field in drain region causes hot carrier effects.

11 V th Lowering Threshold voltage lowering (Vt roll-off) -V T decreases when channel length decreases. Why? V G MS635 Shared charge V S L 1 V D x dc x j n+ n x ds L 2 xdd V B Near S/D, less Q d is required for V T, because the regions are already depleted by source/drain potential. V T V f FB 2 char ge F Q C share d ox f parameter 1.0

12 MS635 Drain-induced barrier lowering (DIBL) - Effect of VD on the source potential barrier: subthreshold region (or weak inversion) This occurs when small channel length is not scaled properly or S/D junction is too deep. Long channel: Drain bias does not affect the source-to-channel potential barrier (built-in potential of pn junction) 0<Vg<Vt Short channel: source-to-channel potential barrier is lowered due to DIBL. In other words, barrier lowering increases as channel length is reduced, because the source and drain form pn junction with the body, and so have associated built-in depletion layers that become significant partners in charge balance.

13 Drain-induced barrier lowering (DIBL) DIBL = d(vth)/d(vds) In Decanano SGT paper, DIBL is defined as the threshold voltage at Vd=1.0V minus the threshold voltage at Vd=0.05V.

14 Subthreshold swing Represent MOSFET switch characteristics. Long channel: Drain bias does not affect the source-to-channel potential barrier (built-in potential of pn junction) Sharp turnoff of MOSFET by gate control Short channel: source-to-channel potential barrier is lowered due to DIBL. Leakage current of punchthrough even though gate is turned off. The smaller S is, the better it is. Along with Vt, it determines the standby power. Bad Subthreshold Swing will result in higher off-state current if the Vgs applied to turn off the transistor is the same.

15 Subthreshold swing (SS): log I D Off On Definition of subthreshold swing: How much gate voltage is needed to increase the drain current one order of magnitude? A measure of switching performence slope V T V G 1 d logi SS slope dvg 60mV/decade Dst 1 dvg d logi Dst 1 C ox On current : W μ I n Dsat C L 2α ox V V 2 G T SS is an important switching parameter. Large slope (good switching) small SS Thinner oxidelarger C ox smaller SS Lower dopingsmaller Cdsmaller SS Thinner oxide increases on current. For high performance MOS TR, a thinner gate oxide is necessary.

16 Punchthrough Another explanation of punchthrough. In n-channel MOSFETs, the surface p- region is more heavily doped than the bulk, making the junction depletion region wider below the surface than in the channel region To avoid punchthrough - Substrate N a - x j - Anti-punchthrough implant: halo or pocket

17 Hot Electron Effects Power supply voltage are not scaled by scaling theory due to system related constraints. Higher electric field in drain region. Avalanche e - -h + pair generated Degrade device lifetime or changing threshold voltage. Solution: LDD (lightly doped drain)

18 LDD MS635 n - V bi kt q n + N N ln n a d 2 i a d ln 2 ni n + 2ε V bi V s D xd x p i + V qn a D V bi kt q N N V bi + V D Q - Q + n - is completely depleted max is muchsmaller