Conventional 4-Way Set-Associative Cache
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1 ISLPED 99 International Symposium on Low Power Electronics and Design Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption Koji Inoue, Tohru Ishihara, and Kazuaki Murakami Department of Computer Science and Communication Engineering Kyushu University Conventional 4-Way Set-Associative Cache Tag subarray Cache-line subarray Way 0 Way 1 Way 2 Way 3 Decode circuit Total energy for an access for decode for I/O pin drive Ecache = Edecode + Ememory + Eio for SRAM access Hit Activate of word line Activate senseamps pre(dis)charge bit lines Miss Activate of I/O pins
2 Phased 4-Way Set-Associative Cache for Low Energy Consumption Energy consumption improvement by sacrificing the performance Cycle 1 Cycle 2 Hit Miss Way-Predicting Set-Associative Cache - Concept - How can we achieve high-performance and low energy consumption at the same time? Fast access by reading out both of tag and line simultaneously Conventional : Good! Phased : Bad! Low energy by avoiding unnecessary line read access Conventional : Bad! Phased : Good! Predict which way has the data desired by the processor before the cache access is started
3 4Way-Predicting Set-Associative Cache - Operation - Way Prediction (Cache-line Base MRU Algorithm) Cycle 1 Cycle 2 Prediction Hit Miss Prediction Miss Cache Miss 4Way-Predicting Set-Associative Cache - Organization - MRU Algorithm
4 Evaluation Environment Cache Models Conventional 4-way Set-Associative Cache (4SACache) Phased 4-way Set-Associative Cache (P4SACache) Way-Predicting 4-way Set-Associative Cache (WP4SACache) Cache Size : 16 K Byte, Cache-line Size : 32 Byte, Replacement Algorithm : LRU Evaluation Items Performance (Tcache)average number of clock cycles for an access Energy (Ecache) average energy consumption for an access Energy consumed for accessing a tag-subarray Ecache ~ Ememory = Ntag Etag Ndata Edata Ave. number of tag-subarray accessed for an access Energy consumed for accessing a line-subarray Ave. number of line-subarray accessed for an access Static Analysis - Energy and Performance Expression - 4SACache P4SACache E4SACache 4 Etag + 4 Edata T4SACache 1 WP4SACache CHR:Cache Hit Rate PHR:Prediction Hit Rate EP4SACache 4 Etag + Edata CHR TP4SACache CHR EWP4SACache (Etag + Edata) + (3 Etag + 3 Edata) (1 - PHR) TWP4SACache (1 - PHR)
5 Static Analysis - Best and Worst Case - 4SACache (Conventional) P4SACache (Phased) WP4SACache (Ours) Energy Consumption Performance (Etag = 0.078Edata) Compare with Conventional (4SACache) Best Case (PHR = 100%) 75% energy improvement without any performance degradation Worst Case (PHR = 0%) 100% performance overhead without any energy improvement Experimental Analysis - Prediction Hit Rate - Average
6 Experimental Analysis - Result of Instruction Cache - Normalized Tcache Normalized Ecache 099.go 124.m88ksim 126.gcc 129.compress 130.li 099.go 124.m88ksim 126.gcc 129.compress 130.li 132.ijpeg 132.ijpeg 134.perl 134.perl 147.vortex 101.tomcatv 102.swim 103.su2cor 104.hydro2d 147.vortex 101.tomcatv 102.swim 103.su2cor 104.hydro2d 4SACache = 1.0 P4SACache WP4SACache (Our approach) Experimental Analysis - Result of Data Cache - Normalized Tcache Normalized Ecache 099.go 124.m88ksim 126.gcc 099.go 124.m88ksim 126.gcc 129.compress 129.compress 130.li 130.li 132.ijpeg 132.ijpeg 134.perl 134.perl 147.vortex 147.vortex 101.tomcatv 101.tomcatv 102.swim 102.swim 103.su2cor 103.su2cor 104.hydro2d 104.hydro2d 4SACache = 1.0 P4SACache WP4SACache (Our approach)
7 Normalized Results (%) Experimental Analysis - Energy and Performance - I-Cache 104.1% D-Cache 30.3% % 28.1% 35.2% Ecache Average of all benchmarks Conventional (4SACache) Phased (P4SACache) Way-Predicting (WP4SACache) 199.4% Tcache Normalized Results (%) Ecache 195.8% Tcache 113.0% Cache Power Consumption Cache Size trend Effect of on-chip caches to total chip power consumption DEC CPU* StrongARM SA-110 CPU* Bipolar ECL CPU** 25% 43% 50% * Kamble, et. Al., Analytical energy Dissipatiion Models for Low Power Caches, ILPED 97 ** Joouppi, et. Al., A 300-MHz 115-W 32-b Bipolar ECL Microprocessor,IEEE Journal of Solid-State Circuits 93
8 Energy Consumption Model 32KB Directmapped I-Cache Ememory=95.6% Components of the power dissipation 32KB 4-way D-Cache Ememory=97.7% Ghose, et. Al. : Energy Efficient Cache Organizations for Superscalar Processors, Power-Driven microarchitecture Workshop in Conjunction with ISCA 98 Bit line Word line Sense Amp Output driver Addr input Comparator Latche Average Energy Consumption for an access Energy consumed for accessing a tag-subarray Ecache ~ Ememory = Ntag Etag Ndata Edata Ave. number of tag-subarray accessed for an access Energy consumed for accessing a line-subarray Ave. number of line-subarray accessed for an access Experimental Analysis - Environment - Benchmarks SPECint go, 124.m88ksim, 126.gcc, 129.compress, 130.li, 132.ijpeg, 134.perl, 147.vortex SPECfp tomcatv, 102.swim, 103.su2cor, 104.hydro2d
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Revision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
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SENSE AMPS POWER DOWN
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