Wide-band mixing DACs with high spectral purity

Transcription

1 Wie-ban mixin DACs with hih spectral purity Bechthum, E. Publishe: 26/03/2015 Document Version Publisher s PDF, also known as Version of Recor (inclues final pae, issue an volume numbers) Please check the ocument version of this publication: A submitte manuscript is the author's version of the article upon submission an before peer-review. There can be important ifferences between the submitte version an the official publishe version of recor. People intereste in the research are avise to contact the author for the final version of the publication, or visit the DOI to the publisher's website. The final author version an the alley proof are versions of the publication after peer review. The final publishe version features the final layout of the paper incluin the volume, issue an pae numbers. Link to publication Citation for publishe version (APA): Bechthum, E. (2015). Wie-ban mixin DACs with hih spectral purity Einhoven: Technische Universiteit Einhoven General rihts Copyriht an moral rihts for the publications mae accessible in the public portal are retaine by the authors an/or other copyriht owners an it is a conition of accessin publications that users reconise an abie by the leal requirements associate with these rihts. Users may ownloa an print one copy of any publication from the public portal for the purpose of private stuy or research. You may not further istribute the material or use it for any profit-makin activity or commercial ain You may freely istribute the URL ientifyin the publication in the public portal? Take own policy If you believe that this ocument breaches copyriht please contact us proviin etails, an we will remove access to the work immeiately an investiate your claim. Downloa ate: 04. Oct. 2018

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3 Wie-ban Mixin-DACs with hih spectral purity PROEFSCHRIFT ter verkrijin van e raa van octor aan e Technische Universiteit Einhoven, op eza van e rector manificus prof.r.ir. C.J. van Duijn, voor een commissie aanewezen oor het Collee voor Promoties, in het openbaar te vereien op onera 26 maart 2015 om 16:00 uur oor Elbert Bechthum eboren te Kapelle

4 Dit proefschrift is oeekeur oor e promotoren en e samenstellin van e promotiecommissie is als volt: voorzitter: prof.r.ir. A.C.P.M. Backx 1 e promotor: prof.r.ir. A.H.M. van Roermun copromotor: r.ir. G.I. Raulov leen: prof.r.ir. G.G.E. Gielen (Katholieke Universiteit Leuven) prof.r.ir. A.B. Smolers prof.r.ir. R.B. Staszewski (Delft University of Technoloy) prof.ir. A.J.M van Tuijl (University of Twente) aviseur: r.ir. J. Briaire (Interate evice technoloy (IDT))

5 Wie-ban Mixin-DACs with hih spectral purity

6 4 Wie-ban Mixin-DACs with hih spectral purity/ by Elbert Bechthum Einhoven University of Technoloy A cataloue recor is available from the Einhoven University of Technoloy Library ISBN: NUR: 959 Copyriht c 2015, Elbert Bechthum, Einhoven All rihts reserve. No part of this publication may be reprouce, store in a retrieval system, or transmitte, in any form or by any means, electronic, mechanical, photocopyin, recorin or otherwise, without the prior written permission from the copyriht owner.

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9 Contents 1 Introuction Aims an scope Scientific approach Thesis outline Oriinal contributions Backroun Introuction Traitional transmitter Mixin-DAC transmitter Multicarrier GSM (Current steerin) Mixin-DAC Performance fiures Spectral contents Definitions of performance metrics State of the art Mixin-DAC performance Conclusion Architecture classification an synthesis Introuction Mixin-DAC architecture classification System level classification Power class Data representation Smart methos Sinal level classification Hih frequency sinal (LO) Low frequency mixer input sinal (BB) Implementation level classification

10 ii Contents Sinal balancin Sequence of operations Transistor usae Conclusion Promisin architectures Introuction Classification uncertainties Architecture synthesis Other architecture consierations Conclusion Mixin locality Introuction Analysis an simulations Output effects Specific lobal mixin non-linearities Specific local mixin non-linearities Common mixin non-linearities DAC non-iealities Output cascoe Conclusion Timin errors Introuction Timin errors characteristics Architecture options Timin of Data sinal Timin of LO sinal Timin of Mixe sinal Architecture comparison Conclusion Output transformer Introuction Cascoe vs. transformer Implementation options Theoretical framework Transformer moel Current-to-voltae transfer H VI (ω) Voltae ain H VV (ω)

11 Contents iii 7.5 Simulation results Transformer Extene transformer moel Transformer an Mixin-DAC Conclusion Calibration Introuction Temperature an isturbance epenence Temperature response Disturbance response Propose new calibration metho Harware Alorithm Simulation results Alorithm Temperature response Disturbance response Conclusion Sementation Introuction Output power back-off Binary matchin Sementation Conclusion Optimal architecture Classification Quantitative architecture analysis Sementation Expecte performance of final architecture Conclusion Desin of a hihly linear wie-ban Mixin-DAC Introuction Architecture Output stae Schematic Layout LO river

12 iv Contents Drivers Local supply voltae Reference enerator Driver for elevate bulk voltae Data path Full system simulations Conclusion Experimental results Introuction Measurement setup Measurement equipment Measurement boar Calibration Baseban performance Mixin ynamic performance External isturbances Output power Biasin optimization Clock - LO phase optimization Dynamic performance Raio sinals Multicarrier intermoulation GSM ACLR of WCDMA an LTE I/Q sinalin Comparison with the state-of-the-art Conclusion General conclusions Recommenations 177 Biblioraphy 179 List of Publications 187 Summary 189 Samenvattin 191 Acknowlement 193

13 Contents v Bioraphy 195 List of symbols an abbreviations 197

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15 1 Introuction Humans are social creatures by nature an hence they strive for communication. Communication can be efine as The impartin or exchanin of information by speakin, writin, or usin some other meium [1]. The way we communicate over lare istances has chane rastically throuhout history. In the past, people use for instance rums, fire beacons, or written forms. More recently, electronic forms of communication aine popularity. The invention of wireless sinals enable an evolution of han-hel evices which chane the way people connect to each other. Althouh these electronic evices offer a wie rane of possibilities, it is sai that extensive use will alter our ability for normal face-to-face communication. Nowaays, people are continuously on-line an they expect to be able to access information an interact with people at any time an place. To achieve this, wireless connectivity is massively use. To maximize the amount of information in wireless sinals, hih sinal banwith an hih spectral efficiency of the sinal is require. Hih spectral efficiency is require to maximize the information rate in the available banwith. An overview of a hypothetical sinal spectrum is shown in Fiure 1.1. The inicate spectral purity is in this work efine as the ratio between the esire sinal an the unesire sinal components. These unesire sinal components inclue noise, harmonic istortion an isturbances. Funamentally there are two omains, which efine the spectral efficiency: time an amplitue. Since the spectrum is strictly reulate an partitione, the banwith of the available ban is limite. It can be seen in Fiure 1.1 that spectral impurities cause the effective sinal banwith to be less than the banwith of the available ban. A lower level of spectral impurities results in less unuse banwith, see Fiure 1.1. Hence, to efficiently use the available ban an thus maximize the information in the time omain, a transmitter with hih spectral purity is require. To maximize the use of the amplitue omain within the sinal banwith, avance moulation methos are use, e.. QAM, OFDM etc. For accurately

16 2 Chapter 1. Introuction Available ban Power Unuse banwith Spectral purity Sinal banwith Ban mask Sinal Frequency Fiure 1.1: Maximum sinal banwith epens on the banwith of the available ban an on the spectral purity reproucin these hih-resolution sinals, a transmitter with hih spectral purity is require too. Various wireless stanars exist, which all have their own specific requirements. Some stanars have narrow-ban sinals but require a hih spectral purity, e.. GSM. Especially for basestations which transmit multicarrier sinals, the require spectral purity is hih. For multicarrier GSM, a spectral purity of more than 80Bc is require [2], see also Chapter 2. Other stanars require a lower spectral purity but have a lare sinal banwith, e.. LTE. Therefore, a universal transmitter that covers all stanars, shoul have both hih linearity an lare banwith. Various hih spectral purity applications an wie-ban applications operate at multi-ghz frequencies, e.. multicarrier GSM at 0.5-2GHz. These performance fiures an the exemplary application of multicarrier GSM are further iscusse in Chapter 2. Two core functions of a transmitter are the iital-to-analo conversion an the mixin to the RF frequency. This research shows that it is avantaeous to implement both functions toether usin a Mixin- DAC. A Mixin-DAC is efine in this work as a sinle interate esin which implements both a mixin function an a iital-to-analo-conversion function. As such, various implementation options are cateorize as Mixin- DAC. Examples of architectures, which are classifie as Mixin-DACs, are: a hih spee Nyquist DAC with interate mixin in the iital omain or a low spee Nyquist DAC with interate analo mixer. For the aforementione wie-ban transmitter with hih spectral purity, a Mixin-DAC with wie-ban hih spectral purity is require.

17 1.1. Aims an scope Aims an scope The research question of this work is: Can a Mixin-DAC be use to enerate wie-ban sinals with hih spectral purity, what are the ominant spectral-purity limitations an what can be achieve with current process technoloies? The overall aim of this work is to explore the possibilities of usin a Mixin- DAC in a wie-ban transmitter with hih spectral purity. The first suboal is to analyze the limitations an stron points of Mixin-DACs. The secon suboal is to esin a chip implementation of a Mixin-DAC with hih spectral purity, to valiate the analysis an explore what is the maximum achievable linearity an spectral purity for Mixin-DACs, in view of the constraints of the iven technoloy. This research is not aime at esinin a Mixin-DAC for a specific wireless stanar. Instea, the intention is to fin funamental an practical limitations on spectral purity. The scope of this work is on the Mixin-DAC function within a transmitter. Other transmitter blocks, e.. filters or power amplifier, are not consiere. Also other concerns, such as the interfacin to the iital omain with ifferent samplin rates, the removal of sinal imaes, or the power control of the output sinal are not consiere. The focus is on the spectral purity of a Mixin-DAC. Other characteristics of the Mixin-DAC are of minor importance, e.. power consumption or cost. The scope is limite to multi- GHz Mixin-DACs up to 4GHz, as iscusse in Chapter 2. As implementin process technoloy, only 65nm CMOS is consiere. However, the conclusions of this work can easily be extene to other process technoloies. 1.2 Scientific approach The approach followe in this work is to first systematically explore the limitations of Mixin-DACs, then synthesize the most optimal solution an finally valiate the approach by measurement of a test chip. Therefore, the followin steps are taken: analyze the state-of-the-art architectures; classify all aspects of a Mixin-DAC architecture; systematically analyze the impact of all architectural aspects on the wie-ban spectral purity; synthesize the concept of the most optimal architecture by combinin the most optimal choices for each architectural aspect;

18 4 Chapter 1. Introuction esin an measure a proof of concept to valiate the effectiveness of the classification. This project was supporte by the hih-spee ata converter roup of IDT. This inustry partner provie IP blocks of a baseline DAC [3]. These IP blocks, which provie functions that are not in the core of this research but have supportive functions, are use for the esin of the chip implementation. Some blocks are use as-is, others are moifie to match the Mixin-DAC function. 1.3 Thesis outline The outline of this work is iven in Table 1.1. Table 1.1: Thesis outline Chapter Purpose Chapter 2 To establish a common backroun an framework for the research iscusse in this thesis, the technical backroun of the research, toether with an analysis of the state-of-the-art Mixin-DACs is iscusse. Chapter 3 To facilitate a structure synthesis of an optimal architecture, a classification of various aspects of the Mixin-DAC architecture an analysis of their impact on the spectral purity is iscusse in this chapter. Chapter 4 To show that the classification leas to three promisin architectures, that nee further investiation. Chapter 5 to 9 To analyze the process-technoloy epenent aspects of the trae-off between the three promisin architectures. Chapter 10 To summarize the conclusions of the previous chapters rearin the process-technoloy epenent aspects, an to conclue which architecture is the most optimal. Chapter 11 an 12 To valiate the conclusions of the classification, an implementation of the most optimal architecture is esine an measure. Chapter 13 an 14 To answer the research question, eneral conclusions are rawn an recommenations for further research are propose.

19 1.4. Oriinal contributions Oriinal contributions The oriinal contributions of this work are: the classification of Mixin-DAC architectures base on architectural aspects; the analysis of the impact of architectural aspects on spectral purity; architectures that are synthesize base on the classification, especially the architecture which is implemente as a test chip; a new DAC sementation trae-off which inclues ynamic characteristics; analysis of the impact of an output transformer on the Mixin-DAC performance with the focus on linearity; a novel calibration metho to improve the static linearity of (Mixin-)DACs; valiation of the theory usin a chip implementation ; a measure esin with an IMD of <-82Bc an an SFDR RB of >75Bc upto1.9ghz, whichismorethanrespectively10ban5bbetterthan all known state-of-the-art publications.

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21 2 Backroun The technical backroun of the research is escribe in this chapter. The main ifferences between a transmitter with Mixin-DAC an a traitional transmitter with separate DAC an Mixer are iscusse. Typical spectra of these two types of transmitters are shown an explaine. The exemplary application, multicarrier GSM, is iscusse alon with the importance of a hih spectral purity. The current-steerin principle is chosen for implementin a Mixin-DAC with hih spectral purity. The most important non-linearity fiure is shown to be the IMD. Various performance metrics are iscusse in this chapter, which are use to quantify the performance of the Mixin-DAC in the remainin part of the thesis. The state-of-the-art Mixin-DACs are iscusse an their performance analyze. 2.1 Introuction Transmitters are important parts of the wireless systems. The performance of transmitters epens on the application. Especially for multicarrier transmitters in basestations, the require spectral purity is hih. The traitional transmitter an the Mixin-DAC transmitter are iscusse in Section 2.2 an Section 2.3 respectively. The specifications of a taret application are iscusse in Section 2.4. Section 2.5 proposes a Mixin- DAC efinition an applies the current steerin approach to Mixin- DACs. Performance fiures of the Mixin-DAC are iscusse in Section 2.6. Section 2.7 ives an overview of the performance of state-of-the-art Mixin- DAC publications. 2.2 Traitional transmitter A popular transmitter architecture is the zero/low-if transmitter. Like most transmitters, the zero-/low IF transmitter exhibits a separation between

22 8 Chapter 2. Backroun low-frequency baseban functions, i.e. the Diital to Analo Converter(DAC), an the hih-frequency RF functions, i.e. mixer an Power Amplifier (PA). A functional overview of such a transmitter is shown in Fiure 2.1. This particular example is base on I/Q sinalin. Alternatives for I/Q sinalin are iscusse in Section f in1 =150MHz I input DAC 150MHz f out =4.05GHz Mixin sinal 3.9GHz 0º 90º PA Q input DAC Diital Analo Fiure 2.1: Sinal chain of a traitional I/Q transmitter, with exemplary sinal frequency values The transmitter elements are meant to be linear. Due to non-iealities in the transmitter elements, the transfer function of the transmitter is nonlinear which introuces harmonic istortion an reuces the spectral purity of the transmitter. The most non-linear elements in a typical transmitter implementation are the PA an the mixer. Usin non-cmos implementation technoloies, e.. GaAs, usually results in a hiher linearity than stanar CMOS technoloy but also increases cost. The amplitue of the non-linear istortion in the mixer an PA epens on the output power. Therefore, usin output power back-off also improves linearity, but eraes the efficiency. Another metho for improvin the linearity is Diital PreDistortion (DPD). The DPD as a sinal (counter-istortion) to the iital input sinal, which cancels the spurious components enerate by the transmitter non-linearity[4]. The characteristics of the aitional counter-istortion can be etermine a-priori or usin a feeback loop urin operation. A-priori characterization requires either a very elaborate characterization for various sinal conitions (e.. sinal power, sinal frequency) an environment conitions (e.. temperature, supply voltae), an can also be limite in the usability (e.. limite banwith, sensitive to ain). Usin a feeback loop for characterization urin normal operation requires a linear feeback path an an alorithm to calculate the require DPD compensation. The implementation of DPD results in a hiher power consumption an increases

23 2.3. Mixin-DAC transmitter 9 the number of transmitter components, which increases cost. DPD also introuces aitional sinal elay. 2.3 Mixin-DAC transmitter Thanks to the continuous reuction of CMOS transistor size, interation ensity increases an errors ue to parasitic capacitance an couplin become smaller, which can result in hiher linearity. This enables the interation of the mixin an DAC function at hih spee an hih linearity at reasonable cost, an recently resulte in the introuction of the Mixin-DAC [5]. A transmitter sinal chain with this novel Mixin-DAC is shown in Fiure 2.2. A Mixin-DAC functionally features two sinal inputs: the baseban (BB) I input f in1 =150MHz f s =1.95GS/s f out =4.05GHz Q input Mixin sinal 3.9GHz Diital 0º 90º Analo PA Mixin-DAC Fiure 2.2: Sinal chain of I/Q transmitter with Mixin-DAC, with exemplary sinal frequency values ata input (i.e. I input an Q input in Fiure 2.2), which contains the sample low frequency information sinal; an a mixin sinal, alternatively calle Local Oscillator (LO) sinal. As a sinle unit, the Mixin-DAC features much more architectural choices, compare to just combinin a DAC an a mixer. Potential avantaes of these new architectural choices inclue: lower power consumption, hiher linearity, hiher sinal frequency an lower noise power[6]. Moreover, by combinin the DAC an mixer in one packae, the number of components of a transmitter is reuce, which reuces the total footprint an reuces cost. One of the most obvious ifferences between the traitional transmitter an the Mixin-DAC transmitter, is the absence of a reconstruction filter between the DAC an mixer function in the latter. This poses aitional requirementsontherfoutputfilter,whichnowalsohastofilteroutthesinal

24 10 Chapter 2. Backroun imaes in the hiher Nyquist bans. Fiure 2.3 raphically shows the output spectrum ifference between a separate DAC an mixer with an without reconstruction filter for the iven input spectra. The former case represents the sinal at the output of the mixer in a traitional transmitter while the latter case represents the output sinal of a Mixin-DAC in the novel Mixin- DAC transmitter. Another isavantae of the absence of a reconstruction filter is that the Mixin-DAC samplin rate an the mixin frequency cannot be chosen freely, but must be interepenent. This relationship is further iscusse in Section In the traitional transmitter with reconstruction filter, the P DAC [B] P LO [B] -2 F S -F S 0 F S 2 F S freq 0 f LO 2 f LO (a) Spectra of input sinals: DAC iital input (P DAC) an LO input (P LO) freq P out [B] 0 F S 2 F S f LO f LO +F S f LO +2 F S 2 f LO 2 f LO +F S (b) Spectrum of mixer output sinal with reconstruction filter freq P out [B] 0 F S 2 F S f LO f LO +F S f LO +2 F S 2 f LO 2 f LO +F S (c) Spectrum of mixer output sinal without reconstruction filter Fiure 2.3: Spectral content of the transmitter sinals: DAC iital input an LO input (a), mixer output sinal with reconstruction filter (b) an without reconstruction filter with f LO = 3 F S (c) freq

25 2.4. Multicarrier GSM 11 mixin frequency is inepenent of the DAC samplin rate. Althouh the Mixin-DAC chanes the filterin requirements, it is expecte to offer architectural choices which enable hih linearity at hih frequency. An application which can profit from these avantaes is iscusse in the next section. 2.4 Multicarrier GSM Different communication stanars have ifferent requirements on the linearity an banwith of the transmitter. GSM is the most emanin communication stanar with respect to linearity. Avantaes of usin a Mixin-DAC for GSM transmitters are similar to the eneral avantaes of Mixin-DAC transmitters: lower power consumption, hiher linearity, hiher sinal frequency an lower noise power (see Section 2.3). The spectral purity of the GSM-transmitter output sinal is efine by a spectral mask in the GSM stanar[2]. An exemplary mask is shown in Fiure 2.4. Since the lowest level of the spectral mask is 80B below the sinal power, the require spectral purity of a GSM transmitter is: SFDR RB >80Bc (Spurious Free Dynamic Rane in a Reuce Banwith, see Section 2.6.2). To account for the non-linear istortion of elements further in the sinal chain, e.. the PA, ieally the SFDR RB shoul be above 85Bc, typically in a RB of 300MHz. A sinle carrier transmitter can achieve these specifications by tiht filterin. For multicarrier transmitters, filterin is not applicable since multiple carriers are present in the output sinal, which woul be attenuate if one carrier is filtere with a tiht banpass filter. Specific filterin is also not practical since it woul nee to be ajuste for each specific frequency confiuration. For multicarrier transmitters, wie-ban noise, intermoulation of various carriers an other spurious components can cause violations of the spectral mask. Therefore, the satisfaction of the spectral mask is much more challenin for multicarrier transmitters. As intermoulation of the carriers shoul not prouce violations of the spectral mask, the require IMD (InterMoulation Distortion, see Section 2.6.2) is between -80Bc an -85Bc, while accountin for the other transmitter elements. The require NSD (Noise Spectral Density, see Section 2.6.2) can be calculate from the lowest mask level of -80Bc in a measurement banwith of 100kHz, see Fiure 2.4. The reference power of the spectral mask (0B in Fiure 2.4) is measure in a 30kHz banwith while the total power of one GSM carrier is sprea over its sinal banwith of approximately 200kHz. Therefore, the reference power is approximately

26 12 Chapter 2. Backroun Fiure 2.4: An examplary GSM mask [2] 6B lower than the total power of the GSM carrier. The require NSD is: NSD= lo 10 (100kHz)=-136Bc/Hz. Since most multicarrier GSM transmitter operate in a back-off of typically -16B FS an to account for other spurious components an other transmitter elements with 10B marin, the require NSD of the Mixin-DAC is NSD=-162B FS /Hz. Some relaxin terms are present in the GSM specifications for multicarrier basestation transmitters. Examples are: hiher spurious components are allowe in a limite number of bans, exceptions are specifie for intermoulation components, an wie-ban noise specifications are relaxe forthetransmitban. However, itisbeyonthescopeofthisworktoevaluate all these exceptions. Therefore, the specifications of sinle carrier GSM are use, which is the most strinent reference point. For multicarrier GSM transmitters in basestations, the require banwith is lare with respect to one carrier. This ownstream banwith (i.e. from the basestation to a mobile evice) of a GSM basestation can be as hih as 75 MHz (i.e. for DCS1800 [2]). The use of preistortion for the

27 2.5. (Current steerin) Mixin-DAC 13 mixer an the PA increases the banwith of the Mixin-DAC output sinal even more. Therefore, the banwith in which the hih linearity shoul be achieve (reuce banwith (RB)) is chosen to be 300MHz. The linearity an banwith taret are visualize in Fiure 2.5. This fiure clearly shows the hih require linearity an banwith of multicarrier GSM transmitters. 0 RF output filter P [Bc] MHz 80B -80 SFDR taret f out -½RB f out f out +½RB Freq Fiure 2.5: Exemplary taret performance fiures of Mixin- DAC output spectrum for this work Current GSM stanars are efine between 450MHz an 1990MHz[2]. To account for future GSM efinitions at hiher frequencies, an other communication stanars, in this work the taret output frequency rane is between 0.4GHz an 4GHz. 2.5 (Current steerin) Mixin-DAC Since the Nyquist DAC architectures are closely relate to Mixin-DACs, Nyquist DAC principles are investiate as a startin point for the research. All state-of-the-art hih spee DACs are implemente usin the currentsteerin (CS) approach. A CS (Mixin-)DAC is base on an array of current sources, which are switche on an off epenin on the iital input ata. An overview of the CS DAC principle is shown in Fiure 2.6. The popularity of the CS approach is mainly because of how a CS DAC prouces the output power. CS DACs enerate a continuous current that creates sinal power in a simple resistive loa. This sinal power is continuously available to rive the loa an output capacitance. Hence, there is no necessity for an output buffer which can limit the performance.

28 14 Chapter 2. Backroun V V out R L R L Vout I out I out D 0 D 1 D 2 D n I 0 I1 I2 In Fiure 2.6: Principle of a current steerin DAC A CS DAC can achieve hih accuracy thanks to the well-known matchin of current sources. Well-matche current sources require a lare area, which result in lare parasitic capacitances, limitin the samplin rate. However, in a CS DAC, these lare current sources only enerate a DC current an on t nee to be switche at hih spee. Furthermore, the lare current sources can be ecouple from the fast switchin action by cascoes. This is not possible if switche resistors or capacitances are use as reference components. 2.6 Performance fiures The performance of a Mixin-DAC is evaluate usin the spectral purity of the output spectrum. A istinction between the esire an unesire components of the output spectrum is iscusse in the next section. Thereafter, performance metrics are efine an iscusse Spectral contents An exemplary sinal spectrum at the output of the Mixin-DAC is shown in Fiure 2.7. Ieally, the taret output spectrum only contains sinal power at the intene output frequency (sinal insie the ashe box in Fiure 2.7): f out = f LO +f in, (2.1) where f out, f LO an f in correspon to the output, LO an input sinal frequencies. However, ue to the samplin nature of a DAC an harmonic components in the mixin sinal, the output spectrum also contains sinal enery at (see Fiure 2.7): f out = M f LO +K F S ±f in, (2.2)

29 2.6. Performance fiures Output in low Nyquist ban LO leakae Output in hih Nyquist ban DAC imae of input Output power [Bc] Harmonic istortion Harmonic istortion Freq. [GHz] f LO -f in f out =f LO +f in f LO +F S 2 f LO Fiure 2.7: Exemplary simulate Mixin-DAC output spectrum (f LO = 2 F S ) where M, K Z, an F S is the samplin rate of the D/A conversion. The power of these imaes epens on a number of variables, such as the shape of the mixin waveform (e.. sine or square, see Section ) an the shape of the Mixin-DAC impulse response. In practice, Mixin-DAC implementations suffer from non-linear istortion. For an input sinal consistin of two tones at f in1 an f in2, the output spectrum also contains unesire harmonic istortion components: f out = M f LO +K F S +N 1 f in1 +N 2 f in2, (2.3) where N 1, N 2 Z. This harmonic istortion epens on for instance the sequence (i.e. orer) of Mixin an DAC operation (see Section 3.5.2) or the mixin locality (see Section ). The enery at M = 1, K = 0, an N 1 = 1 or N 2 = 1 is esire. For hih spectral purity, the other components shoul be minimize. A banpass filter (ashe line in Fiure 2.7) can filter unesire output sinals far from the esire output sinal frequency. However, Intermoulation Distortion (IMD, see Section 2.6.2) is close to the esire output sinal, which can be seen in a zoom-in aroun the output frequency of the output spectrum in Fiure 2.8, where the ashe filter characteristic cannot filter the IMD tones. Therefore, IMD is the most critical type of non-linear istortion.

30 16 Chapter 2. Backroun 20 0 Output power [Bc] IMD 3 IMD Freq. [GHz] Fiure 2.8: Zoom-in of simulate exemplary Mixin-DAC output spectrum (f LO = 2 F S ) Definitions of performance metrics This section iscusses the performance metrics which are use in this work to quantify the performance of the Mixin-DAC Static specifications Power consumption [mw]: sum of the power consume from all static power sources. Hence, ynamic sources such as the LO or clock input are not taken into account in the power consumption fiure. The power consumption epens amon others on the sample rate an the input sinal. Interal NonLinearity (INL) & Differential NonLinearity (DNL) [LSB]: INL is the ifference between the Mixin-DAC transfer characteristic an the expecte straiht line, an DNL is the error in a DAC coe transition, see [7]. A oo INL is crucial for achievin a hih linearity. In this work, the static linearity is not limitin the performance at hih frequencies. The measurement of INL is not trivial when usin the use output confiuration, which is tailore for the measurement of the RF characteristics, see Section However, the orer of manitue of the INL can be estimate from the low frequency harmonic istortion Dynamic specifications with sinusoial sinal Output power [Bm]: The output power is measure per tone, unless inicate otherwise. For example, for a ual-tone sinal, the output power

31 2.6. Performance fiures 17 per tone is 6B lower than a sinle tone with the same amplitue. Spurious Free Dynamic Rane (SFDR) [Bc]: The ratio between the power of the esire sinal an the power of the hihest tone of the unesire spurious components (spurs). For an input sinal with multiple tones, the power of the tone with the hihest power is use as the sinal power. In this work, the input sinal is a full-scale 1 sinle tone sinal, unless otherwise specifie. The banwith in which the spurs are measure, is one Nyquist ban. Hence, LO leakae an sinal imaes are not taken into account. SFDR in a Reuce BanWith (SFDR RB ) [Bc]: SFDR measurement within a preefine frequency ban (the reuce banwith RB), which is smaller than the Nyquist ban. In this work, the position of the RB in the frequency omain is relative to the output sinal. The RB is from f out RB/2 to f out +RB/2. When the input frequency f in is low, the LO frequency falls in the RB ( f out f LO <RB/2). In that case the SFDR RB coul be equal to the LO leakae, since that spur is mostly hiher than all other spurs aroun the output sinal in this work. Therefore, for low input frequency values, the RB is chosen such that the LO leakae oes not fall in the RB: the RB is then from f LO to f LO +RB for the hih Nyquist ban an from f LO to f LO -RB for the low Nyquist ban. InterMoulation Distortion (IMD) [Bc]: The ratio between the power of the IMD tone an the esire output sinal power per tone. The two sinal tones have equal power per tone. The power of both sinal tones is equal. Theoretically, for a two-tone output sinal with frequencies f 1 an f 2, the IMD spectral components are situate at n 1 f 1 + n 2 f 2, with n 1,n 2 Z. In a Mixin-DAC, IMD is enerate in two ifferent frequency omains: the basebanomainantherfomain. IftheIMDisenerateinthebaseban part of the Mixin-DAC, these spurs are enerate ue to the frequencies f in1 an f in2, an then mixe with f LO. Hence, baseban IMD is present in the output spectrum at f LO +(n 1 f in1 +n 2 f in2 ). If the IMD is enerate inthe RF omain, the IMD is enerate ue to f out1 =f LO ±f in1 an f out2 =f LO ±f in2, an hence occurs at n 1 f out1 +n 2 f out2. Since spurs close to the output sinal are the most important spurs, in this work only the IMD components close to the output sinal are consiere when iscussin IMD, hence the o orers which satisfy: n 1 +n 2 = 1. The orer of the IMD component is efine as n 1 + n 2. For example, the two IMD3 components are shown in Fiure 2.8. In this work, the IMD3 value is calculate usin the hihest of the two IMD3 tones. When a IMD value is iven without reference to the orer of the IMD tone, the hihest tone of all o IMD orers is use. 1 In measurements, limitations in the software use for eneratin the iital input sinal, forces the maximum input amplitue to be -0.1B FS

32 18 Chapter 2. Backroun Harmonic istortion (HD) [Bc]: The harmonic istortion components, which are measure usin a sinle-tone output sinal, are situate at frequency multiples of the funamental frequency. For a iven frequency f ex, the HD components are at (n+1) f ex, with n N. For Mixin-DAC harmonics that areenerateinthebasebanomain, thehdfrequenciesaref LO +(n+1) f in. When a HD component falls outsie the Nyquist ban, the power of the fole back component is use as the corresponin HD value. HD components which are enerate in the RF omain, are situate at (n + 1) f out. The frequencyofthehdcomponentsintherfomainisfarfromthefunamental output frequency, an hence only the HD components from the baseban omain are taken into account. LO leakae [Bm]: Power in the output sinal at the frequency of the LO sinal. The absolute power is use for the LO leakae, since it is shown to be inepenent of the output sinal power. Imae leakae [Bc]: The output of a sinle Mixin-DAC contains two input sinal components, one at f LO +f in an one at f LO -f in. When usin I/Q sinalin an two LO sinals with 90 phase ifference, one of those two imaes can be cancele in the combine output. However, this suppression is never perfect. The amplitue of the unesire suppresse sinal imae with respect to the esire output component is the imae leakae. Phase noise [Bc/Hz]: Phase noise is uncertainty in the phase of the output sinal. Phase noise can istort narrowban output sinals. A phase noise measurement uses a sinle tone output sinal. The phase noise is measure in the frequency omain at various frequency istances from the output tone. Noise Spectral Density (NSD) [B FS /Hz]: Wie-ban noise can also cause violations of the spectral mask of the taret application. A wie-ban noise measurement uses a small input sinal to prevent harmonic istortion which can obscure the noise measurement. The NSD is measure in the frequency omain an as far from the carrier as necessary to not measure the phase noise. Efficiency [%]: The efficiency is the output power ivie by the total power consumption. The output power is measure usin a sinusoial sinle tone input sinal with full scale amplitue Dynamic specifications with moulate sinal Error vector manitue (EVM) [B]: Error in the accuracy of the moulate sinal. For hih linearity Mixin-DACs, the EVM is usually orers of manitue smaller than specifie by the stanar. Measurement of the EVM requires specialize harware to emoulate of the sinal. Therefore,

33 2.7. State of the art Mixin-DAC performance 19 it is not taken into account in this work. Spectral mask: The GSM application efines a spectral mask, which is the maximum power of the output sinal at each frequency, see Fiure 2.4. This spectral mask is rawn over the spectrum of the output sinal to reveal any violation. Ajacent Channel Leakae Ratio (ACLR) [Bc]: The ACLR is efine for wireless stanars which have preefine sinal bans, which are ajacent. The ACLR is the ratio between the sinal power in the esire sinal ban an the power in the ajacent channel with the hihest power. The sinal power is interate over the complete sinal ban. The ACLR is a measure of the linearity an noise performance of the Mixin-DAC. In this work, the ACLR fiures of WCDMA an LTE sinals are measure. 2.7 State of the art Mixin-DAC performance The first appearance of an RFDAC or Mixin-DAC at RF frequency [5] uses the traitional CS DAC topoloy, where the current-source transistor IMD [Bc] Multicarrier GSM taret Static errors [3] [5, 10] [3] [11, 13] [8,9] [8,9] [12] [14] Dynamic errors [15] [15] -30 DAC Mixer Mixin-DAC f [GHz] out Fiure 2.9: Overview of the IMD of state-of-the-art Mixin-DAC publications, DACs an mixers (at 1V pp output sinal amplitue)

34 20 Chapter 2. Backroun SFDR [Bc] 90 Multicarrier GSM taret Static errors 80 [3] [11] [3] [5, 10] [8,9] [13] [13] [11, 13] [8,9] Dynamic errors [23] [25] 40 [27] [16] [17] [26] [24] 30 DAC Mixin-DAC (in Nyq. ban) Mixin-DAC (in RB) f [GHz] out [17] [28] [18 20] [22] [17] [22] [21] [22] [27] [21] Fiure 2.10: Overview of the SFDR of state-of-the-art Mixin- DAC publications an DACs acts as the amplitue reference an as a mixer. Other publications use the same architecture [10, 11, 13]. However, there is a tren towar topoloies base on a (fully balance) Gilbert-cell mixer [8, 9, 12, 17 23, 25 27, 29 32]. Compare to a CS DAC output stae, these topoloies have an aitional layer of transistors which implement the mixin function. This stratey can enable separate optimization of the three functions in the Mixin-DAC output stae (i.e. reference eneration, ata switchin, an mixin). The aitional layer of transistors sacrifices voltae hearoom which otherwise coul have been use for cascoin the current source or the entire output stae. Therefore, only few publications combine Gilbert-cell mixin with an output cascoe [21,22,33] an none combine it with a current source cascoe. Topoloies focusin on hih efficiency an hih output power use a minimal stack of just one or two transistors [28,34 37]. This low number of stacke transistors requires a low operatin voltae an enables a lare output voltae swin an hence can result in a hih enery efficiency. To achieve a hih frequency, some publications use a low resolution, which results in a small area an hence achieves hih frequency [10 13, 21 23, 29, 30]. In these low resolution Mixin-DACs, the quantization noise is shape

35 2.8. Conclusion 21 usin Σ-moulation. However, Σ-moulation results in hih noise power at frequencies farther away from the output frequency (out-of-ban) an hence limit the banwith. Some solutions use a banpass filter to remove the hih out-of-ban noise [21, 22]. For a hih performance Mixin-DAC, both the static an ynamic errors shoul be sufficiently low. Most publications are unable to sufficiently isolate those two types of errors. They achieve either hih performance at low frequency or low performance at hih frequency. This can be seen in the overview of the IMD an SFDR performance of relevant DACs, mixers an Mixin-DACs, which is iven in Fiure 2.9 an Fiure 2.10 respectively. For mixers, the 3 r orer interception point at 1V pp output voltae is chosen as a measure of the linearity. These fiures clearly show that the intrinsic linearity of both the Mixin- DAC an the traitional DAC an mixer combination is not sufficient for the exemplary application. Above f out =600MHz, the IMD values are worse than necessary for the multicarrier GSM taret. Mixin-DAC SFDR values close to the taret are only achieve in a narrow reuce banwith, e.. [5,13], usin expensive non-cmos technoloies, e.. GaAs [8], or at low output power, e.. [22]. Usin an architecture which isolates the static errors from the ynamic errors, enables separate optimization an can offer hih performance at hih frequency. 2.8 Conclusion A Mixin-DAC can be use to replace the DAC an Mixer of a traitional transmitter. Usin a Mixin-DAC instea of a separate DAC an mixer reuces the number of components in a transmitter, which can ecrease the cost an increase robustness. Novel architectures of Mixin-DACs can offer hiher linearity an hiher sinal to noise ratio an lower power consumption. The current-steerin principle is the main approach for the implementation. The exemplary application, i.e. multicarrier GSM, requires a hih linearity an lare banwith, which cannot be achieve by state-of-the-art Mixin-DACs. The most important non-linear istortion component is the IMD because it cannot be filtere out.

36

37 3 Architecture classification an synthesis To achieve hih spectral purity, a novel architecture is neee. However, there are numerous possible architectures. This chapter proposes a classification of Mixin-DAC architectures. Each architecture is characterize base on its architectural aspects. This chapter proposes a set of thirteen architectural aspects an subivies them into three ifferent roups: system level, sinals level an implementation level. The structure synthesis of an architecture consists of a set of choices for all architectural aspects. The optimal choices for all architectural aspects lea to three propose caniate architectures. This chapter is base on a paper submitte to the Spriner journal Analo Interate Circuits an Sinal Processin [82]. 3.1 Introuction The esin space of Mixin-DACs is hihly complex. Numerous interepenent architectural choices exist. In open literature, a hih number of exemplary Mixin-DAC implementations can be foun, as illustrate in Section 2.7. However, the choice for a iven architecture is not well substantiate, since a comparison between Mixin-DAC architectures is not available. To achieve hih spectral purity, a novel architecture nees to be synthesize. Only a structure synthesis lea to the most optimal architecture. Therefore, this chapter proposes a classification to clarify an structure the impact of hih level architectural choices on the Mixin-DAC performance. The scope of this comparison is hih spectral purity. The

38 24 Chapter 3. Architecture classification an synthesis classification incorporates the Mixin-DAC efinition of Section 2.5. The focus is on architectural choices which are specific for Mixin-DACs an are ifferentiatin between various architectures. Subjects like Data rivers, LO river, sementation or RF packain are not iscusse since these are not ifferentiatin between the various architectures. Usin the classification, a caniate Mixin-DAC architecture is propose, which is expecte to provie sufficient intrinsic performance for multicarrier GSM. The classification of Mixin-DAC architectures is propose in Section 3.2. Three levels of abstraction are iscusse: system level, sinal level an implementation level in Section 3.3, Section 3.4 an Section 3.5 respectively. 3.2 Mixin-DAC architecture classification For hih spectral purity at hih output frequency, the Current Steerin (CS) principle is almost solely use. The reasons for that are explaine in Section 2.5 an Section In this classification, the class of CS Mixin- DACs is mainly consiere. In CS (Mixin-)DACs, the output wie-ban noise power is preominantly cause by the thermal noise of the current sources. Therefore, it is not ifferentiatin between architectures an is not iscusse into etail. Simulations of exemplary circuits are one usin an implementation in 1.2V/3.3V 65nm CMOS. For the simulations, each Mixin- DAC output stae (array of parallel current cells which enerate the output sinal, e.. Fiure 3.4 or Fiure 3.8) are moele at transistor level, unless state otherwise. To focus on the ifferences between various output-stae architectures, the common sinals (e.. the LO an Data sinal, an the biasin sinals) are assume to be ieal. Realistic sinal levels an transition times assure realistic simulation results an an accurate comparison between architectures. An overview of the propose classification is shown in Fiure 3.1. The three levels of abstraction in the classification are iscusse separately in the next three sections. 3.3 System level classification The three system level classes are: Power class, ata representation an smart methos.

39 3.3. System level classification 25 System Sinals Implementation Power class: Data representation Smart methos: - Current steerin - Class-E-like - Cartesian - Polar Section Section Sub-DAC harmonic cancellation - ΔΣ moulation - Preistortion -... Section Hih frequency (LO) mixer input sinal Baseban (BB) mixer input sinal Polarity: - Return to Zero (RZ), - Symetric aroun Zero (SaZ) Section Amplitue Frequency: Resolution: - 1-bit (square-wave mixin) (sine-wave mixin) Section F LO =F RF F LO =F RF / Section Polarity: - Return to Zero (RZ), - Symetric aroun Zero (SaZ) Section Amplitue Resolution (mixin locality): - 1-bit (local mixin) (lobal mixin) Section Frequency: - F clk =F LO F clk =F LO / Section LO sinal: - Differential - Quasi-ifferential - Sinle ene Sinal balancin BB sinal: - Differential - Quasi-ifferential - Sinle ene Operations sequence: - Cascae: Mixin DAC - Cascoe - Cascae: DAC Mixin Transistor usae: - LO current, BB ate voltae - BB current, LO ate voltae BB LO LO BB Section Section Section Section Fiure 3.1: Overview of the propose classification of Mixin-DAC architectures

40 26 Chapter 3. Architecture classification an synthesis Power class Two main principles are in use for eneratin the output power: current steerin an class-e-like[28]. The current-steerin approach is well known from hih performance DACs, an offers hih linearity an hih sample rate at reasonable output frequency. For example, the DAC of [38] prouces IMD3<-85Bc at 1.5GSps an 152MHz input frequency. However, the efficiency of a current-steerin DAC is not very hih, typically well below 1% [3,38]. Class-E type Mixin-DACs are base on the class-e power amplifier (PA), which is a switchin type PA an offers hih output power an a hih efficiency. The class-e Mixin-DAC basically consists of a number of class-e amplifiers in parallel, which are enable epenin on the iital input ata. Just like class-e PAs, hih output power an efficiency are achieve (e.. 20% at 2GHz in [28]), compare to current-steerin Mixin-DACs. Since this type of Mixin-DAC basically uses a transistor in the linear reion as referenceresistor, the linearity of this Mixin-DAC principle is low compare to CS Mixin-DACs. The current-steerin principle is the best option for achievin the hih linearity which is require for a Multicarrier-GSM transmitter. Hence, in the followin parts of the classification, it is assume that the current-steerin principle is use Data representation Most traitional transmitters use the Cartesian ata representation an processin, i.e. I-Q sinalin. Another option for the sinal representation is polar sinalin. In polar sinalin, a sinal is efine by its phase an amplitue(i.e. envelope). Examples of transmitters usin polar sinalin are the Kahn Envelope Elimination an Restoration (EER) [39] or Direct Diital RF (DDRF) polar transmitters [33, 35, 36]. The eneral avantaes an isavantaes of Cartesian an polar Mixin-DACs are summarize in Table 3.1. The avantaes an isavantaes of a complete polar transmitter are elaborately iscusse in literature [41 43] Efficiency The efficiency of Cartesian an polar Mixin-DACs partly epens on the balancin of the sinals, which is iscusse in Section The main avantae of a transmitter base on a sinle-ene polar Mixin- DAC is the hih power efficiency, especially at low output power. Since the phase is coe in the LO sinal, the envelope sinal will always have a positive

41 3.3. System level classification 27 Table 3.1: Comparison between sinal representations Sinal repres. Cartesian Polar Example Sine-wave RZ current source mixin [5,10,11, 13] Gilbert current cell mixin [8,9,18 20,30,31,40] an many others Kahn envelope elimination an restoration [39] Differential irect iital to RF [33,35] Sinle ene irect iital to RF [36] Characteristics Avantaes: baseban sinal oes not nee conversion, LOclock phase can be optimize. Disavantaes: usually poor power efficiency at low sinal level. Avantaes: oo power efficiency at low sinal level. Disavantaes: sinals nee larer banwith; isables RZ maskin of BB timin errors. sin, an hence can irectly control the number of enable current sources in the Mixin-DAC output stae. At a low sinal level, only few current sources are enable, an hence the power efficiency can be hih. In a sinle-ene Cartesian Mixin-DAC, on averae half of the current sources are always enable, since even a sinal with small amplitue resies aroun mi-scale. Quasi-ifferential sinalin can improve the power efficiency of I/Q Mixin-DACs[28], see Section Since baseban sinals are usually in Cartesian format, a polar transmitter may require a conversion step from Cartesian sinalin to polar sinalin, which results in a hiher power consumption an hiher elay Banwith A isavantae of polar transmitters is the require banwith of the envelope an phase sinal, which is require to be much larer than the banwith of the corresponin Cartesian sinals to satisfy EVM[42, 43] an harmonic istortion requirements[41] Synchronization Another avantae of a polar Mixin-DAC is that only one Mixin-DAC core is require for sinle sieban transmission. For Cartesian transmitters,

42 28 Chapter 3. Architecture classification an synthesis two Mixin-DACs are require (for the I an Q path), or a steep filter is require to filter out the unesire imae in the output spectrum. The shape of such a filter is shown as a ashe line in Fiure 2.7. In I/Q Mixin-DACs, the I an Q paths can be combine to remove one of the two sinal imaes at the left or riht of the LO frequency. The I an Q paths nee to be matche in orer to achieve oo imae rejection. This problem has been extensively investiate for traitional I/Q transmitters. Since both paths are of the same type, their behavior is intrinsically matche, an only ranom mismatch causes an unbalance in the two sinal paths. To improve the matchin, iital preistortion [44] can be use. Interestin I/Q combinin techniques exist for Mixin-DACs[28]. In polar Mixin-DACs, the hybri matchin of the phase path an amplitue path poses a challene[41]. These sinals are ifferent in type an processin harware, an o not offer intrinsic matchin, as in I/Q matchin. Timin mismatch between the two paths worsens EVM, causes spectral mask violations [42, 43], an causes harmonic istortion [41]. For polar Mixin-DACs, the transitions in the LO sinal an the amplitue sinal are not aline. Section iscusses that RZ sinalin for the LO sinal can be use to mask the timin errors in the transitions of the BB sinal if these transitions are aline with the zero phase of the LO sinal. Therefore, in polar Mixin-DACs the RZ sinalin cannot be use to mask the timin errors, which can be a isavantae. Section shows that the phase between the sample clock an the LO sinal influences the harmonic istortion components. For I/Q transmitters, this phase can be chosen freely, an hence optimize for performance. For polar transmitters, this phase is ictate by the input ata an cannot be chosen freely Conclusion Because of the isavantae of polar transmitters rearin the sinal banwith, they are almost solely use for narrowban sinals, e.. sinle carrier GSM[42]. Polar transmitters are not suitable for the transmission of multicarrier GSM because of the hih sinal banwith combine with hih spectral purity of the sinal, especially in combination with preistortion, which is iscusse in Section 2.2. However, polar transmitters are suitable for narrowban, hih efficiency an low spectral purity transmitters. Cartesian transmitters can achieve lare banwith an hih linearity. Therefore, Cartesian sinalin is the best option for the hihly linear multicarrier GSM transmitter.

43 3.4. Sinal level classification Smart methos Smart methos can be use to improve the intrinsic performance of a CS Mixin-DAC architecture. Examples of smart methos are: amplitue calibration [45, 46][87], see also Chapter 8, timin error calibration [47][88], Sub-DAC harmonic cancellation[48], Σ moulation[5, 11, 22], RF FIR filterin [11 13, 49] or preistortion [50]. More examples of smart methos are summarize in [7]. Althouh these smart methos can improve specific non-iealities, the correction mechanisms can introuce or worsen other noniealities, e.. increase the noise power, increase the power consumption or ecrease the maximum output frequency. This chapter is aime at synthesizin a Mixin-DAC architecture with the hihest intrinsic spectral purity. In eneral, smart methos can be applie with almost equal effect on every architecture. Hence, it is assume that the Mixin-DAC architecture with the hihest intrinsic performance also provies the hihest spectral purity when smart methos are taken into account. However, smart methos will be mentione when they influence the traeoff between architectural choices. 3.4 Sinal level classification The mixer function in the Mixin-DAC has two input sinals. One input is the hih frequency mixin sinal (LO), usually only containin a iscrete number of frequencies. The other is the low frequency input containin the baseban ata (BB). These two sinals are consiere in the sinal level of the classification Hih frequency sinal (LO) Oneoftheinputsofthemixerfunctionisthehihfrequencymixinsinal. The characteristics of the LO mixin sinal can be ivie in two subsets: amplitue an frequency characteristics. The amplitue characteristics are subivie into resolution an polarity characteristics Amplitue - resolution Two common shapes of mixin waveforms are: sine-wave an square wave, which correspons with -bit an 1-bit resolution. A thir option is quantize sine-wave mixin, which correspons with n-bit resolution, where n epens on the number of quantization levels. Examples of the aforementione options an a summary of the avantaes an isavantaes are shown in Table 3.2.

44 30 Chapter 3. Architecture classification an synthesis Table 3.2: Classification of Mixin-DAC architectures base on the amplitue resolution of the LO sinal Shape Example Characteristics Sine-wave Sine-wave RZ current source mixin [5,10,11, 13] Gilbert current cell Quantize sine-wave Squarewave sine-wave mixin [21,22,51] Conventional two step conversion Quantize sine-wave two step conversion[52] Quantize sine-wave Mixin-DAC[53] Sinle-ene squarewave mixin [54 56] Semi-ifferential square-wave current source mixin [57] Direct conversion [48] Gilbert current cell mixin [8,9,18 20,30,31,40] Combine output mixin [12,58] Conventional two step conversion [59] Avantaes: low control sinal feethrouh, low ata timin error sensitivity, no aitional input sinal imaes in output sinal. Disavantaes: sensitive to mixin transistor non-linearity. Avantaes: controllable number of aitional input sinal imaes in output sinal, low ata timin error sensitivity, compatible with moern CMOS process technoloies. Disavantaes: hih chip area, limite output frequency. Avantaes: very well compatible with moern CMOS process technoloies, low sensitivity to mixin transistor linearity, hih output sinal enery. Disavantaes: aitional number of input sinal imaes in output sinal. Spurious components The amplitue behavior of the LO mixer input etermines the repetition of the BB input spectrum in the RF output spectrum, i.e. M > 1 in (3.1) (see also (2.2)): f out = M f LO +K F S ±f in, (3.1)

45 3.4. Sinal level classification 31 where f out, f LO an f in are the output, LO an input sinal frequencies respectively, an F S is the D/A-conversion samplin rate, an M, K Z. Fiure 3.2 shows the ifference between the output spectra of sine-wave mixin, quantize sine-wave mixin an square-wave mixin. When the resolution is 1-bit, the LO mixer input is a square-wave. A square wave with 50% uty cycle results in repetition of the BB input spectrum at each o multiple of the funamental LO frequency[30], i.e. M {1,3,5,...} Ampl(LO ) time PSD(BB) 0 T LO 2 T LO FFT 0 freq PSD(LO) PSD(Out) 0 f LO 3 f LO 5 f LO 7 f LO freq (a) Square-wave mixin 0 f LO 3 f LO 5 f LO 7 f LO freq Ampl(LO ) time PSD(BB) 0 T LO 2 T LO FFT 0 freq PSD(LO) PSD(Out) 0 f LO 3 f LO 5 f LO 7 f LO freq 0 f LO 3 f LO 5 f LO 7 f LO (b) Quantize sine-wave mixin[52] freq Ampl(LO ) time PSD(BB) 0 T LO 2 T LO FFT 0 freq PSD(LO) PSD(Out) 0 f LO 3 f LO 5 f LO 7 f LO freq (c) Sine-wave mixin 0 f LO 3 f LO 5 f LO 7 f LO freq Fiure 3.2: Spectral consequence of sine-wave mixin, squarewave mixin an quantize sine-wave mixin[52]

46 32 Chapter 3. Architecture classification an synthesis in (3.1). An exemplary output spectrum of square-wave mixin is shown in Fiure 3.2(a). The unesire spurious components at hiher frequencies can be filtere out, which is illustrate by the ashe filter characteristic in Fiure 3.2(a). When the resolution of the LO input is infinite, the mixin sinal can be a sine-wave, ieally resultin in just one repetition of the BB input spectrum in the RF output spectrum[21], i.e. M {1} in (3.1). An exemplary output spectrum of sine-wave mixin is shown in Fiure 3.2(c). Sine-wave mixin reuces the necessity of applyin output filterin. However, repetitions of the BB spectrum are also present in the output spectrum ue to the sample nature of the BB input sinal in combination with the zero-orer-hol impulse response of the Mixin-DAC, corresponin to K > 0 in (3.1). Hence, choosin sine-wave mixin only reuces the spectral repetitions of the BB spectrum, but it oes not completely remove them. With quantize sine-wave mixin, the number of input spectrum repetitions in the output spectrum is controlle by the number of quantization levels: M {1, 7, 13,...} for the example of Fiure 3.2(b) [52]. Output filterin can be relaxe with respect to square-wave mixin since the closest mixin spur is at a hiher frequency. Linearity The linearity of the mixin transistors is important when usin sine-wave mixin. Only sine-wave mixin with a linearly mixin transistor results in no input sinal imaes in the output sinal ue to the mixin operation. Newer CMOS processes exhibit lower linearity an faster switchin[60]. Therefore, square-wave mixin an quantize sine-wave mixin are more attractive than sine-wave mixin when implemente in CMOS. However, square wave mixin allows for a hiher LO frequency than quantize sine-wave mixin, since the latter requires more LO sinal transitions for the same funamental frequency. Complexity Another isavantae of quantize sine-wave mixin compare to the other two options, is the implementation complexity. Typically, multiple synchronize control sinals an DAC cores are necessary to enerate the quantize sine-wave mixin. This increases chip area an power consumption. Feethrouh Since both the square-wave mixin an the quantize-sine-wave mixin use switchin sinals with steep transitions, couplin between the control sinals an the output of the Mixin-DAC can easily lea to spurs in the output spectrum at harmonics of the control sinal frequency. However, the

47 3.4. Sinal level classification 33 frequency of this control sinal feethrouh is n f LO, which is much hiher than the frequency of the primary output sinal, an hence can be filtere out. When usin sine-wave mixin, the control sinals o not contain sharp ees an hence sine-wave mixin is less sensitive to mixin-sinal feethrouh to the output of the Mixin-DAC. BB transition maskin Aroun the zero crossin of the sine-wave mixin sinal, the mixer masks the Mixin-DAC input from the output[10]. Therefore, if the input ata chanes at that specific moment, the switchin non-iealities of the transition from one input coe to the next are maske by the mixin sinal. Since timin errors in the transition between input coes introuces harmonic istortion in the DAC output sinal[61,62][88], this maskin behavior improves the ynamic performance of the Mixin-DAC. The maskin behavior is to a smaller eree also present in a quantize sine-wave Mixin-DAC. The squarewave mixin sinal oes not possess the aforementione maskin behavior, unless RZ sinalin is use for the LO waveform. Output power The output spectrum amplitue in the first Nyquist ban, i.e. the primary output sinal, is epenent on the mixin sinal shape. Assumin equal peakto-peak amplitue for both the square-wave an the sine-wave, the power of the funamental frequency in the square-wave spectrum is π 4 2.1B times the power of the funamental frequency in the sine-wave spectrum. This assumes the square-wave contains infinitely fast transitions, which is not true in practice. Therefore, the output power of a square-wave Mixin-DAC can be up to 2.1B hiher than a sine-wave Mixin-DAC. The output power of quantize sine-wave mixin is comparable with sine-wave mixin. Conclusion Sine wave mixin is suitable for transmitters which have no output filter or a simple output filter. Square wave mixin is suitable for transmitters where the far-off spurious components are not important because of the presence of an output filter, an where no maskin of the BB timin errors is require, unless RZ sinalin is use. Hence, square-wave mixin is the most suitable mixin-sinal shape for the emanin multicarrier GSM transmitter Amplitue - polarity The mixin sinal can alternate between +1 an -1, i.e. Symmetric aroun Zero (SaZ) sinalin, or alternate between +1 an 0, i.e. Return to Zero

48 34 Chapter 3. Architecture classification an synthesis (RZ) sinalin. Examples of Mixin-DAC implementations are cateorize in Table 3.3, base on their LO sinal shape an polarity behavior. Table 3.3: Classification of exemplary Mixin-DAC architectures base on LO sinal polarity an shape Shape SaZ RZ Sine-wave Gilbert current cell sinewave mixin [21,22,51] Sine-wave RZ current source mixin [5,10,11, Conventional two step 13] conversion with sinewave Direct conversion [48] mixin Quantize sine-wave Quantize sine-wave two step conversion[52] Square-wave Sinle-ene squarewave mixin [54 56] Semi-ifferential squarewave current source mixin [57] Gilbert current cell square-wave mixin [18 20, 30, 31, 40] Global square-wave mixin [12] Conventional two step conversion with squarewave mixin [59] Avantae: hiher output power. Gilbert current cell RZ mixin [8, 9] Combine output RZ mixin [58] Gilbert current cell Multi-RZ mixin [17] Avantae: lower sensitivity to ata sinal timin errors. The reason for eliberately choosin RZ sinalin is usually to mask the transitions of the BB sinal. Timin errors in these transitions cause harmonic istortion. This maskin is enable by switchin the BB sinal urin the Zero phase of the LO sinal[5,17]. The effect of BB timin errors can also be alleviate by other techniques[47]. A ownsie of RZ mixin is that a portion of the output power is lost, typically 50%. Moreover, RZ mixin results in a lare common moe sinal at the output, which makes interfacin with other RF components troublesome. The lower output power an lare common moe output sinal can be alleviate by time-interleavin of two Mixin-DACs with RZ mixin.

49 3.4. Sinal level classification 35 However, the power efficiency of RZ mixin remains two times lower than SaZ mixin. RZ mixin is inherent to sinle-ene mixin[5, 12, 54], which is iscusse in Section When ata timin errors are a concern, an no other technique is employe to reuce the consequence of these timin errors, RZ sinalin results in the hihest linearity. When ata timin errors are not relevant, SaZ mixin is the best option because of the output power avantae an RF interfacin avantae Frequency Usually, the first Nyquist ban at the funamental LO frequency of the output spectrum is use as the primary output sinal, i.e. M = 1 an K = 0 in (3.1). Hiher Nyquist bans also contain sinal enery which can be use as output sinal [17,63], i.e. K > 0 in (3.1). When the LO sinal also contains enery at multiples (harmonics) of the funamental LO frequency, also the sinal enery aroun these LO harmonics can be use as primary output sinal, i.e. M > 1 in (3.1). The sinal enery in hiher LO harmonic bans can be maximize by choosin square-wave mixin, an by choosin a specific uty-cycle for the LO waveform [58]. Fiure 3.3 shows an exemplary Mixin-DAC output spectrum, where both the hiher Nyquist zones an the LO harmonic bans are inicate. In this case, the LO frequency is twice the BB sample rate, i.e. f LO = 2 F S. PSD(Out) I II -II -I I II -II -I I II -II 3 4 -I I II -II LO harmonic Nyquist zone 0 F S f LO f LO +F S 2 f LO 2 f LO +F S 3 f LO 3 f LO +F S freq Fiure 3.3: Multiple Nyquist zones an LO harmonic bans in a Mixin-DAC output spectrum contain sinal enery an can be use as primary output zone. In this case, f LO = 2 F S Usin K > 0 or M > 1 oes not result in better linearity while the sinal power an Sinal to Noise Ratio (SNR) is worse [17,63]. Therefore, for hih spectral purity, the output sinal in the 1st Nyquist ban an primary LO output ban shoul be use as the output of the Mixin-DAC.

50 36 Chapter 3. Architecture classification an synthesis Low frequency mixer input sinal (BB) The other input of the mixer function is the baseban sinal. The characteristics of the baseban (BB) mixer input sinal can be ivie in two subsets: amplitue an frequency characteristics. The amplitue characteristics are subivie into resolution an polarity characteristics Amplitue - resolution When the resolution of the BB sinal is hih, mixin is applie to the combine DAC output, i.e. lobal mixin. When the resolution of the BB sinal is 1 bit, mixin is applie locally to each DAC unit cell separately, i.e. local mixin. Examples of lobal an local mixin are shown in Fiure 3.4 an Fiure 3.5 respectively. An option in between lobal mixin an local mixin is subset mixin, where a subset of the outputs of the DAC 1-bit cells are combine before the mixin operation takes place. An example of subset mixin is shown in Fiure 3.6. V R L R L M 8 V out V out M 9 V c V b1 V b1 Vc LO I mixbias M 4 V b1 LO M 7 V b1 M 5 M 6 Data M 2 M 3 Data LO I mixbias V 2 V 1 M 1 M 0 Fiure 3.4: Global mixin an simultaneous operations; the architecture is synthesize base on the classification Avantaes an isavantaes of the various mixin locality options, an literature examples are iven in Table 3.4. Subset mixin oes not appear in open literature. For lobal mixin, a very linear mixer is require since the current throuh the mixer in Fiure 3.4 is ata epenent. However, a current commutin CMOS transistor is not very linear. When increasin the bias current throuh the mixer (I mixbias in Fiure 3.4), the ratio between ata-epenent current

51 3.4. Sinal level classification 37 V R L V out V out R L LO M 8 M 9 V c V b1 V b1 Vc M 5 V b1 LO M 6 V b1 M 4 M 7 Data Data M 2 M 3 V 2 M 1 LO V 1 M 0 Fiure 3.5: Local mixin an simultaneous operations; the architecture is synthesize base on the classification V R L R L V out V out LO M 8 M 9 V c V b1 V b1 Vc V b1 LO V b1 M 4 M 5 M 6 M 7 LO Data M 2 M 3 Data V 2 V 1 M 1 M 0 Fiure 3.6: Subset mixin an simultaneous operations; the architecture is synthesize base on the classification

52 38 Chapter 3. Architecture classification an synthesis an ata-inepenent current ecreases, which increases the linearity at the expense of power consumption. For local mixin, the current throuh the mixer only contains binary information, hence the linearity of the mixer is not important. However, mismatch between the numerous local mixers, i.e. mismatch in the LO sinal timin or mismatch of the mix transistors (M 4 -M 7 in Fiure 3.4), can erae the linearity of the Mixin-DAC. This effect is similar to timin errors in traitional baseban DACs, iscusse in [64]. The chip layout of a Mixin-DAC with local mixin is expecte to be more complex than with lobal mixin, since local mixin requires mixin transistors for each current cell an the routin of the LO sinal to each current cell. A more complex layout can result in more unesire couplin between sinals. The avantaes an isavantaes of subset mixin larely epen on the specific implementation. Subset mixin has a better mismatch sensitivity than local mixin. However, mixer linearity is a concern in subset mixin, since the current throuh the mixer is sinal epenent. Subset mixin will a layout complexity since the layout oes not have the reularity of local or lobal mixin. The qualitative analysis of the ifferences between lobal mixin an local mixin oes not ive a clear view on which option is better for hih spectral purity. Therefore, Chapter 5 an Chapter 6 iscuss a quantitative analysis of the ifferences between these two options Amplitue - polarity Almost all Mixin-DAC s employ Symetric aroun Zero (SaZ) sinalin for the BB mixer input since there is no avantae in usin Return to Zero (RZ) sinalin. This RZ sinalin is not to be mistaken for the RZ mixin of the LO sinal, the avantaes an isavantaes or which are iscusse in Section The ifference between the polarity of the LO sinal an the polarity of the BB sinal are visualize in Fiure 3.7. RZ is only use when the architecture oes not allow SaZ sinalin because the chosen architecture is completely sinle ene[54]. Section iscusses the sinal balancin Frequency The sample rate of the BB mixer input influences the spectral content relate to the term K F S in (3.1). These spectral components are usually unesire an can be filtere out. When these spectral components are filtere

53 3.4. Sinal level classification 39 Table 3.4: Examples of Mixin-DAC architectures for all three classes of mixin locality Mixin locality Local mixin Subset mixin Global mixin Example Current source mixin [5,10,11,13] Gilbert current cell mixin [8,9,18 22,30,31,40,51] Sinle-ene squarewave mixin [54 56] Semi-ifferential square-wave current source mixin [57] Direct conversion [48] Two step conversion[52, 59] Combine output mixin [12,58] Characteristics Avantae: insensitive to mixin transistor non-linearity. Disavantaes: sensitive to mixin transistor mismatch, larer chip area. Characteristics between local mixin an lobal mixin. Avantaes: insensitive to mixin transistor mismatch, smaller chip area Disavantae: sensitive to mixin transistor non-linearity. SaZ baseban (BB) sinal RZ baseban (BB) sinal RZ LO sinal SaZ LO sinal Ampl Ampl time time Ampl Ampl time time Fiure 3.7: Mixin-DAC output sinal, inicatin the ifference between BB polarity an LO polarity, with BB sinal in analo omain (lobal mixin)

54 40 Chapter 3. Architecture classification an synthesis out between the D/A conversion an the mixin operation, the sample rate F S of the BB sinal can be chosen freely. However, when no intermeiate filterin is present, or when this filterin is not possible (e.. cascoe mixin, see Section 3.5.2), F S shoul be an inteer value of the LO sinal frequency f LO : F LO = n F S, n Z. (3.2) This synchronization is necessary to alin the LO an BB transitions, an to alin the BB spectrum repetitions, relate to M > 1 an K > 0 in (3.1), in the output spectrum. The avantae of a low sample rate is the low istortion ue to timin errors [64]. The avantaes of hih sample rate inclue: low noise floor ue to clock jitter[64], low quantization noise floor, lare Nyquist banwith, an lare separation between the main output sinal an the imae in the secon Nyquist ban. The choice for a certain sample rate is also influence by the positionin of the harmonic istortion components. 3.5 Implementation level classification At the implementation level, four ifferent aspects are istinuishe: balancin of the sinals, sequence of the DAC an mixin operation, locality of mixin, an the usae of the mixin transistors Sinal balancin The two main sinals in the Mixin-DAC (BB an LO) can both be implemente with sinle ene sinalin, ifferential sinalin or quasi-ifferential sinalin[28]. Table 3.5 ives examples of Mixin-DAC architectures with ifferent combinations of sinal balancin. The various combinations are: both sinals ifferential ( Fully ifferential ), one sinal ifferential an one sinal sinle ene ( Partially sinle-ene ), both sinals sinle ene ( Sinle ene ), an combinin two sinle ene Mixin-DACs to enerate a ifferential-like sinal ( Quasi-ifferential ) Reference current Fully ifferential CS Mixin-DACs can use a reference current source which is always on. This enables the use of a lare area which results in a hih accuracy. In sinle-ene Mixin-DACs, the reference is switche on an off,

55 3.5. Implementation level classification 41 Table 3.5: Examples of Mixin-DAC architectures classifie accorin to balancin of sinals Sinal balancin Fully ifferential Partially sinleene Sinleene Quasiifferential Example Gilbert current cell mixin [8,9,18 22,30,31,40,51] Two step conversion [52, 59] Direct conversion [48] Combine output mixin [12,58] Sine-wave RZ current source mixin [5,10,11, 13] Semi-ifferential square-wave current source mixin [57] Sinle-ene squarewave mixin [54 56] Quasi-ifferential mixin [28] Characteristics Avantaes: insensitivity to common moe isturbances, low control sinal feethrouh, suppression of even orer harmonic istortion, unisturbe power supply current. Disavantae: possibly larer chip area, low enery efficiency Avantaes: moerate enery efficiency, partially insensitive to common moe isturbances, partial suppression of even orer harmonic istortion Disavantae: output sinal contains lare common-moe part Avantaes: hih enery efficiency Disavantae: interface mismatch with ifferential circuits later in the sinal chain Avantaes: hih enery efficiency, partially insensitive to common moe isturbances, partial suppression of even orer harmonic istortion Disavantae: output sinal contains lare common moe part an hence must occupy a small area to enable fast switchin. This small area results in a low accuracy, which eraes the linearity. Also quasi-ifferential sinalin uses a switche references, which nees to have a small area which results in a low accuracy.

56 42 Chapter 3. Architecture classification an synthesis Disturbance When a certain sinal is implemente with ifferential sinalin, an both wires are close toether in layout, most isturbances equally couple to both sinals. This common isturbance is attenuate by the followin block in the sinal chain, provie it has a hih Common Moe Rejection Ratio (CMRR). With a sinle ene sinal, isturbances are irectly ae to the sinal. Applyin this to the Mixin-DAC, it can be arue that when both input sinals are implemente with ifferential sinalin (fully ifferential sinalin), isturbances at the Mixin-DAC output are minimize. When one of the two sinals is sinle ene, or when the Mixin-DAC is completely sinle-ene, the Mixin-DAC is most sensitive to isturbances, since each isturbance irectly couples to the output sinal. With quasi-ifferential sinalin, both sinals partially receive the same isturbance, epenin on the spatial separation. However, the isturbance sensitivity is hiher than for ifferential sinalin since the two sinals are usually not as close as ifferential sinalin, an there is no common reference Even-orer harmonics Another avantae of ifferential sinalin is the suppression of even orer harmonic istortion. For the LO sinal, even orer harmonics only influence sinal frequencies far outsie the ban of interest. However, for the BB sinal, the frequency of the secon orer harmonic is close to the sinal ban an hence must be as low as possible. The actual suppression of even orer harmonic istortion epens on the matchin of the two paths of the ifferential sinals. Partial sinle ene sinalin an quasi-ifferential sinalin exhibit partial secon-orer istortion cancellation, epenin on the specific implementation Sinal feethrouh For some fully ifferential circuits with ifferential control sinals, the feethrouh of the input sinals to the output partially cancel. For instance, a fully ifferential Gilbert cell mixer sinificantly reuces the couplin between the LO sinal an the output with respect to a sinle-ene mixer. For full cancellation, matchin of the ifferential sinal paths is require. (Partially) sinle ene sinalin an quasi-ifferential sinalin o not offer input sinal feethrouh cancellation.

57 3.5. Implementation level classification Data-epenent power consumption The power consumption of (partially) sinle ene sinalin an quasiifferential sinalin is epenent on the input sinals. This causes inputepenent voltae rop (i.e. IR-rop) over the power supply connections, which can couple back to output stae an causes harmonic istortion in the Mixin-DAC output sinal. Fully ifferential sinalin results in a constant power consumption, an hence the aforementione couplin path oes not cause harmonic istortion Chip area Sinle ene circuits require less active components than ifferential structures, hence the active chip area of a sinle ene Mixin-DAC can be less. However, sinle ene sinalin will require more ecouplin capacitance than ifferential sinalin on the supply noes to filter the aforementione input-epenent isturbance, which increases the chip area. The actual amount of require chip area epens on a number of factors an is specific for each architecture an implementation. Quasi-ifferential sinalin requires approximately the same chip area as ifferential sinalin, ue to the ouble sinal paths. The larer active area of the active circuits an the ouble wirin of a ifferential solution usually results in hiher parasitic capacitances. An example of this is the ouble output capacitance of a ouble balance Gilbert cell mixer in comparison with a sinle balance Gilbert cell mixer. This results in a hiher power consumption or lower maximum frequency of ifferential circuits Output sinal Almost all RF circuits require ifferential input sinals, hence the Mixin- DAC shoul prouce such a sinal. A fully sinle ene circuit cannot prouce a ifferential output sinal without aitional circuitry, e.. a balun. A partial sinle ene or quasi-ifferential Mixin-DAC has a positive an neative output terminal, but oes not prouce a true ifferential output sinal. Instea, the common moe of the output sinal is equal to half the manitue of the ifferential output sinal[13]. This output sinal behavior is not always acceptable for RF applications. Only fully ifferential sinalin prouces a true ifferential output sinal without a lare common-moe component.

58 44 Chapter 3. Architecture classification an synthesis Efficiency An avantae of sinle ene structures is that the power consumption of the Mixin-DAC output stae scales with the power of the sinal, when polar sinalin is use, see Section For I/Q sinalin, the power consumption of a sinle-ene Mixin-DAC is half of the power consumption of a ifferential Mixin-DAC, ue to the DC level which is present in the BB input sinal. The power consumption of quasi-ifferential sinalin is similar to the power consumption of sinle-ene sinalin Conclusion For hih spectral purity, the sensitivity of the Mixin-DAC to isturbances must be minimize, while power consumption is a seconary consieration. Therefore, fully ifferential sinalin shoul be use for hih spectral purity Sequence of operations The sequence of the two operations in the Mixin-DAC (i.e. mixin an iital to analo conversion) can be chosen freely. The two operations can be one cascae (mixin before the D/A conversion, or mixin after the D/A conversion), or cascoe. Cascoe mixin an D/A conversion can be one in the same current path (e.. traitional Gilbert current-cell mixin of for instance Fiure 3.5) or usin a fole cascoe structure (e.. fole Gilbert-cell Mixin-DAC, propose in Fiure 3.8). V V f M 8 M 9 Vf Data M 2 M 3 Data LO V b1 LO V b1 LO M 4 M M 5 M 6 7 V 2 V 1 M 1 M 0 V out R L V out R L Fiure 3.8: Mixin-DAC architecture with local mixin, simultaneous mixin an DA conversion with fole structure; the architecture is synthesize base on the classification

59 3.5. Implementation level classification 45 The choice for the sequence of D/A conversion an mixin operation, an the previously iscusse choice for BB mixer input resolution (i.e. mixin locality, see Section ) are interepenent. Fiure 3.9 raphically shows this interepenence. For example: lobal mixin is not available with the cascae mixin -> D/A conversion sequence. Mixin locality Cascae, Mixin -> D/A Local mixin Sequence of operations Cascoe Global mixin Cascae, D/A -> Mixin Fiure 3.9: Choices for mixin locality an sequence of operations are interepenent Examples for the classification base on the sequence of mixin an DAC operation in the Mixin-DAC are iven in Table 3.6. The main ifference between the various operations sequences is the presence or absence of an analo voltae-to-current (V-I) an a current-tovoltae (I-V) conversion Cascae: DAC before mixin An I-V conversion usin a MOST is a non-linear operation. 1-bit sinals remain unistorte by efinition when passin a non-linear operation while analo sinals are istorte. Therefore, the linearity of analo mixers is limite an hence D/A -> mixin sequence results in a non-linear mixin operation [6]. Applyin mixin after the D/A conversion enables the use of an analo reconstruction filter between the DAC an mixer. This filter can remove the unesire sinal imaes associate with K 0 in (3.1) an reuces the requirements of the RF filter after the Mixin-DAC Cascae: mixin before DAC In cascae Mixin -> D/A, mixin is one on 1-bit sinals, hence a hih linearity can be achieve. This iital mixin requires a DAC core which is capable of proucin at least 8GSps for a 4GHz RF output, which is a very hih spee for the require linearity. Known problems with hih linearity DACs at hih frequency are the ata-epenent output impeance[65], ranom timin errors ue to mismatch [64] an inter-symbolinterference.

60 46 Chapter 3. Architecture classification an synthesis Table 3.6: Classification of Mixin-DAC architectures base on sequence of the operations mixin an DAC Sequence Example Cascae: mixin before DAC square-wave Cascae: DAC before Mixin Sinle-ene squarewave mixin [54 56] Semi-ifferential current source mixin [57] Direct conversion [48] Quantize sine-wave two step conversion[52] Conventional two step conversion [59] Cascoe Sine-wave RZ current source mixin [5,10,11, 13] Gilbert current cell mixin [8,9,18 22,30,31,40,51] Combine output mixin [12,58] Characteristics Avantaes: no mixin sinal feethrouh to output because of mixin in iital omain, compatible with moern CMOS process technoloies because of mixin in iital omain, possibility of intermeiate filterin. Disavantaes: hiher power consumption because of twostae conversion, iital mixin reuces possibility of hih output frequency Avantaes: possibility of intermeiate filterin. Disavantaes: hiher power consumption because of twostae conversion. Avantaes: no linearity eraation ue to multiple staes in sinal path, low power consumption. Disavantaes: no possibility of intermeiate filterin, reuce current cell voltae hearoom. Timin errors are an important consieration in iital mixin. Mixin to the RF frequency can be one anywhere in the iital sinal chain, ranin from the Mixin-DAC ata input sinal to the Mixin-DAC river stae. Implementin the latter option results in a novel architecture which is propose in Fiure The potentially lare mismatch in the RC time constant of the Mixe noes causes timin errors. These timin errors will introuce non-linear istortion an limit the spectral purity. The manitue of the non-linearity ue to the timin errors requires quantitative analysis, which is iscusse in Chapter 6.

61 3.5. Implementation level classification 47 V 2 R L V out R L Vout V 1 R D R D V c M 4 M 5 Vc LO M3 M4 LO M5 M6 LO Mixe C D M 2 M3 Mixe Data M 1 M 2 Data V 2 M 1 V 1 M 0 Driver C D V 1 M 0 Fiure 3.10: Diital mixin in the river with fully ifferential, current steerin DAC structure; the architecture is synthesize base on the classification Applyin iital mixin early in the sinal chain enables iital filterin an iital I/Q combinin, as oppose to mixin in the river or later in the sinal chain. Filterin in the iital omain reuces the requirements on analo RF filterin. However, iital filterin of the upconverte RF sinal requires aitional iital harware. Diital filterin at the RF frequency can be very costly in terms of power when the RF output frequency is hih. However, with newer CMOS process technoloies, iital operations are becomin cheaper in terms of power consumption an chip area. I/Q combinin (see Section 3.3.2) in the iital omain is accurate an oes not suffer from the mismatch in I/Q combinin or LO leakae of analo I/Q combinin Cascoe Cascoe mixin an DAC offers a choice in mixin locality. Section shows that both lobal an local mixin have avantaes an isavantaes. This is further iscusse in Chapter 5. Cascoe operations with the traitional Gilbert-cell mixin has the isavantae that it requires aitional voltae hearoom with respect to a CS DAC, ue to the transistors which implement the aitional mixin function. Two exceptions are the use of the current source transistor as the mixer [5], or usin a fole structure. Mixin usin the current source is limite in spee

62 48 Chapter 3. Architecture classification an synthesis or accuracy, epenin on the size of the current source transistor. Cascoe operations with the fole Gilbert-cell mixin has the isavantae that it has a hiher current consumption ue to the aitional current path throuh the fole mixer path, with respect to the CS DAC Conclusion The three options for the sequence of mixin an D/A conversion are iscusse in the previous sections. Cascae operations with mixin after D/A conversion has an analo I/V an V/I conversion which results in severe non-linear istortion. Cascae operations with D/A conversion after mixin is sensitive to timin errors, but eterminin its manitue requires further quantitative analysis, which is iscusse in Chapter 4 an Chapter 6. Cascoe mixin an D/A conversion is sensitive to non-linear mixin or timin errors, epenin on the mixin locality. Determinin the actual manitue of the resultin nonlinear istortion also requires further quantitative analysis, which is iscusse in Chapter 4 an Chapter Transistor usae When usin a current commutatin transistor as a mixer, two ifferent usae scenarios are available with respect to the LO an BB sinals, see Fiure Out Out LO LO BB BB BB LO (a) (b) Fiure 3.11: Difference between options of transistor usae: BB current throuh transistor(a) an LO current throuh transistor(b) One option is to supply the ate of the mix transistor with the LO sinal an put the BB sinal in the current throuh the mixer, see Fiure 3.11(a). An example of this mixin confiuration is propose in Fiure 3.5. The other option is to supply the ate of the mix transistor with the BB sinal an put the LO sinal in the current throuh the mixer, see Fiure 3.11(b). This option is available for two architectures types. The first architecture is iital mixin, imaine Fiure 3.10 but with swappe LO an Data connections. The secon architecture roup is when mixin an

63 3.6. Conclusion 49 DAC conversion are execute cascoe in the output stae an local mixin is applie, imaine Fiure 3.5 but with swappe Data an LO sinals, or mixin in the current sources [5]. Fiure 3.11(b) shows that when the current throuh the mixer is at a hih frequency, the source noe of the mixer transistor contains hih frequency voltae swin. For charin an ischarin the parasitic capacitance at that noe, sinal current is use. Simulations have shown that the power loss can be as lare as 1.5B compare to the other transistor usae option. Simulations of the Gilbert cell Mixin-DAC base on Fiure 3.5 o not show a linearity ifference between the two transistor usae scenarios, but output power ifference is present. Therefore, the LO ate option is chosen althouh there is no avantae in spectral purity. An overview of the classification base on transistor usae is iven in Table 3.7. Table 3.7: Classification of Mixin-DAC architectures base on transistor usae Usae Example Characteristics BB ate Sine-wave RZ current source mixin [5,10,11, 13] Combine output mixin [12, 58] Gilbert cell mixin [18 22, 40] Disavantae: lower output power. LO ate Gilbert cell mixin [8, 9,30,31,51] Avantae: hiher output power. 3.6 Conclusion The propose systematic analysis an classification of Mixin-DAC architectures reveals the most crucial architecture choices, when hih frequency hih spectral purity is consiere. The sequence of mixin an D/A operation an the resolution of mixin sinals are important architectural choices that stronly etermine the linearity of a Mixin-DAC architecture. For hih spectral purity at GHz frequencies, the followin characteristics are optimal: current-steerin principle, Cartesian sinalin, square-wave mixin, symmetric aroun zero sinalin for the LO an ata sinal, fully ifferential an LO-ate transistor usae. The best mixin-locality option epens on the manitue of the mixer non-linearity an the timin errors

64 50 Chapter 3. Architecture classification an synthesis for lobal mixin an local mixin respectively. The best sequence of mixin an D/A conversion operations also epens on the impact of timin errors. However, mixin after the D/A conversion is expecte to result in a poor linearity. These uncertainties require aitional quantitative analysis, which will be iscusse in the next chapter. With the presente analysis of Mixin-DAC architectures, esiners an researchers now have a clear insiht on the impact of architectural choices on the spectral purity of the Mixin-DAC output sinal.

65 4 Promisin architectures The precein classification of Mixin-DAC architectures ientifies a number of characteristics of a Mixin-DAC which are expecte to enable the best spectral purity. This leas to three promisin architectures, which require aitional quantitative analysis. In the classification, the trae-off between various architectures was virtually technoloy-inepenent. But for the analysis of timin errors an mixer linearity, 65nm CMOS is assume to be the implementin process technoloy. However, the analysis can be extene to other process technoloies. 4.1 Introuction The top level view of the synthesis of the most optimal architecture is shown in Fiure 4.1. All possible architectures are consiere. First, the classification is use to analyze which choices for all architectural aspects result in an architecture which is suitable for wie-ban sinals an is expecte to lea to hih spectral purity. These architectural choices are: currentsteerin principle, Cartesian sinalin, square-wave mixin, symmetric aroun zero sinalin for the LO an ata sinal, fully ifferential an LO-ate transistor usae. However, there are also architectural aspects which require further analysis. These architectural aspects are further analyze usin process information, which leas to a most optimal architecture. 4.2 Classification uncertainties The previous chapter ientifies two architectural choices which nee further analysis: mixin locality an sequence of operations. Mixin locality efines if mixin is one locally in each current cell or lobally on the combine output of the current cells, see Section Both local mixin an lobal mixin coul result in a hih linearity. For lobal

66 52 Chapter 4. Promisin architectures All architectures Classification: Chapter 3 Wie-ban & hih spectral purity Promisin architectures: A: cascoe lobal mixin B: cascoe local mixin C: iital mixin Technoloy: CMOS 65nm C A B Wie-ban & hih spectral purity Chapter 4 Chapter 5-10 Optimal architecture: Fiure 4.1: Process to synthesize a promisin Mixin-DAC architecture mixin, the linearity of the mixer is crucial. For local mixin, mismatch between the local mixers introuces non-linearity. The manitue of both effects epens on the implementation an on the sequence of the mixin an D/A conversion, an requires quantitative analysis. The sequence of the two Mixin-DAC operations (D/A conversion an mixin) etermines the orer in which these two operations take place. Three options can be istinuishe: cascae DAC before mixin, cascae mixin before DAC an cascoe operations, see Section Main ifference between these two options is the presence or absence of V-I an I-V conversions. Cascae DAC before mixin is expecte to prouce lare non-linearities ue to an analo V-I an I-V conversion. Hence, only cascoe operations an cascae mixin before DAC can result in a hih linearity. 4.3 Architecture synthesis Combinin the two options for the two architectural choices of the previous section, three promisin architectures can be synthesize. These architectures are: cascoe lobal mixin, see Fiure 3.4, cascoe local mixin, see Fiure 3.5, iital mixin, see Fiure The trae-off in the mixin locality between cascoe lobal mixin an cascoe local mixin is iscusse in Chapter 5. The trae-off in the sequence of mixin an D/A conversion between cascoe local mixin an iital mixin is iscusse in Chapter 6.

67 4.4. Other architecture consierations Other architecture consierations Other important aspects of a CS Mixin-DAC architecture are: amplitue errors an sementation. Amplitue errors between the current source of the current cells result in non-linearity in the transfer characteristics [7]. Chapter 8 presents a calibration metho which is especially aime at (Mixin-)DACs at hih frequencies an with hih robustness. The trae-off for the sementation of the Mixin-DAC is a complex problem. A theoretical framework for the sementation of Nyquist DACs is publishe in [66]. However, that work is focuse at low-frequency characteristics, i.e. INL an DNL. For Mixin-DACs, ynamic characteristics are much more important, e.. IMD an SFDR. Therefore, a sementation trae-off for hih frequency Mixin-DACs is iscusse in Chapter Conclusion The classification ientifies two architectural choices which nee further analysis: mixin locality an sequence of operations. Combinin these architectural choices results in three promisin Mixin-DAC architectures: cascoe lobal mixin, cascoe local mixin an iital mixin. These architectures require quantitative analysis, which is iscusse in the followin chapters. The analysis of amplitue errors an sementation is important, which is also iscusse in the next chapters.

68

69 5 Mixin locality The previous chapter iscusse that the mixin locality is an important trae-off in the architecture synthesis of a Mixin-DAC with hih spectral purity. Local mixin is sensitive to mismatch between the local mixer in each current cell. Global mixin requires a linear mixer. Base on an estimation of parasitic capacitances on the most sensitive noes, lobal mixin is shown to offer a lower linearity than local mixin. It is also shown that local mixin requires an output cascoe in each current cell to sufficiently isolate the internal noes from the lare output voltae swin. An alternative to the output cascoe is an output transformer, which is iscusse in Chapter 7 This chapter is base on a paper publishe in the proceeins of the IEEE ISCAS 2012 conference [85]. 5.1 Introuction Numerous error sources that limit the Mixin-DAC linearity exist. Simulations show that the mixin locality has a major impact on the linearity. This mixin locality is also iscusse in Section Two main options for mixin locality are istinuishe: lobal mixin an local mixin, see Fiure 5.1. In lobal mixin, the output sinals of the unit DAC functions are first combine before bein mixe. When implementin lobal mixin with transistors, the non-linearity of the transistor results in a non-linear mixin function. When local mixin is use, the mixin is execute insie the DAC unit cells before the sinals are combine. These unit cells contain only 1-bit sinals, hence the mixin operation is inherently linear even if real transistors are use. However, mismatch between the mixin operation in the unit cells can eteriorate the linearity of the Mixin-DAC. A thir option for mixin locality is subset mixin. With subset mixin, a subset of the DAC unit element output sinal is combine before the mixin

70 56 Chapter 5. Mixin locality Data N bits Data N bits Coin transform Coin transform 1 bit 1 bit D/A D/A D/A D/A D/A D/A D/A D/A LO LO RF (a) RF (b) Fiure 5.1: General moel of lobal mixin (a) an local mixin (b) operation is applie, see Fiure 3.6 in Section The linearity of subset mixin larely epens on the implementation an the error sources are a combination of the error sources of local mixin an lobal mixin. Therefore, this thir option is not iscusse separately. 5.2 Analysis an simulations For the analysis of the two mixin locality options, a specific implementation is assume: a 65nm 1.2V/3.3V CMOS process with thin-oxie an thickoxie transistors. However, the analysis can be extene to other process technoloies. Since hih linearity DACs are usually implemente as Current Steerin(CS) DACs, the Mixin-DAC uner investiation is chosen to be a CS Mixin-DAC. The simplifie schematics of a CS Mixin-DAC with lobal mixin an local mixin are shown in Fiure 5.2(a) an Fiure 5.2(b) respectively Table 5.1 summarizes the most important error sources of the CS Mixin- DAC which lea to non-linearity. The followin subsections systematically analyze each error source separately, usin the corresponin ientification number in Table 5.1 an Fiure 5.2. Unless otherwise inicate, simulations use the followin simulation setup. The loa resistors (R L ) are 25Ω (50Ω ouble terminate) each an the maximum output current is 20mA, eneratin a ifferential output-sinal amplitue of 1V PP. The input sinal is a two-tone full scale sinal at f in1 =150MHz an f in2 =165MHz. Toether with a mixin sinal frequency (f LO ) of 4.02GHz, the resultin output sinal

71 5.2. Analysis an simulations 57 V R L V out LO V b LO M 4 3 C M 5 M 6 I 6 cs mixbias V out 2 R b V b R L 1 C LO M7 I mixbias Data 7 M 2 M 3 9 C cs V 2 M 1 8 Data V 1 M 0 (a) V R L R L V out V out LO I blee V b LO M 4 5 C M 5 M cs Rb V b 1 C M7 I blee LO Data M 2 M 3 Data V 2 9 M 1 C cs 8 V 1 M 0 (b) Fiure 5.2: Transistor moel of two options for mixin locality: lobal mixin (a) an local mixin (b)

72 58 Chapter 5. Mixin locality Output effects Global mixin Local mixin Table 5.1: Mixin-DAC error sources leain to non-linearity # Description 1 Non-linear C combine with output voltae swin 2 Non-linear R b combine with output voltae swin 3 Mixer input-current epenent mixin 4 Mixer ata-epenent timin errors 5 C cs combine with the output-voltae epenent settlin of the mixer common source noes after ata switchin Common 6 Common-source noe isturbance ue to LO transition DAC effects combine with C cs, epenent on output voltae swin 7 Data timin errors 8 Disturbance ue to ata switchin combine with C cs 9 Mismatch between output current of current sources frequencies (f out ) are 4.17GHz an 4.19GHz. In the simulations, the IMD3 of the output sinal is use as a measure for the linearity Output effects For isolatin the Mixin-DAC non-linear output effects in simulation, the simulation setup of Fiure 5.3(a) is use. An ieal Mixin-DAC output sinal is enerate by I out an R L, while M 1 an M 2 moel the output non-linearity of a Mixin-DAC. A sweep over the output common moe voltae (V out c ) for various values of the output sinal frequency (f out ) is use to show the effect of the output non-linearities, see Fiure 5.3. This simulation clearly shows that an IMD3 of -85Bc at 4GHz is achievable with CMOS output transistors. The most limitin output effects are: ate-rain capacitance an rainbulk leakae (error sources 1 an 2 in Table 5.1 an Fiure 5.2). These two effects mainly epen on V out c, f out an output sinal voltae swin Specific lobal mixin non-linearities In the lobal mixin simulation moel, only transistors M 4 to M 7 of Fiure 5.2(a) are real transistors. The other parts of the Mixin-DAC are implemente in Verilo-A. Global mixin suffers from non-linearity errors ue to the ata-epenent current throuh the mixin transistors (error source 3). Global mixin can

73 5.2. Analysis an simulations 59 V out_c R L I c I c R L V out 2 1 Rb C V b V M 1 1 C 2 R b V M b 2 V out I out I c I c I out (a) IMD3 [Bc] f out = 4.02GHz f out = 1.00GHz f out = 252MHz R b 100 C V out_c V [V] (b) Fiure 5.3: Output effect simulation: circuit (a) an simulation results (b) be linearize by optimizin the ratio between sinal current an bias current, hence by ain bias current throuh the mixer (I mixbias in Fiure 5.2(a)) Fiure 5.4 shows the IMD3 epenence on I mixbias. For equal bias voltae levels at each noe, increasin I mixbias also means increases the size of the mixin transistors, which increases the output-relate non-linearity. Therefore, there is a maximum achievable IMD3 for lobal mixin which is -82Bc (see Fiure 5.4). This is worse than the require -85Bc Specific local mixin non-linearities In the simulation moel of the local Mixin-DAC, only transistors M 4 to M 7 of Fiure 5.2(b) are real transistors, the other Mixin-DAC parts are

74 60 Chapter 5. Mixin locality IMD3 [Bc] Mixin effect Output effects ImixBias [ma] Fiure 5.4: With lobal mixin, the mixin operation linearity epens on the ae bias current implemente usin Verilo-A. The current throuh a mixer transistor pair (e.. M 4 -M 5 ) exhibits a lare step if the input coe of the corresponin ata transistor (e.. M 2 ) chanes. This enerates a lare voltae step at the mixer common source noe V cs. The settlin behavior of the V cs step epens on the output voltae (error source 5), which introuces a error chare on the parasitic capacitance C cs. By optimizin I blee, this error source can be minimize. Threshol voltae mismatch of the mixin transistors causes timin errors in the mixin operation between current cells, eneratin non-linearity (error source 4). A more elaborate iscussion of the nature of the timin errors in a local Mixin-DAC is iven in Chapter 6. The results of a Monte Carlo (MC) mismatch simulation are shown in Fiure 5.5. In this simulation the transition time of the LO waveform is 50ps an R L is chosen very small (0.25Ω) to isolate the mismatch non-linearity. The simulate stanar eviation of the timin errors is approximately 0.8ps. In the corresponin IMD3 istribution, 99% of all IMD3 results is better than -93Bc. Therefore, it is conclue that the LO timin errors o not erae the ynamic linearity of the CS Mixin-DAC below the require IMD3=-85Bc. The timin errors ue to imperfect sinal routin are assume to be neliible an hence are not taken into account Common mixin non-linearities Both local an lobal mixin are very sensitive to capacitance C cs at the common source noe of the mixer (error source 6). Durin an LO transition a isturbance occurs at the common source noe of the mixer transistors. The size of this isturbance is epenent on the Mixin-DAC input sinal,

75 5.2. Analysis an simulations 61 IMD3 [Bc] # occurrences Timin error [ps] Fiure 5.5: Monte Carlo mismatch simulation: istribution of timin errors between two current cells an resultin IMD3 istribution eneratin non-linear istortion. For local mixin, this ata epenence oriinates from the finite isolation between the output voltae swin an the mixer common-source noe. For lobal mixin, the sinal current throuh the mixer causes the above mentione ata-epenence. Fiure 5.6 shows the IMD3 epenence on the value of C cs. In this simulation, the same moels as iven in Section an are use. Realistic values for C cs are 10-20fF for local mixin an 1-2pF for lobal mixin. In those reions, the linearity of the Mixin-DAC is reuce to IMD3=-72Bc, which is much worse than the require -85Bc DAC non-iealities Non-linearities specifically relate to the DAC function (e.. error sources 7-9) are not iscusse in this chapter. Other authors have extensively iscusse these effects [61, 64][87, 88]. Moreover, the DAC-function nonlinearities are common to lobal mixin an local mixin Output cascoe For local mixin, the isolation between the output sinal an the mixer common source noe can be increase by ain a local output cascoe to each cell. Fiure 5.7 shows the schematic of a local Mixin-DAC with output cascoe. Careful biasin ensures all transistors o not excee their maximum

76 62 Chapter 5. Mixin locality IMD3 [Bc] Local mixin: Ccs [ff] Global mixin Local mixin Expecte values Global mixin: Ccs [ff] Fiure 5.6: Sensitivity of mixin linearity to capacitance at the mixer common-source noe, without output cascoe operatin conitions. The new IMD3 epenence on mixer common source noe capacitance is simulate usin a simulation moel where only M 4 -M 9 are real transistors. The results are shown in Fiure 5.8. It can be seen that the simulate performance is improve to IMD3=-92Bc. The isolation between the output an internal noes can also be implemente usin an output transformer, which is further iscusse in Chapter 7. Usin a simulation moel where all Mixin-DAC current cell transistors (M 0 -M 9 ) are real transistors an assumin realistic wirin capacitances, the IMD3 is -88Bc, achievin the esire linearity. For lobal mixin, ain aitional isolation between the output an the mixer common-source noe oes not improve the linearity, since the C cs epenent non-linearity in lobal mixin is ue to the ata epenent current throuh the mixer. Fiure 5.8 confirms this claim, where the expecte IMD3 value is -75Bc. 5.3 Conclusion For hih linearity Mixin-DACs, mixin locality is a major concern. For a current steerin Mixin-DAC, the impact of the capacitance at the mixer common-source noe (C cs ) ominates the Intermoulation Distortion (IMD) performance. For lobal mixin, this error source cannot be prevente. For local mixin, the IMD eraation ue to C cs oriinates from couplin

77 5.3. Conclusion 63 V R L V out V out R L LO M V 8 c V V b1 b1 Vc M 9 M 6 V b1 LO V b1 M 4 M M 7 5 I blee I blee LO Data M 2 Data M 3 V 2 V 1 M 1 M 0 Fiure 5.7: Local CS Mixin-DAC with local output cascoe IMD3 [Bc] Local mixin: Ccs [ff] Global mixin Local mixin Global mixin + output cascoe Local mixin + output cascoe Expecte values Global mixin: Ccs [ff] Fiure 5.8: Sensitivity of mixin linearity to capacitance at the mixer common-source noe, with an without output cascoe. from the mixer common-source noe to the output voltae. Implementin a local output cascoe reuces the sensitivity to C cs. The expecte IMD3 performance of the exemplary local mixin CS Mixin-DAC is <-88Bc at f out >4GHz output frequency, enablin the use of a Mixin-DAC for multicarrier GSM applications.

78

79 6 Timin errors The architecture classification in Chapter 3 ientifie mixin locality an the sequence of mixin an D/A conversion are important trae-offs. Chapter 5 emonstrates that local mixin is the most promisin mixin locality. In this chapter, the sequence of operations is investiate by comparin two architectures with local mixin: cascoe local mixin an cascae mixin before DAC (iital mixin). It is shown, that the impact of timin errors is ifferent for the two architectures. Cascoe local mixin has avantaeous characteristics with respect to its timin errors, but timin errors in iital mixin o cause a non-linear istortion that is much worse than in the case of cascoe local mixin. This chapter is base on part of a paper publishe at the IEEE ISCAS 2014 conference[83]. 6.1 Introuction A Current Steerin (CS) Mixin-DAC with local mixin (see Chapter 5) can be very linear if the responses of all 1-bit switche current sources(current cells) are uncorrelate an ientical, or ieally scale for binary current cells. For hih linearity at hih frequency, both timin an amplitue of the 1-bit cells shoul be consiere. The amplitue matchin in CS (Mixin-)DACs has been thorouhly researche, an many intrinsic an correction methos exist[67], for example the calibration metho propose in Chapter 8. However, the synthesis of a Mixin-DAC architecture with the focus on timin errors is not iscusse in open literature, while this is critical for achievin hih linearity at hih frequency. This chapter focuses on local mixin, since this architecture can suffer from timin errors, see Chapter 5. With local mixin, the timin synchronization between the current cells is important, since timin errors erae the linearity.

80 66 Chapter 6. Timin errors Current steerin Mixin-DACs preominantly use a semente implementation, with a unary scale MSB part an a binary scale LSB part. Without loss of enerality, the analysis in this chapter assumes a 16 bit Mixin-DAC withasementationof6bitunarymsban10bitbinarylsb,implementein 65nm CMOS. The presente analysis is also applicable to other sementations. The use sinal frequencies are: input frequency f in =150MHz, sample rate F S =1.95GSps an LO mixin frequency f LO =3.9GHz. Section 6.2 iscusses the characteristics of timin errors in a CS Mixin- DAC. Various architecture options are propose in Section 6.3. The timin errors on the three most important sinals in the Mixin-DAC are analyze in Section 6.4, Section 6.5 an Section 6.6. A comparison between the propose architectures is iscusse in Chapter Timin errors characteristics In CS Mixin-DACs, a semente approach results in the most optimal performance. For a full-scale sinal, the performance of the unary (MSB) part is most critical. Timin errors in the unary part are only ranomly istribute. No systematic timin errors are present since each cell is ientical. Ranom timin errors preominantly can occur in three sinals in the Mixin-DAC unit cells: Data input, LO input an the M ixe sinal (see Fiure 6.2 for Data an LO, an Fiure 6.4 for Mixe). Only timin error ifferences between the current cells are relevant since they lea to non-linear istortion. The timin errors are assume to be Gaussion istribute with zero mean. Two types of timin errors are consiere: elay timin errors an utycycle timin errors. An ieal perioic square waveform an the same waveform with timin errors are shown at the left of Fiure 6.1. The ifference between t waveform: spectrum: T s Delay: t t f s 3f s 5f s f Duty-cycle: t t 0 2f s 4f s f Fiure 6.1: Time omain an spectral characteristics of timin errors

81 6.3. Architecture options 67 the base waveform an the waveforms with timin errors, an the spectra of these ifferences, are also shown. For all practical values of the timin errors, the error spectrum of the -waveform with a elay timin error only contains o harmonics of the base frequency, an the uty-cycle error spectrum only contains even harmonics of the base waveform. This spectral ifference is important for the Mixin-DAC architecture analysis. For all practical sementations an for a full-scale sinal, the response of the MSB unary current cells etermines the performance. In this section the binary current cells are thus assume to be ieal. The next subsections iscuss possible Mixin-DAC architectures an the impact of timin errors at three noes in a Mixin-DAC: LO, Data an Mixe sinal. The value of the SFDR RB in a a 200MHz ban aroun f out =f LO +f in is use as a measure of the spectral purity. 6.3 Architecture options Two main Mixin-DAC architectures with local mixin, but with ifferent choices for the sequence of operations, are: cascoe local mixin an cascae mixin before DAC (iital mixin). Another eree of freeom is the locality of the LO river, which can be either lobal or local. Hence, in this chapter three Mixin-DAC architectures are compare: cascoe local mixin with lobal LO river, cascoe local mixin with local LO river, an iital mixin. For iital mixin, the choice of a local or lobal river oes not influence the results of the timin error analysis. Mixin-DAC architectures with cascoe local mixin with a lobal an local LO river, are shown in Fiure 6.2 an Fiure 6.3 respectively. For iital mixin, the mixin can be one in the river usin a mixin-river (see Fiure 6.4) or earlier in the iital sinal path. In this chapter, intrinsic timin error sensitivity of the three propose architectures is mutually compare. Numerous timin error calibration techniques for CS DACs exist [47,61][88] but they are not consiere since it is assume that they are equally applicable to all propose architectures. 6.4 Timin of Data sinal Timin errors in the Data input sinal are extensively iscusse in publications rearin CS DAC timin errors[47, 61, 64, 68][88]. The same conclusions an calibration techniques apply to all propose Mixin-DAC architectures, which is verifie with simulations. Therefore, Data timin errors have no influence on the architecture comparison.

82 68 Chapter 6. Timin errors V R L R L V out V out LO in LO LO M V 8 c V V b1 b1 Vc σ M 9 V b1 LO V b1 M 4 M 7 M I 5 M 6 blee I blee LO Data M 2 Data M 3 V 2 V 1 M 1 M 0 Fiure 6.2: Local Mixin-DAC architecture with annotate timin errors: output stae mixin with a sinle lobal LO river V R L R L V out V out LO in LO LO M V 8 c V V b1 b1 Vc σ M 9 σ V b1 LO V b1 LO M 4 M 7 M I 5 M 6 blee I blee Data M 2 Data M 3 V 2 V 1 M 1 M 0 Fiure 6.3: Local Mixin-DAC architecture with annotate timin errors: output stae mixin with local LO rivers

83 6.5. Timin of LO sinal 69 V out R L V 2 R L Vout R D LO M3 M4 V 1 LO M5 M6 Data M 1 M 2 Data R D σ LO V c M 4 M 5 Mixe M 2 M3 C D V 2 M 1 σ Vc Mixe V 1 M 0 Driver C D V 1 M 0 Fiure 6.4: Local Mixin-DAC architecture with annotate timin errors: propose example of mixin in the iital omain with mixin-river 6.5 Timin of LO sinal Sensitivity to LO timin errors is specific for Mixin-DACs. Fiure 6.5(a) shows the results of transistor level simulations of the circuit of Fiure 6.2 at f LO =3.9GHz, where the two types of timin errors are eliberately introuce in the LO input. Each current cell has its own inepenent ranom timin error, which is fixe for one trial of the Monte Carlo simulation. To isolate the nonlinear istortion ue to timin errors, other error sources are eliminate: R L 0 (to reuce output relate effects [85]), the rivers an current sources are moele with ieal components with realistic rive strenth an transition times. A 90% yiel SFDR RB of 85Bc at f LO =3.9GHz requires σ(elay)<55fs an σ(uty-cycle)<1.3ps. Hence, the Mixin-DAC is very sensitive to elay errors, but at least 20 times less sensitive to uty-cycle errors. The cause for the ifference in sensitivity to the two types of timin errors can be seen in Fiure 6.6, where two output spectra with ae elay an uty-cycle timin errors in the LO sinal are shown. The elay timin errors cause spurs aroun f LO (which is close to the output ban) while the uty-cycle timin errors create spurs aroun 2 f LO. This can be expecte, see Fiure 6.1, since the elay error spectrum contains enery at the funamental frequency (i.e. f LO ), while the uty-cycle error spectrum contains enery at ouble this frequency (i.e. 2 f LO ). With a sinle common LO sinal (i.e. a sinle lobal LO river, see

84 70 Chapter 6. Timin errors SFDR RBW [Bc] Delay sprea Duty cycle sprea Timin error stanar eviation [ps] (a) LO timin errors in Fiure 6.2 SFDR RBW [Bc] Delay sprea Duty cycle sprea Timin error stanar eviation [ps] (b) Mixe timin errors in Fiure 6.4 Fiure 6.5: Resultin SFDR RBo f timin errors (error bar=90%, #trials=20) Fiure 6.2) an output stae mixin, preominantly uty-cycle timin errors occur. The uty-cycle timin errors mainly oriinate from threshol mismatch an ain mismatch in the mixin transistors, M 4 -M 7 in Fiure 6.2. This can be verifie in the results of Monte Carlo mismatch simulations for the architecture of Fiure 6.2, which is shown in Fiure 6.7, where only the mixin transistors have mismatch. The mismatch-inuce timin errors are almost exclusively uty-cycle timin errors. The stanar eviation of each type of timin error are: σ(elay) =35fs an σ(uty-cycle) =0.92ps. These values are very close to the require values. The resultin 90% yiel SFDR RB is approximately 85Bc. A sinificant elay error can only oriinate from imperfect layout of the LO istribution or output recombination structure. Careful layout of the corresponin tree structures can reuce the expecte elay error to less than ±5fs. A local LO river, as propose in Fiure 6.3, introuces aitional utycycle timin errors an elay timin errors, which can easily excee 200fs, while <55fs is require.

85 6.6. Timin of Mixe sinal F LO f out =F LO +f in σ(elay)=1.0ps σ(uty cycle)=1.0ps Differential spectrum [Bc] F LO +F S 2 F LO Output frequency [GHz] Fiure 6.6: Schematic level simulation, comparin the spectral impact of elay an uty cycle timin errors Occurrences [%] Delay timin errors Duty cycle timin errors Timin error [ps] Fiure 6.7: Simulate LO timin errors ue to mixer mismatch 6.6 Timin of Mixe sinal Fiure 6.5(b) shows the results of a Monte Carlo transistor level simulation of the Mixin-DAC architecture with mixin-river of Fiure 6.4, where R L 0, an with ieal current sources, an ieal Data an LO rivers. In each current cell with mixin-river, a ranom timin error is eliberately introuce in the M ixe sinal (i.e. output of mixin-river). Aain, the performance is very sensitive to elay timin errors: σ(elay)<31fs for 90% yiel SFDR RB >85Bc.

86 72 Chapter 6. Timin errors Mismatch in the mixin-river, e.. in the current source (M 0 in Fiure 6.4), loa resistor value (R D ) or (parasitic) loa capacitance C D of the CML river, can enerate lare timin errors. Note that C D is not an intentional capacitor, but consists of the parasitic capacitance of the river transistors (M 3 -M 6 ), wirin an the switches in the output stae (M 2 an M 3 ). TheexemplaryimplementationoftheaforementioneMixin-DACwith iital mixin is simulate with mismatch in the value of R D an C D. The simulation results are presente in Table 6.1. The frequencies of the sinals are: 3.9GHz LO sinal an 160MHz an 175MHz ual-tone input ata at 1.95GS/s sample rate. Table 6.1: Simulate iital Mixin-DAC non-linearity ue to mismatch in the river RC-constant σ RC = 1% σ RC = 3% σ RC = 10% σ(elay) 87fs 0.26ps 0.87ps SFDR RB (90%) 76Bc 66Bc 56Bc The relationship between the 90% yiel SFDR RB value an the sprea in C D an R D is: SFDR RB (90%) 1/σ 2 RC (6.1) The physical positions of the R D s an C D s are sprea over a lare area, i.e. the complete output stae with which can be as wie as 1mm. Therefore, 3% mismatch estimation is realistic. A mismatch of 3% in R D C D results in a elay timin error of σ(elay)=0.26ps, while σ(elay)<31fs is require. The corresponin 90% yiel SFDR RB value of is -66Bc. Hence, mismatch in the local mixin-river alreay causes enouh timin errors to severely limit the spectral purity. 6.7 Architecture comparison A summary of the performance of cascoe local mixin an mixin in the river is iven in Table 6.2. Diital mixin with a mixin-river requires σ(elay)<31fs for a 90% yiel SFDR RB of85bc, while the expecte timin errors are much larer, leain to a inferior spectral purity. Cascoe local mixin (Fiure 6.2) requires: σ(elay)<31fs an σ(uty cycle)<1.3ps. Simulations show that these requirements can be achieve when a sinle lobal LO river is use. Hence, the architecture with cascoe local mixin achieves the hihest performance an is expecte to achieve the taret SFDR RB of 85Bc.

87 6.8. Conclusion 73 Table 6.2: Comparison of the two Mixin-DAC architectures SFDR RB Architecture Fiure Nominal 90% yiel Cascoe local mixin Bc 85Bc Cascae mixin in the river Bc 66Bc 6.8 Conclusion Timin errors are a main concern in hih spee hihly linear Mixin-DAC architectures. The ranom timin errors of the unary part influence the choice of the most optimal architecture. The linearity of a Mixin-DAC architecture is very sensitive to elay timin errors in the LO an Mixe sinal. Hence, the architecture with cascoe local mixin achieves the hihest performance. The simulate performance of this architecture is: 90% yiel SFDR RB =85Bc at f out =4GHz.

88

89 7 Output transformer Chapter 5 shows that the isolation between the lare output voltae swin an internal noes is important for achievin hih linearity. A traitional solution is the use of a local output cascoe. Another solution, iscusse in this chapter, is an output transformer. It is shown that usin a hih turn ratio results in a hih attenuation of the output voltae swin from the seconary to the primary sie. But it is also shown that a hih turn-ratio also results in a hih power consumption. This chapter is base on a paper publishe in the proceeins of the IEEE ECCTD 2013 conference [84]. 7.1 Introuction An RF-DAC base on the Current Steerin DAC approach can be very linear when the 1-bit switche current sources are inepenent an ientical. However, amon the main causes of harmonic istortion are the output relate error mechanisms, which are iscusse in Chapter 5. The lare sinal swin at the output (typically 1V pp ) moulates the non-linear output capacitance an couples to internal noes ue to the finite output impeance. When the output sinal swin is reuce, the linearity of the converter improves. For a simple simulation, Fiure 7.1 shows the IMD3 (i.e. linearity) versus the loa resistance at I out,pp =20mA an f out =4GHz. At the typical loa resistance of 50Ω, the IMD3 is -71Bc, which is not sufficient for a hihly emanin application such as multicarrier GSM. Since the output relate non-linearity mainly oriinates from the switchin output transistors, only those transistors are realistically moele in the simulation of Fiure 7.1. In Chapter 5, local output cascoe transistors are use to shiel the internal switchin transistors from the output, an hence improve the linearity. This chapter proposes another solution: the use of an output transformer, which is shown in Fiure 7.2. When the turn ratio of the

90 76 Chapter 7. Output transformer 70 IMD3 [Bc] R L [Ω] V out [V pp ] Fiure 7.1: Current Steerin Mixin-DAC output linearity epenence on the loa resistor (i.e. output voltae swin) V out,cm R L R L V out L 2 V out k L 1a L 1b V LO I blee M 4 V b Data LO M 5 M 6 M 2 M 3 V b Data M7 I blee LO V 2 V 1 M 1 M 0 Fiure 7.2: Current Steerin Mixin-DAC with output transformer transformer n is larer than one, the loa impeance seen from the Mixin- DACcurrentcellsisrouhlyR L /n 2. Thereforethevoltaeswinattheoutput of the Mixin-DAC current cells is lower than at the loa, which reuces the output relate non-linearities. An RF-DAC with output transformer has been

91 7.2. Cascoe vs. transformer 77 presente before [28], but it has never been propose for linearity reasons. The next section compares these two linearity enhancement methos. In Section 7.3, implementation options for the output transformer are iscusse. Section 7.4 presents calculations of the specific transformer setup. Section 7.5 presents simulation results of the transformer an Mixin-DAC with transformer. 7.2 Cascoe vs. transformer Two methos for RF-DAC linearization, iscusse in this section, are: local output cascoe an output transformer. Note that the two methos are not mutually exclusive, but can be combine. Table 7.1 ives an overview of the comparison. Table 7.1: Comparison of cascoe an transformer for RF-DAC Cascoe Transformer Area Power consumption / efficiency Common moe isolation Voltae hearoom Hih frequency output filterin - + DC output filterin o o Ae non-linear elements - + Hih frequency capability - + Noise - + Main isavantaes of the output transformer metho inclue power consumption an chip area usae. For the transformer, a turn ratio n > 1 is require to ecrease the output relate non-linear istortion. However, the Mixin-DAC output current nees to be increase by n to maintain equal sinal power at the loa, increasin the power consumption an area of the Mixin-DAC core. In aition, inuctors usually consume sinificant chip area an create power losses. Main avantaes of the transformer are as follows. The output transformer introuces common moe isolation between the Mixin-DAC an the loa, resultin in a completely inepenent common moe level at the loa. Moreover, the require voltae hearoom is lower than for the output cascoe. Especially in avance process technoloy noes, the voltae hearoom is severely limite. The output transformer also filters the low frequency offset an hiher frequency unesire output components. Low frequency filterin

92 78 Chapter 7. Output transformer can be a isavantae of the transformer when DC-couplin to a next stae is require. A core-less transformer (i.e. passive element) is hihly suitable for hih frequencies an oes not introuce sinificant aitional non-linear istortion. An output cascoe on the contrary consists of transistors (i.e. active element), which are inherently non-linear an introuce aitional parasitic capacitances, limitin the maximum sinal frequency. The wieban output noise of the Mixin-DAC is mainly enerate by the current source transistors. Since the output current is increase in the transformer metho, the SNR will also improve for equal current ensity. 7.3 Implementation options Three ifferent transformer implementation options are consiere: onchip (i.e. on-ie), on-laminate an on-pcb; see Fiure 7.3. In principle, multiple cascae transformers with ifferent implementation can also be use. For simplicity, in this chapter only a sinle transformer is consiere. Implementation: On-Chip an/or On-laminate an/or On-PCB Die Laminate RF out PCB Fiure 7.3: Three implementation options for the Mixin-DAC output transformer On-chip transformers are very popular in literature [69 71], but not yet propose for linearity enhancement of RF-DACs. For the esin an simulation of a fully customize transformer, numerous tools are available. The interface between the Mixin-DAC an the transformer is very oo, since both resie on the same substrate. However, the transformer coils can be bulky for the low taret frequencies, which can make the on-chip transformer expensive. A iscrete on-pcb transformer is the most inexpensive an flexible option, but is only available in a limite number of confiurations. The interface between the transformer an the Mixin-DAC contains one or multiple bonwires, which can erae the transformer performance.

93 7.4. Theoretical framework 79 With on-laminate transformers, lare inuctors are possible ue to the low cost of laminate area compare to stanar CMOS chip area, an custom transformer esin is possible. However, a bonwire interface is present between the Mixin-DAC an the transformer. Flip-chip assembly can minimize the inuctance an resistance of the chip-to-laminate interface. Simulations of the transformer moel incluin bonwires reveal the most suitable implementation, see Section Theoretical framework The transfer of a Mixin-DAC with a transformer as output buffer can be calculate. Two moels of a Mixin-DAC with transformer are iscusse in this section. Calculation results an simulation results provie the optimal parameter values Transformer moel For calculations an simulations, the Direct form moel of [69] is use. Fiure 7.4 shows this transformer moel with the source an loa confiuration, where k is the transformer couplin factor (k < 1), an n is the turn ratio n = L 2 /L 1. V in Simple transformer moel I 1 L2 I 2 I in ki 2 n C L ki par 1 1 /n CL RL V out Fiure 7.4: Simple transformer moel for calculations The sinal source is the Mixin-DAC, which can be moele as a current source (I in ) with finite output impeance. In practice, the output resistance is much larer than the loa resistance, hence it is not moele. The output capacitance C par is typically 1pF. The loa impeance is ieally only a resistor (R L ), but typically also contains some capacitance (C L ). In reality, transformers also contain parasitic capacitances an resistances. Bonwires are usually not taken into account in transformer analysis, but can severely limit the transformer performance. Therefore, also an extene moel of the transformer with the aforementione elements is use in the simulations, see Fiure 7.5. Calculations on transformer characteristics in open literature usually iscuss the transformer performance in the case of matche source an

94 80 Chapter 7. Output transformer Extene transformer moel V in I in Cpar L bon1 R bon1 C ps L bon2 I 1 R1 L 2 I ki 2 n ki C1 L 1 /n R 2 2 R bon2 1 C 2 C L RL V out Mixin-DAC Bonwire C ps Bonwire Loa Fiure 7.5: Extene moel of a transformer in a Mixin-DAC loa impeances an only icuss S-parameters. In the Mixin-DAC output transformer, the source impeance is not matche an the S-parameters o not ive the esire information. Instea, the voltae attenuation between input an output, H VV (ω), is of main importance. The power transfer is analyze usin the input current to output voltae transfer of the transformer H VI (ω). Both performance metrics are iscusse in the next subsections. For the first orer approximation, the simple moel of Fiure 7.4 is use Current-to-voltae transfer H VI (ω) It is assume that the output current of the Mixin-DAC current cells is scale with n, such that the output power at the loa is constant. The output impeance of the Mixin-DAC current cells also chanes accorinly: I in = I in,0 n, C par = C par,0 n. The calculate transfer characteristic is: where: H VI (ω) = V out(ω) I in (ω) = H 0 1+j ω 1 1 ( ω ω res ) 2 1 ω H j ω + ω L j ω + 1 ω A j ω ω B, (7.1) H 0 =R L k 1 n, ω 1 res = (1 k 2 ) L, (7.2) 2 n C par,0 ω L = R L, ω A = R Lk 2 L 2 L 2 (1 k 2 ), (7.3) ω H = 1 n, ω B = R L C L k 2. (7.4) R L C par,0 An approximation of the boe plot of the H VI (ω) amplitue is shown in Fiure7.6. ThepassbanamplitueH 0 iseterminebyr L, convertebythe

95 7.5. Simulation results 81 transformer with ratio k/n. The lower frequency corner ω L is mainly ue to the R L /L 2 time constant. A resonance peak an secon orer low-pass filter corner is present at ω res. This resonance is cause by an LC tank, forme by the leakae inuctance (1 k 2 )L 2 an the Mixin-DAC output capacitance seen at the transformer output C par,0 /n. The other hih frequency pole ω H is mainly ue to the R L C L time constant. The other two roots at ω A an ω B only slihtly influence the H VI transfer characteristic aroun the resonance frequency. H VI (ω) H 0 ω L ω res ω H ω Fiure 7.6: Amplitue of the H VI (ω) of the simplifie transformer moel Voltae ain H VV (ω) The voltae ain H VV (ω) of the transformer is a measure for the linearity improvement which can be attaine when ain the transformer to the output of the Mixin-DAC: H VV (ω) = V out(ω) V in (ω) =k n 1 1+(1 k 2 )jω L 2 R L (1 k 2 )ω 2 C L L 2 (7.5) As expecte, the low frequency value of H VV (ω) is etermine by k n. The banwith is etermine by the leakae inuctance ue to imperfect transformer couplin L 2 (1 k 2 ) toether with R L an C L. 7.5 Simulation results In this section, simulation results of the separate transformer an simulations of the Mixin-DAC with output transformer are presente.

96 82 Chapter 7. Output transformer Transformer The confiuration of the simulation setup is: R L = 50Ω, C L = 500fF an C par,0 = 1pF. Simulations have shown that an optimal transformer confiuration for the exemplary application ( GHz) is: L 2 = 8nH, k = 0.85 an n = 4 (hence, C par = 4pF an L 1 = 0.5nH), where k an n are limite by what is practically achievable. The resultin simulate transfer characteristic H VI (ω) an voltae ain H VV (ω) are shown in Fiure 7.7. H [BΩ] VI H [B] VV Frequency [GHz] 10 Fiure 7.7: Simulation results of simple transformer moel The shapes of the simulate H VI (ω) an H VV (ω) closely match the calculate shapes. The passban amplitue of H VI (ω) is 22BΩ, resultin in approximately 1V pp sinal at R L for I in =n 20mA=80mA. The passban flatness is 6B. At low frequencies H VV (ω) is 10.7B, lowerin to 9.4B at 4.0GHz. The H VI (ω) in-ban flatness of 6B can be improve by improvin k or C par, which are both practically limite. However, simple iital preprocessin can easily counteract the non-flatness of the power transfer. The 4GHz H VV (ω) value can only be increase by ecreasin the L 2 inuctance, increasin the turn ratio n, or improvin the couplin factor k, which are all impractical or unesirable Extene transformer moel One of the important extensions to the simple transformer moel is bonwire inuctance an resistance. The bonwire inuctances act in the same way as imperfect transformer couplin k, lowerin the resonance frequency in H VI (ω) an lowerin the banwith of H VV (ω). The transformer input inuctance value L 1 is very low (L 1 = L 2 /n 2 ), hence the transformer input is sensitive to aitional bonwire inuctance.

97 7.5. Simulation results 83 Fiure 7.8 shows the H VI (ω) flatness an the values of H VV (ω) at the extremes of the ban of interest, as a function of L bon1. For hiher L bon1 values, the H VV (ω) banwith an amplitue eraes, an the resonance peak in H VI (ω) shifts in the ban of interest, causin a poor H VI (ω) flatness. Therefore, L bon1 shoul be less than 0.15nH, which is not practical. Hence, transformers for hih frequency an with hih turn ratios (i.e. small inuctance at the transformer input) can only be implemente on-chip, resultin in L bon H [BΩ] VI H VV (0.7GHz) H VV (4GHz) H VI flatness L bon1 [nh] H [B] VV Fiure 7.8: Transformer performance eraation ue to L bon1 A bonwire at the transformer output with achievable values for the inuctance an resistance (L bon2 =0.5nH, R bon2 =1Ω) oes not erae the transformer performance sinificantly. The require parasitic coil resistance an capacitance for performance preservation are not critical. The followin values are assume: C 1 =100f, C 2 =200fF, C ps =200fF, R 1 =1Ω, R 2 =4Ω Transformer an Mixin-DAC The Mixin-DAC moel, mentione in Section 7.1, toether with the simple an extene transformer moel of Section an Section is use to verify the linearity improvement when usin the output transformer on a Mixin-DAC. The IMD3 epenence on n of the Mixin-DAC for the most critical output frequency (4GHz) is shown in Fiure 7.9. The sinal voltae swin at the loa is approximately 1V pp for all simulations. For an almost ieal transformer Simple, k=0.95, the IMD3 at n=4 is -89Bc, 18B better than the conventional Mixin-DAC. However,

98 84 Chapter 7. Output transformer IMD3 [Bc] Simple, k=0.95 Simple, k=0.85 Extene k=0.95 Extene, k= Turn ratio n Fiure 7.9: Simulate IMD3 for Mixin-DAC with output transformer the linearity eraes when the non-iealities of the transformer are ae, specifically at lower values of k. Also k itself stronly influences the linearity. For the simulation setup with insufficent linearity improvement, it can be observe that sinal power at the transformer input at multiples of the LO frequency is not attenuate by the transformer because of the limite transformer banwith. This unattenuate hih frequency sinal power causes non-linear istortion in the Mixin-DAC. A hiher k increases the banwith of the transformer an hence improves the linearity. Usin the extene transformer moel at n=4 an assumin k=0.9 is achievable, the resultin IMD3 is -85Bc, 14B better than the conventional Mixin-DAC. 7.6 Conclusion Output relate non-linearity is a major concern for hihly linear current steerin RF-DACs. This chapter proposes a novel approach for RF-DAC linearization base on a wie-ban impeance transformation. Simulations of the presente transformer moel clearly inicate that for the implementation of an output transformer for hih-frequency wie-ban RF-DACs, on-chip transformer implementation is the only viable approach. Hiher turn ratios result in a larer voltae ain, an hence a hiher linearity improvement. However, hiher turn ratios also increase the power consumption of the DAC output stae, thus ecreasin the efficiency of the Mixin-DAC. Simulations of a specific RF-DAC moel with an output

99 7.6. Conclusion 85 transformer show that the IMD3 improves by about 14B. The propose novel output-transformer base RF-DAC architecture is expecte to enable the esin of hihly linear wie-ban transmitters.

100

101 8 Calibration One of the sources of non-linearity in Current Steerin (CS) DACs an Mixin-DACs is mismatch of the current sources in the switche current cells. Some traitional calibration methos compensate this mismatch by means of a calibratin DAC in each current cell. However, this metho tries to calibrate a mismatch value with a nominal value. These two values respon ifferently to chanes in the environment, e.. temperature chanes. Hence, the calibration is only vali for the same environment as the calibration environment. A novel calibration metho is iscusse in this chapter, that compensates the mismatch of the main current source with the mismatch of another current source. This ensures equal response to environment variations. Simulations emonstrate the effectiveness of the calibration metho. This chapter is base on a paper publishe in the proceeins of the IEEE ISCAS 2011 conference [87] an in the proceeins of the annual STW ProRISC 2011 conference [86]. 8.1 Introuction The static DAC linearity, e.. INL (Interal Non Linearity), is mainly limite by the finite matchin of the DAC current source transistors. The mismatch between ientically size an biase transistors is iven in (8.1) [72]. ( σī ) ( 2 = A 2 β I + 4A 2 ) VT (V GS V T ) 2 1 2WL (8.1) Usin lare evices (W L) reuces the ranom mismatch, but increases occupie area an hence increases the systematic mismatch an eraes hih-frequency performance. The ynamic linearity, e.. SFDR (Spurious Free Dynamic Rane), is usually limite by the achieve static linearity, an further reuce at hih spees by the parasitic capacitances an resistances

102 88 Chapter 8. Calibration of the current source transistors. Therefore, to achieve hih linearity at hih spee, both small an accurate current source transistors are necessary. To improve the DAC static linearity an to reuce the size of the DAC current source transistors, calibration of the mismatch errors of the DAC current sources can be use. An example of calibration in a Current Steerin DAC (CSDAC) is shown in Fiure 8.1 [46]. For an analysis of ifferent correction methos, see [73]. OPERATIONAL CIRCUIT CALIBRATION CIRCUIT Cal_off M3,off M 3,on Cal_on V b2 M 2 V b1 M 1 I cue I cor Calibratin DAC (CALDAC) I main CALIBRATED CURRENT SOURCE CALIBRATED UNIT ELEMENT (CUE) Fiure 8.1: Implementation of CalDAC calibration principle in a current cell[46] Two types of calibration strateies can be istinuishe: foreroun an backroun calibration. Backroun calibration is continuously runnin while the DAC is actively use [74]. It suffers from increase power consumption urin operation an the output sinal may be pollute by spurious components of the calibration activities. Foreroun calibration is only active when the DAC is ile, e.. at startup, an hence avois the aforementione isavantaes. However, iscrepancies in the environment between calibration an use, e.. temperature or supply voltae, can reuce the avantaes of the calibration. In aition, the avantaes of the existin calibration methos also reuce at hih spees [74]. The propose foreroun calibration metho uses ientical unit transistors in both the current source an the CalDAC to uarantee matche responses to isturbances an temperature variations. The current cell is calibrate by combinin unit transistors with opposite mismatch within one current cell

103 8.2. Temperature an isturbance epenence 89 such that their combine mismatch is minimize. The next section explains the temperature an isturbance sensitivity of the conventional calibration. In Section 8.3, a new CalDAC implementation an calibration alorithm is propose which is insensitive to temperature variations an isturbances. Section 8.4 shows simulation results Temperature an isturbance epenence An exemplary schematic of a CSDAC usin CalDAC calibration is shown in Fiure 8.1, which is use in [75] an [76]. In the current cell, name Calibrate Unit Element (CUE), transistor M 1 is the main current source with output current I main. Due to process spreain an systematic mismatches, the value of I main eviates from the nominal esine value Īmain, i.e. for the n-th current source I main,n = Īmain + I error,n. The CalDAC enerates a correction current such that the output of the CUE I cue,n equals the value of Ī cue. In the example of Fiure 8.1, the state of transistors M 3,off an M 3,on ecies if the CUE output current is either use for the normal operation of the DAC or connecte to the Calibration circuit an measure for calibration. An exemplary implementation of a conventional CalDAC is shown in Fiure 8.2 [76,77]. The main current source M 1 consists of M transistors. The CalDAC, consistin of transistors M cal,1 to M cal,n, as the require correction current. I cue Icor V b1 I main Main current source mae of M units M 1 M cal,1 M... cal,2 M(W 1 /L 1 ) W 2 /L 2 2W 2 /L 2 1b mem 1b mem 1b mem 1 st bit 2 n bit N th bit N-bit CALDAC M cal,n V bcal 2 N-1 W 2 /L 2 CALIBRATED CURRENT SOURCE, V b1 > V bcal Fiure 8.2: Conventional implementation of the CalDAC 1 The presente calibration metho is not use in the Mixin-DAC esin of Chapter 11. Instea, the calibration metho which is available in the baseline DAC from the inustry partner (see Section 11.1) is use, which can calibrate both the static an ynamic errors of a DAC [3].

104 90 Chapter 8. Calibration To achieve hih post-calibration static linearity, the LSB of the CalDAC shoul be much smaller than the LSB of the DAC [7]. Therefore, the transistors of the CalDAC have a smaller overrive voltae (V GS V T ) an usually also ifferent with (W) an lenth (L) with respect to the main current source transistors. With the exemplary DAC of [76], measurements I show that a relative correction step of LSB,cor I LSB,main < 0.2 results in a 12 bits I linearity an a relative correction step of LSB,cor I LSB,main < 0.1 results in a 13 bits linearity [73] Temperature response In CMOS processes, the mismatch between the output current of ientically biase transistors is iven by (8.1). For hih performance DACs, the main current source transistor is usually much larer than the feature size of moern CMOS processes. Thus, the current mismatch is ominate by the threshol voltae mismatch. This assumption is confirme by measurements of an existin DAC implementation [7]. Fiure 8.3 shows the stanar eviation of the output current of the 15 unary current cells. The mismatch clearly exhibits a square root epenence on the rain current, which is in conformance with (8.1) in combination with the rain current relationship of a MOS transistor in saturation, as shown by (8.2). I D = µc oxw 2L (V GS V T ) 2 (8.2) At hih temperatures, the mobility of the carriers (µ) ecreases. Usually, a temperature inepenent current controls the output current of the DAC currentsourcetransistors. Therefore,athihtemperatures,V GS V T increases to compensate for the ecreasin µ. Toether with the matchin equation of (8.1), it is clear that when the temperature increases, i.e. V GS V T increases, the relative threshol mismatch ecreases. Mismatch measurements of the existin DAC at hih temperature confirm this analysis, see Fiure 8.3. In the iscusse conventional CUE, the mismatch of a main current source is compensate by the nominal value of the CalDAC output current, i.e. I cue,n = Īmain + I error,n + I cor,n. Ī main an I cor,n are set by temperature inepenent references, while I error,n is temperature epenent. Therefore, the temperature coefficient of I cue,n epens on the ratio between I cue,n an I error,n. Fiure 8.4 shows the builup of the output current of two exemplary CUEs. The CUEs are calibrate at T = 25 C, but for T 25 C, the CalDAC calibration is not vali. To quantify the temperature epenence, a simple transistor level simulation base on [76] is performe. Two calibrate CUEs with threshol

105 8.2. Temperature an isturbance epenence 91 σ / I D (%) INL=8.1LSB INL=4.6LSB INL=6.8LSB INL=4.0LSB I D (ma) Mismatch at 25 C Mismatch at 90 C Fitte square root INL=3.7LSB INL=3.0LSB Fiure 8.3: For an existin DAC current cell array, increasin the bias current an hence the output current improves the output current stanar eviation. More importantly, the output current matchin improves for hiher temperature. Current I u Icor,1 Imain,1 Icor,2 Imain,2 errorlow T Hih Icor,1 Imain,1 Icor,2 Imain,2 25 C Icor,1 Imain,1 Icor,2 Imain,2 T Low errorhih Temp. I 1 I 2 Thermal cae I main,1 I main,2 Icor,1 I cor,2 Fiure 8.4: Output current temperature epenence of two CUEs voltae mismatch between each other are simulate over a temperature rane of 50 C to 125 C. The temperature epenence of the CUEs output current ifference, i.e. error Low error Hih, can be as lare as 8 CalDAC LSBs, which is 1.3% of the CUE output current. Thus, for foreroun calibration, the INL eraes an also the SFDR worsens when temperature chanes. This phenomenon is confirme by INL an SFDR measurements of an existin DAC [7] Disturbance response Next to the temperature epenence of the calibration, the CUEs exhibit a calibration epenent isturbance response. It can easily be arue that two

106 I(B) 92 Chapter 8. Calibration CUEs with ifferent ratios between main current an CalDAC current have ifferent responses to a isturbance on the ate noe of the CalDAC current sources. This also hols for isturbances on other noes of the CUEs. For an exemplary DAC, implemente in a CMOS 65nm process, with two current cells with ifferent correction currents an a isturbance at V bcal of Fiure 8.2, the ifference in the output current response of the two current cells is shown by the top waveform of Fiure 8.5. The cell epenent response ifference of more than 50% will certainly introuce input coe epenent behavior, which results in spurious components, sinificantly reucin the SFDR. Conventional CalDAC Propose CalDAC Freq(Hz) Fiure 8.5: Difference in response of two current cells with ifferent calibrate mismatch for both the conventional CalDAC an the new propose CalDAC 8.3 Propose new calibration metho To match the response of the correction harware to temperature an on-chip isturbances, an hence exten the avantaes of the foreroun calibration, a new calibration metho is propose [86, 87]. A chip implementation of this metho is later publishe in [78]. In the propose CUE, the same number of unit transistors (M) is use in every CUE. These M transistors are ivie in two roups, M K unit transistors in the fixe roup an K unit transistors in the confiurable roup. The K unit transistors in the confiurable roup can be interchane with X aitional reunant unit transistors, such that the mismatch of the confiurable roup transistors compensates the mismatch of the fixe roup. The two roups toether enerate the esire output current. A novel principle is the use of ientical unit transistors for both the fixe roup an the confiurable roup, sharin a common bias voltae, proviin

107 8.3. Propose new calibration metho 93 a matche response for every CUE in the DAC. Another novel concept is to compensate the mismatch of the fixe roup of transistors in the current cell with the mismatch of the confiurable roup transistors, eneratin a temperature stable calibration Harware A schematic overview of the new CalDAC implementation is shown in Fiure 8.6. The M K main current source transistors provie the fixe current I main. K units in the roup of P unit transistors in the CalDAC are switche on to enerate the correction current I cor. The value of X efines the ae amount of reunant current sources with respect to the M-transistor intrinsic current cell. The value of P is an inication of the ae layout complexity, since every transistor in the CalDAC is controlle separately. I cue Icor I main V b1 M M cal,1 M... cal,2 M cal,p 1 W1 (M-K)(W1 /L /L 1 1 ) W 1 /L 1 W 1 /L 1 1b mem 1b mem 1b mem Main current source 1 st unit 2 n unit P th cell mae of M-K units CALDAC mae of P=K+X units CALIBRATED CURRENT SOURCE Fiure 8.6: Propose Calac with common transistor imensions an biasin Alorithm The alorithm to fin the optimal correction for a current source is explaine usin a semente DAC architecture, of which the Least Sinificant Bits (LSBs) are implemente usin binary current cells an the Most Sinificant Bits(MSBs) are implemente with unary coe current cells. Note that the escribe metho can also be applie to a fully unary or binary coe DAC. Two ifferent calibration methos are use for the unary current cells an the binary current cells, which are escribe separately.

108 94 Chapter 8. Calibration Unary current cells The principle of the calibratin alorithm of one CUE is to select which transistors of the CalDAC shoul be switche on such that I cue is properly correcte. The first step in the alorithm is to sort the transistors in the CalDAC accorin to their output amplitue an then switch on K of the hihest amplitue transistors. Fiure 8.7 ives an example, where M = 8, K = 3 an X = 3. The top fiure shows the output amplitue of the unit transistors (which are name a-k), an ives the first step. Fixe part Variable part 2 3 Current source amplitue a b c e M-K units f K units h 1 i j X units k First step On a b c e a b c e a b c e a b c e Off f h f i f f h h i j I ref Secon step Fiure 8.7: Example of the calibration alorithm The secon step in the alorithm is to swap transistors between the onroup an the off-roup until the total output current becomes less than the reference. The top iaram of Fiure 8.7 inicates the first three swap actions (name 1-3). The bottom iaram ives the resultin total output current of the CUE for the initial state (name 0) an after each swap action. The alorithm will stop after swap step 3, because the total output current is less than the reference I ref. For the calibration of the unary current cells, the reference consists of the sum of all binary current cells an one LSB current source as in [77]. Therefore, the binary current cells shoul be calibrate before the unary current cell calibration. The main harware component necessary to implement the alorithm for the unary current cells is a comparator to sort the transistors an compare the reference an the CUE total output current. The alorithm can be realize as a simple Finite State Machine (FSM).

109 8.4. Simulation results Binary current cells The alorithm to calibrate the binary current cells is larely ientical to the alorithm for the unary current cells. For the calibration of N lsb binary current cells in one DAC, N lsb reference currents are require, with a ratio of 2 between two successive references. Since exact current ratios are ifficult to implement in the analo omain, the complete binary calibration alorithm is implemente in the iital omain. Therefore, all unit transistor currents are measure usin an Analo to Diital Converter (ADC), an all transistor sortin, swappin an output current calculation can be one iitally. To be insensitive to ain an offset errors of the ADC, the main current source of the binary current cells is omitte (M K = 0). Instea, the current cell output current is constructe usin the separately measure unit transistors of the CalDAC. The alorithm is insensitive to the ADC offset an ain error since all unit transistors share the same ADC errors with equal relative importance. For the binary calibration, the simple comparator check in the unary current cell calibration is replace by a check if the ifference between the reference an the total output current is minimal. The reference for the binary calibration is enerate by separately measurin all CalDAC transistors of the complete DAC with the ADC, computin the averae an multiplyin by the corresponin power of two. The necessary harware to implement the binary current cell calibration is the ADC an a FSM. The ADC oes not nee to be fast or accurate an is implemente as a Successive Approximation (SAR) ADC [76, 77] with 5 bits linearity. The aitional area for the ADC an the FSM is neliible compare to the area of the current source array. 8.4 Simulation results The effectiveness of the propose calibration metho is valiate with simulations of the INL improvement, temperature response an isturbance response Alorithm The presente new calibration alorithm is valiate usin a Matlab moel of a 6+6 (unary + binary) bits semente DAC. All current cells are base on the same unit transistor. The LSB current cell consists of 1 transistor, the next current cell of 2 transistors, etc. Thus, the unary current cell has a weiht of 2 Nlsb LSB, an hence consists of M = 64 transistors.

110 96 Chapter 8. Calibration There is a trae-off between the aitional harware an harware complexity in the choice for K an X. The achieve improvement between the intrinsic INL an the calibrate INL epens on K an X. Monte Carlo simulations of 1200 DACs per one simulation point are execute to investiate the effects of usin ifferent values for K an X on the 99% yiel INL. First, these simulation show that with a fixe number of CalDAC transistors (P), the hihest improvement of INL is achieve when K = X, since then the number of possible combinations is maximize. For ifferent values of K, X an unit transistor matchin, the 99% yiel INL values, with respect to 12 bits accuracy, are shown in Fiure 8.8. It is clear that usin more transistors in the CalDAC results in more possibilities for the alorithm an hence hiher improvement when applyin the calibration metho. It is also observe that the improvement between the intrinsic INL an the calibrate INL is constant when the values of K an X are fixe % yiel INL [LSB] bits improvement Intrinsic K=5, X=5 K=10, X=10 K=20, X=20 K=32, X= % Mismatch 10% Fiure 8.8: Matlab simulations showin the matchin- an confiuration-epenent 99% yiel INL of the new calibration metho When for the exemplary 6+6bits DAC, 12 bit linearity is require an 99% yiel for the INL specification, the combination of 3% unit transistor matchin an a CalDAC with K = X = 20 results in an improvement of static linearity from 9.4 bits to 12.2 bits, while only increasin the current source area with approximately 30% Temperature response To investiate the temperature coefficient of the propose calibration metho, the same transistor level simulation of Section 8.2 has been performe. After calibration, the temperature epenence of the ifference between the two currents is less than 0.001% of the total output current

111 8.5. Conclusion 97 over the complete temperature rane, which is 1000 times lower than the conventional CalDAC calibration. Thus, the propose calibration principle results in a temperature stable calibration Disturbance response The same number of transistors is switche on in every CUE. Therefore, every CUE has approximately the same response to isturbances, inepenent of the correction current. This inicates that the calibration avantaes are also present at hih spees. For a isturbance at the ate noe of the current source transistors (V b1 in Fiure 8.6), the ifference in output response of the twoexemplarycuesisshownasthebottomwaveforminfiure8.5. Overthe complete frequency ban, the ifference in response between the two CUEs is less than -70B. Since the response ifference is manitues lower than the conventional CalDAC, it is expecte that the spurious components ue to on-chip isturbances are sinificantly reuce. 8.5 Conclusion The propose novel calibration metho overcomes the problems with the cell-epenent temperature coefficients of the Calibrate Unit Elements. Also the cell-epenent response to isturbances is reuce. Due to the reuction of these two cell-epenent responses, the spectral purity of the DAC output sinal is expecte to improve. The new calibration alorithm provies opportunities to improve the post calibration INL of a DAC. For an exemplary 6+6bits semente current steerin DAC, the expecte 99% yiel INL improves with almost 3 bits when usin only 30% aitional current cell area. The propose new calibration metho will obliviate the nee for backroun calibration, while also proviin calibration avantaes to hih DAC spees.

112

113 9 Sementation The sementation trae-off of many current-steerin DACs is base on the sementation approach of [66]. This trae-off is base on the INL/DNL characteristics of the converter. However, for hih spee DACs an Mixin- DACs, also the ynamic characteristics of the converter influence the sementation trae-off. This chapter iscusses these ynamic characteristics an proposes a new approach to the sementation trae-off. This chapter is base on part of a paper publishe at the IEEE ISCAS 2014 conference[83]. 9.1 Introuction Current Steerin (CS) Mixin-DACs preominantly use a semente implementation, with a unary scale MSB part an a binary scale LSB part. A CS Mixin-DAC with local mixin[85] can be very linear if the responses of all 1-bit switche current sources(current cells) are uncorrelate an ientical, or ieally scale for binary current cells. For multicarrier transmitters, the power of a sinle carrier is much lower than the total full scale output power. This sinificantly increases the importance of the responses of the binary (LSB) current cells an alters the sementation trae-off. As iscusse before, amplitue errors are extensively iscusse in open literature. In this chapter, the timin error of the binary part an its impact on the performance are iscusse. In the binary part, systematic timin errors are ominant over ranom timin errors. The systematic binary timin errors are iscusse in this chapter. Section 9.2 introuces the concept of output power back-off an its impact on the spectral purity. In Section 9.3, the importance of matchin of the binary LSB part of a Mixin-DAC is iscusse. The consequences of these two subjects for the sementation trae-off are iscusse in Section 9.4.

114 100 Chapter 9. Sementation 9.2 Output power back-off One of the characteristics of a multicarrier transmitter is that the power of each sinle carrier is lower than the full scale sinal, which is calle backoff (typically aroun -16B FS /tone). In such a transmitter, the sinal of one tone only uses a small subset of the unary current cells, effectively chanin the sementation of the Mixin-DAC. Hence, the binary part of a semente Mixin-DAC becomes increasinly important. Fiure 9.1 shows the spectra of a full-scale ual-tone sinal at -6B FS /tone, an a sinal at -16B FS /tone (10B back-off). While the ifference in sinal power is 10B, the spur-floor is at the same absolute level, reucin the SFDR. The cause of this hih spur-floor is systematic timin errors between the binary current cells B FS /tone 16B FS /tone F LO f out =F LO +f in =10B Differential spectrum [Bm] Output frequency [MHz] Fiure 9.1: Spectral compariston between full-scale output an back-off 9.3 Binary matchin In a traitional DAC output stae, only one critical hih-spee noe shoul be riorously optimize for binary scalability: the source of the output cascoes. In the chosen Mixin-DAC architecture of Fiure 9.2, two sets of hih-spee noes nee precise optimization: the source of the output cascoes (noes A an A ) an the source of the mixer (noes B an B ). The response of these noes shoul be exactly scale with respect to the unary current cell. To uarantee this binary matchin, the capacitance values an the ain of the transistors at these noes shoul scale exactly with the binary current cell scalin.

115 9.3. Binary matchin 101 V R L R L V out V out LO in LO LO M V 8 c V V b1 b1 Vc A A σ M 9 V b1 LO V b1 M 4 M 7 M I B 5 M 6 B blee I blee LO Data M 2 Data M 3 V 2 V 1 M 1 M 0 Fiure 9.2: Chosen Mixin-DAC architecture with annotate timin errors: output stae mixin with a sinle lobal LO river To illustrate the sensitivity of the performance to capacitance eviations in the binary current cells, Fiure 9.3 shows the SFDR RB as a function of the parasitic capacitance at the source of the output cascoes (A an A ) of the three most sinificant binary cells (B9, B8 an B7) in the LSB part of the exemplary Mixin-DAC. The pre-annotate capacitance in the schematic moel of the current cells is altere. The x-axis is in % eviation of the ieally scale value to ease the comparison between the various binary cells. The ieal value at 0% is the exactly binary scale capacitance: the 6fF in the unary cell results in 3fF for B9, 1.5fF for B8, etc. Fiure 9.3 clearly emonstrates the low robustness of the spectral purity to the capacitance value. A chane of 4% in the capacitance value in B9 results is a SFDR RB eraation of 9B to 83Bc, which is worse than the require 85Bc. Fiure 9.3 also shows a relationship between the capacitance robustness an the binary cell inex. The B9 cell has the lowest robustness: ±3% for 85Bc. The subsequent binary cells have a ouble robustness for each inex ecrement: B8=±6%, B7=±12%. Even thouh the actual robustness numbers may only be vali for the exemplary Mixin-DAC implementation, the robustness tren is vali for all CS (Mixin-)DACs. The robustness of an implementation is limite, which also limits the maximum SFDR RBw hen the sementation is fixe.

116 102 Chapter 9. Sementation SFDR RBW [Bc] % 12% 24% B9 B8 B Wire capacitance eviation from ieal [%] Fiure 9.3: SFDR epenence on the parasitic capacitance at the output cascoe source noe of B9, B8 an B7 9.4 Sementation A novel, back-off aware sementation trae-off is propose in Fiure 9.4(a), in analoy to the sementation trae-off fiures in [66]. A larer unary MSB part improves the SFDR RB, but a lower output power reuces the SFDR RB. The sementation trae-off of the exemplary Mixin-DAC is shown in Fiure 9.4(b). The propose sementation (6b unary, 10b binary) is esin point α, where SFDR RB =86Bc at -16B FS /tone. If the back-off requirement increases to -22B FS /tone, the SFDR RB =80Bc (esin point β). If the SFDR RB of 86Bc value shoul be maintaine at -22B FS /tone back-off, the sementation shoul be chane to one more unary bit, which is esin point γ. This illustrates the trae-off between SFDR RB, sementation an output power back-off. Naturally, chanin the sementation has numerous other implications, e.. on layout area or maximum sinal frequency. The simulate performance of the exemplary Mixin-DAC sementation at -16B FS /tone(10bback-off)ofsfdr RB =86Bcissufficientfortherequire 85Bc, hence the chosen sementation is optimal. 9.5 Conclusion Timin errors are an important consieration in hih spee hihly linear Mixin-DAC architectures. For multicarrier transmitters, output power backoff is often use. With back-off, the matchin of parasitic capacitances at the hih-spee noes in the binary current cells is crucial for achievin a hih SFDR RB. The propose sementation trae-off shows that for every 6B of aitionally require back-off, one extra unary bit is neee.

117 9.5. Conclusion 103 SFDR RBW 0BFS/tone back-off -6BFS/tone back-off -12BFS/tone back-off SFDR RBW 86Bc 80Bc 6B α β -16BFS/tone back-off -22BFS/tone back-off γ 1 bit B/0U 10B/6U 9B/7U 0B/16U Binary Sementation [%] Unary Binary Sementation [Binary/Unary] Unary (a) (b) Fiure 9.4: Sementation trae-off base on SFDR RB an backoff, showin both the tren (a) an quantitative results for an exemplary Mixin-DAC (b) The propose metho leas to an optimal sementation for the chosen Mixin-DAC architecture tailore towar the hih spectral purity an hih frequency requirements of multicarrier GSM transmitters. The simulate performance of this architecture is SFDR RB =86Bc at f out =4GHz an -16B FS /tone output power (10B back-off).

118

119 10 Optimal architecture Chapter 4 iscusses three promisin architectures. Chapter 5-9 aresses the ifferences between those architectures. This chapter summarizes the conclusions of that analysis an proposes the most optimal architecture. Base on the linearity of the three architectures, both in the nominal case an with mismatch, it is conclue that cascoe local mixin is the most optimal architecture. The implementation of this architecture as a test chip is iscusse in Chapter Classification The classification (see Chapter 3) ientifies the most optimal characteristics for a hih spectral purity GHz frequencies Mixin-DAC: currentsteerin principle, Cartesian sinalin, square-wave mixin, symmetric aroun zero sinalin for the LO an ata sinal, fully ifferential an LO-ate transistor usae. The classification ientifies two architectural choices which nee quantitative analysis: Mixin locality an sequence of operations. Combinin these architectural choices results in three promisin Mixin-DAC architectures: cascoe lobal mixin, cascoe local mixin an iital mixin Quantitative architecture analysis Chapter 5 shows that cascoe local mixin achieves a hiher linearity than lobal mixin with the use of a local output cascoe. Chapter 6 shows that cascoe local mixin exhibits much lower timin-error sensitivity than iital mixin. These conclusions are summarize in Table 10.1 by comparin the SFDR RB values of all three promisin architectures. For these simulations, the frequency values are: f LO =3.92GHz, F S =1.96GHz, f in =150MHz & 165MHz. For the mismatch simulations, only the relevant

120 106 Chapter 10. Optimal architecture components have mismatch. Mismatch that is correcte with calibration is not taken into account. Table 10.1: Comparison of a selection of Mixin-DAC architectures SFDR RB Sequence Locality Fiure Nominal 90% yiel Global Bc 75Bc Cascoe Bc 85Bc Local Mixin DAC Bc 66Bc It can seen that cascoe operations toether with local mixin achieves the best spectral purity, both in the nominal case an the mismatch case. Chapter 7 shows that usin an output transformer instea of a local output cascoe is feasible. However, the resultin power consumption is much hiher than when usin an output cascoe. Since the output cascoe also achieves the esire linearity, no output transformer is use. Base on the classification of Mixin-DAC architectures an the aforementione quantitative analysis, a stron caniate Mixin-DAC architecture for hih spectral purity can be synthesize. The basic characteristics of the architecture are as follows: Cartesian sinalin, 1-bit SaZ LO mixer input (square-wave LO sinal), 1-bit SaZ BB mixer input (local mixin), fully ifferential sinalin, cascoe mixin an D/A conversion, LO mixin sinal at transistor ate. The choice for SaZ LO mixer input over RZ LO mixer input is influence by the features of the baseline DAC of the inustry partners, see Section This DAC core contains a metho to reuce the effect of BB timin errors, which eliminates the avantae of usin RZ LO sinal, see Section Since this calibration metho also calibrates the amplitue mismatch of the current source, the calibration metho of Chapter 8 is not use Sementation The sementation of the baseline DAC of the inustry partner is use for the implementation of the propose Mixin-DAC architecture. The resolution is 16 bit, semente in 6 MSB unary bits an 10 LSB binary bits. This sementation results on the one han in a nominal SFDR which is just over the require 85Bc. On the other han, the capacitance of the output tree is such that the output power at the taret maximum frequency of 4GHz

121 10.4. Expecte performance of final architecture 107 is reuce with approximately 5B, which is sinificant. However, chanin the sementation to less MSB bits will result in a worse SFDR which is not esire Expecte performance of final architecture A mixin-dac architecture incorporatin all above mentione characteristics is shown in Fiure 3.5. A typical output spectrum of the implementation of this architecture is shown in Fiure 10.1 an Fiure For this simulation, the frequency values are: f LO =3.92GHz, F S =1.96GHz, f in =150 & 165MHz. In this ranom mismatche simulation, the IMD3 is -86Bc an the SFDR RB in a reuce banwith of 300MHz is -85Bc. 20 Output power [Bc] f LO -f in f out =f LO +f in flo +FS 2 f LO 2 f LO +F S Freq. [GHz] Fiure 10.1: Exemplary Mixin-DAC output spectrum 10.5 Conclusion The classification leas to a number of promisin Mixin-DAC architectures for hih spectral purity at GHz frequencies. Quantitative analysis of these promisin architectures leas to the synthesis of the most optimal architecture. The characteristics of this architecture are: Cartesian sinalin, 1-bit SaZ LO mixer input (square-wave LO sinal), 1-bit SaZ BB mixer input (local mixin), fully ifferential sinalin, cascoe mixin an D/A conversion, LO mixin sinal at transistor ate.

122 108 Chapter 10. Optimal architecture 20 f out =f LO +f in1 f out =f LO +f in2 0 Output power [Bc] Freq. [GHz] Fiure 10.2: Exemplary Mixin-DAC output spectrum

123 11 Desin of a hihly linear wie-ban Mixin-DAC In the previous chapter the most optimal Mixin-DAC architecture for hih spectral purity is propose. To valiate this architecture, it is implemente in 65nm CMOS. Various aspects of the esin are iscusse in this chapter, toether with main performance limitations. The iscusse circuits are: output stae, LO river, ata path an elevate bulk eneration. This chapter also presents the simulation results of this architecture. Measurement results of this esin are presente in Chapter 12. This chapter contains parts of a paper submitte to the IEEE ISSCC conference [81] Introuction To valiate the propose architecture, a 16 bit 2GSps 4GHz Mixin-DAC is esine. The use process technoloy is a triple-well 65nm CMOS with 1.2V an 3.3V supplies. IP blocks of a baseline DAC are provie by the inustry partner. These IP blocks inclue: the iital sinal processin, the ata path incluin the ata rivers, the chip outline incluin IO rin an ESD evices, the biasin, the current source array, an the calibration circuitry. Lare amount of alterations neee to be mae to a the circuitry for chanin the function to a Mixin-DAC. One of the most important features which are use, is the sort-ancombine calibration alorithm to calibrate the timin errors of the ata path an the amplitue errors of the current source array, see Section 11.2 an Section The maximum sample rate of the baseline DAC is more than 2GSps, hence this is also the taret of the Mixin-DAC. For eneratin an

124 110 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC output sinal up to 4GHz, a maximum LO frequency of 4GHz is chosen. Since the case of F S =2GSps an f LO =4GHz is the most challenin case, this confiuration is use in most of the simulations. The frequency of the baseban input sinal is aroun 150 MHz since in that case any LO leakae falls outsie the RB with a banwith of 300MHz. The typical full-scale output current is 20mA, terminate in 50Ω ifferential loa. In Section 11.2, the various elements of the architecture are introuce. The main elements are: output stae, LO river, elevate bulk eneration an ata path. These elements are iscusse in Section 11.3 to Section 11.6 respectively. Section 11.7 presents the hih level simulation results of the Mixin-DAC Architecture An overview of the architecture is shown in Fiure The chip consists of two inepenent Mixin-DACs which can also be use in an I/Q confiuration. These two Mixin-DACs are esinate Mixin-DAC A an Mixin-DAC B. The schematics of the two Mixin-DACs are ientical an there are no sinificant ifferences between the layouts. Unless state otherwise, Mixin-DAC A is iscusse. The 16 bit converter is semente into a 6 bit unary part an a 10 bit binary part. The ata ecoin for the 63 unary current cells is one by a prorammable ecoer, which is also use for calibration similar to [3]. The sort-an-combine alorithm calibrates the static mismatch of the current sources an timin mismatch of the ata switchin in the switche current cells of the output stae. Besies the minimum require 63 unary current cells, there are a number of reunant current cells. These reunant current cells are use for outlier elimination in the calibration alorithm. The current cells with the most eviatin behavior are isable urin normal operation. The performance of the Mixin-DAC is mainly etermine by the output stae. The output stae enerates the output current, an is iscusse in Section The LO sinal is enerate by the LO river from the external LO in sinal. This river is require to have a low output impeance since it nees to rive the LO istribution tree an the ate capacitance of the mixer transistors. The LO river is iscusse in Section The triple-well process technoloy enables usin a separate bulk voltae if esire. An elevate bulk voltae is use for a number of transistors in the output stae, in orer to raise the absolute operatin voltaes of these transistors. The eneration of this elevate bulk voltae is iscusse in Section 11.5.

125 11.2. Architecture 111 Mixin-DAC B 3.3V 25Ω 25Ω Vout Vout LOin M9 Vb1 Vc M8 M8m M9m Vb1 Vm Vc LO LO LO Datain Clkin LO I blee,oc Error measurement LO river: Section V Ref. + - Vb1 LO Vb1 M4 M5 M6 M7 1.2V Data M2 M3 Data Pro. ecoer 16 Sinal processin 63MSB +10LSB I blee,mix M1 V2 M0 V1 I blee,mix I blee,oc Data path: Section 11.6 Current cell Vb1 Vb1 Ref. Elevate bulk en.: Section 11.5 Serial interface Output stae: Section 11.3 Fiure 11.1: Overview of Mixin-DAC system Mixin-DAC A

126 112 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC The baseban ata is provie externally by the Data in sinal. After processin, the sinal is ecoe to the semente coin of the output stae. Latches an rivers synchronize the sinal an amplify it to the esire amplitue. This ata path is iscusse in Section Output stae An overview of the output stae is shown in Fiure Both the schematic (see Section ) an layout (see Section ) of the output stae are important for achievin hih performance. out I out I meas I meas I out LO V c V m M 8 M 8m M 9m M 9 V c V V b1 m V b1 V c OutCasc,s LO V lohih 1.2V V b1 enable Local biasin V 2 en V 3 M 4a M 2a M 1a M 0a V b1 Iblee,oc M 4 V b1 mix,cs M 3a Data M 1b Iblee,mix M 0b LO M 5 M 6 M 2 M 3 ata,cs M 1 V b1 Data M 1c M 0c LO M7 V b1 Iblee,mix V lohih 1.2V M 1 Iblee,oc M 0 V 1 M 0 Fiure 11.2: Schematic of output stae Schematic Acurrentcellcontainsacascoecurrentsource(M 0, M 1 ), basebanata switches (M 2, M 3 ), mixer switches (M 4 -M 7 ) an output cascoes (M 8, M 9 ).

127 11.3. Output stae 113 The array of current sources is rawn separately from the other part of the current cell to inicate that there is a relatively lare spacin between those two parts in layout while the current sources themselves are close toether. The measurement probes (M 8m, M 9m ) for the error measurement of the calibration can iniviually connect each current cell to the measurement circuit urin calibration. The blee currents have cascoin at the same levels as the path of the main sinal current. This is to ensure a maximum output impeance, to protect the thin-oxie evices an to minimize parasitic capacitances at the sensitive noes OutCasc, s an mix, cs. Besies the cascoe transistors M 1,M 8 -M 9, the switchin transistors (ata switches M 2 -M 3 an mixin transistors M 4 -M 7 ) also act as cascoes. This multi-level cascoin stratey ensures that each function of the current cell is isolate from the other functions. Some state-of-the-art Mixin-DACs combine multiple functions in one transistor, which hampers the separate optimization of each function. Examples of combinin functions are: use the current source transistor also as mixer[5, 10, 11, 13, 13], use the current source also as Data switch [29], or combine the function of the Data an LO switch [79]. The separate transistor level per function of the propose architecture enables the precise optimization of the implementation of each function. Aitional cascoin (M 1,M 8,M 9 ) an blee currents are use to protect the most sensitive noes an increase the output impeance Output cascoe The output cascoe (M 8,M 9 in Fiure 11.2) isolates the sensitive internal noes of the output stae from the lare output voltae swin. At the output cascoe, three error-sources introuce non-linear istortion: non-linear rain impeance, switchin of the rain impeance, settlin of the source noe. The non-linear rain-impeance mainly comes from the ate-source an aterain capacitance (C s an C ), which both oriinate from the channel of the output cascoe. The manitue of this non-linear istortion epens on the size of the capacitances an on the non-linearity of the capacitance. The non-linearity of these two capacitances stronly epens on the output common-moe voltae, iven a fixe ate voltae V c. This epenence is illustrate in Fiure 11.3, where V out cm is the common-moe output voltae. The shape of the waveform is ifferent than iscusse in Section 5.2.1, since that section iscusses a thin-oxie transistor while the final output cascoe, iscusse in this section, is implemente usin a thick-oxie transistor. The

128 114 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC rain voltae, which is the Mixin-DAC output voltae, etermines the shape of the channel in the output cascoe, an thereby the non-linearity introuce bythechannelmoulation. ForlowV out cm, theoutputcascoeisinthelinear reion where C s an C are both connecte to the output throuh a low resistance. Hence, they both fully contribute to the non-linearity. When V out cm is increase, the output cascoe transistor is more in saturation, C s counts less an the non-linearity is less. The optimum (at 2.8V for the example of Fiure 11.3) is ue to partial cancellation of the non-linearity of the two capacitances. This cancellation effect is very stable an is present in all simulations. Hence, V c is chosen such that the output voltae is in this optimal reion IMD3 [Bc] C s C V out_cm [V] Fiure 11.3: Linearity epenence on the output common-moe voltae The size of the capacitance is minimize by reucin the area of the transistor. The with/lenth ratio of the output cascoe (W oc /L oc ) is minimize while respectin the mixer voltae hearoom require for saturation. At a iven W oc /L oc ratio, the area is minimize by minimizin L oc. However, reucin L oc increases the non-linearity of the C s an C capacitance values. Hence, there is an optimal value of L oc, which is emonstrate in Fiure The secon non-linearity is enerate ue to the switchin of the output cascoe, which enerates a ata-epenent output capacitance [65]. This capacitance aain epens on the C s an C capacitances. The ifference of the capacitance values between the on- an off-state can be reuce by

129 11.3. Output stae IMD3 [Bc] capacitor size cap. non-linearity L [µm] Fiure 11.4: Linearity epenence on the lenth of output cascoe ain blee currents. The total blee current throuh the output cascoe is the sum of the blee current throuh the mixer (I blee,mix ) an the aitional blee current (I blee,oc ): I cascbias = I blee,mix +I blee,oc. (11.1) The thir error source which enerates non-linear istortion is the settlin of the source noes of the output cascoe (OutCasc,s noe in Fiure 11.2). Incomplete settlin causes inter-symbol-interference(isi) for transitions of the Data sinal, which causes non-linear istortion. Incomplete settlin after LO sinal transitions o not cause ISI since the LO sinal switches in each current cell, an hence there is no cell-epenent behavior which can cause non-linear istortion. The ISI ue to incomplete settlin at the Data transitions can also be reuce by increasin I cascbias. The epenence of the IMD3 value on I cascbias is shown in Fiure In this simulation, the with of the output cascoe transistors linearly epens on the maximum current throuh the output cascoe to keep the occupie voltae hearoom constant. For low values of I cascbias, increasin I cascbias improves the IMD3 value since the ISI effect is reuce. However, when I cascbias is too hih, the transistor size of the output cascoe has to increase sinificantly, increasin the impact of the non-linear rain impeance an thereby increasin the non-linear istortion. The optimum epens on the value of the parasitic capacitance of the output cascoe source noe C OutCasc,s. For this esin, the optimal I cascbias is between 10µA an 100µA for C OutCasc,s =5fF.

130 116 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC 70 IMD3 [Bc] ISI at OutCasc,s & output cascoe capacitor switchin non-linear output impeance I cascbias [µa] Fiure 11.5: Linearity epenence on the total blee current throuh the output cascoe The output cascoe also acts as a selection switch. Toether with another set of transistors (M 8m,M 9m ), the output cascoe selects the output tree or the measurement tree as the output network for the current cell Mixer The mixer operates at the LO frequency an hence its parasitic capacitances are critical. Therefore, ieally the mixer shoul be implemente usin thin-oxie evices. This woul result in a challene to fit 4 cascoe transistors in a voltae hearoom of only 1.2V, which is the maximum voltae for thin-oxie evices without reucin the reliability. Decreasin the voltae hearoom for each level of transistors requires the W/L ratio of the transistors to be larer which increases the size of the parasitic capacitances. Larer parasitic capacitances result in lower switchin spee for the switches an larer non-linearity. The lower voltae hearoom also results in more mismatch for the current-source transistor which also reuces the linearity. The state-of-the-art Mixin-DAC architectures solve the voltaehearoom problem by reucin the number of stacke transistors. This is one by combinin multiple functions in one transistor level, which hampers the separate optimization of the implementation of each function leain to a reuction in the performance, as iscusse in Section Another solution is to omit cascoin of the current source [18 20,22], which results in a ecrease in the performance. A thir solution is to apply a neate bulk voltae

131 11.3. Output stae 117 to the current source an its cascoe [79], which requires a neative supply voltae. Usin a thick-oxie transistor as mixer is also a solution, but this results in a lower switchin frequency or a hiher power consumption. Hence, these solutions are not practical or result in inferior performance. The propose architecture uses a solution which oes not have the aforementione isavantaes. Utilizin the triple-well technoloy, the operatin voltaes of the mixer are shifte. The bulk voltae of the mixer transistor is elevate by approximately 0.6V. If the absolute voltaes of the terminals of the mixer transistor are between 0.6V an 1.8V, the relative voltaes between the mixer terminals are lower than 1.2V an the reliability is not compromise. The total available voltae hearoom for the thinoxie transistors is increase to 1.8V, supplyin sufficient aitional voltae hearoom for the thin-oxie mixer transistors. Since all functions are implemente usin a separate level of transistors, an a current-source cascoe is applie to protect the sensitive current-source rain noe, maximum performance is achieve. No impractical neative supply voltae is necessary. There are three mechanisms which enerate non-linear istortion relate to the local mixer. One error mechanism is mismatch in the mixer which enerates timin errors. This is iscusse in Chapter 5 an Chapter 6. Another error mechanism is relate to the LO sinal transitions which enerate a isturbance on the voltae of the common-source noe of the mixer (V mix,cs in Fiure 11.2), see error mechanism 6 in Section The waveforms are shown in Fiure 11.6, which shows the output waveform an the isturbance on V mix,cs. The size of the isturbance, inuce by a LO transition, epens on the settlin value of V mix,cs. Due to a limite output impeance, the settle V mix,cs value epens on the output voltae. Since there is parasitic capacitance on this noe, the output-epenent isturbance consumes sinal chare an hence introuces non-linear istortion. The thir error-source is the settlin of V mix,cs when the Data sinal switches. The mixer common-source noe settles slowly. When the ata switches aain before V mix,cs is settle, ISI occurs, which enerates non-linear istortion. This settlin behavior is shown in Fiure The non-linear istortion ue to the latter error-source can be reuce by increasin the blee current I blee,mix. Increasin I blee,mix ecreases the settlin time an hence reuces the ISI. The require blee current also epens on the input sinal frequency, since a hiher frequency results in the Data sinal switchin more frequent an thus the ISI occurrin more often. This relationship is emonstrate in Fiure 11.8 an Fiure To isolate this specific error source f LO an F S are chosen to be a low value (1GHz), which eliminates the other non-linearities. In this simulation, the

132 118 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC [V] Vout Vmix,cs t [ns] 5.0 Fiure 11.6: Mixer transitions cause isturbance on V mix,cs which introuces non-linear istortion Vout [V] ISI Vmix,cs t [ns] Fiure 11.7: Incomplete settlin of V mix,cs after Data transitions can cause Inter-Symbol-Interference (ISI) which causes non-linear istortion with of the mixer transistors linearly epens on the maximum current throuh the transistor. The total blee current throuh the output cascoe is kept constant. The fiures clearly shows the impact of the Data relate ISI, which is present at hiher input frequencies. Increasin I blee,mix

133 11.3. Output stae 119 ecreases this istortion. However, for very hih I blee,mix, the transistor sizes become sinificantly larer, which increases C OutCasc,s, increasin other non-linearities. A hih blee current also results in a hih power consumption an lare area. The chosen blee current is 30µA, which is a trae-off between performance, power consumption an area ISI at mix,cs C OutCasc,s IMD3 [Bc] f in =151 MHz f in =307 MHz I blee,mix [µa] Fiure 11.8: IMD3 epenence on blee current an input frequency The capacitive loa for the LO river shoul be as small as possible. Therefore, the area of the mixer is minimize. The lenth of the mixer (L mix ) is chosen 80nm, which is almost the lowest value. Choosin a lower value oes not result in a sinificant lower capacitance but increases the mismatch sinificantly which worsens the timin errors. The with of the mixer transistor (W mix ) is minimize for two reasons. The first reason is minimizin the capacitive loa on the LO sinal. The secon reason is to minimize the parasitic capacitances at the source an rainofthemixerintheoutputstae. Thecapacitanceatthesenoeserae the linearity. However, minimizin W mix is limite by the available voltae hearoom. Moreover, for scalin of the binary cells, a mixer transistor consists of 8 unit elements, which limits the minimum total W mix. Choosin less unit elements will hamper the matchin of the binary cells an erae the SFDR, see Section The ISI ue to the C mix,cs introuces IMD3 an sinle-ene HD2. Increasin W mix increases this parasitic capacitance. Since the external balun has a limite common-moe rejection ration (CMRR), also the ifferential HD2 of the output sinal is affecte. The HD2 epenence on W mix is shown

134 120 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC IMD3 [Bc] I blee,mix =3 µa (=1 %) I blee,mix =10 µa (=3 %) I blee,mix =30 µa (=10 %) I blee,mix =100 µa (=32 %) I blee,mix =300 µa (=96 %) C OutCasc,s ISI at mix,cs f in [MHz] Fiure 11.9: IMD3 epenence on input frequency an blee current in Fiure S.E. HD2 [Bc] W mix [µm] Fiure 11.10: Sinle ene HD2 epens on the mixer with

135 11.3. Output stae Data switches & cascoe current sources The ata switches an cascoe current source are ientical to the implementation of the baseline DAC. The sizin of the Data switches an current source cascoe are optimize for voltae hearoom for the current source an for minimizin the parasitic capacitances C mix,cs an C ata,cs. These transistors consist of a number of unit elements to offer oo scalability for the binary current cells Local biasin an ecouplin To prevent crosstalk between the various unary current cells, local biasin an ecouplin is use. A lobal ate-source voltae is istribute to enerate a local bias current in each current cell. This bias current is use to locally enerate the ate voltae of the current-source cascoe (V 2 ) an output cascoe (V c an V m ). Local ecouplin of the sensitive voltaes ensures that isturbances are filtere out. All static voltaes of transistors hiher than the current source cascoe (Data switch, mixer, output cascoe an blee-current cascoes) are ecouple to the 1.2V supply. In this way, almost all voltaes in the current cell are relative to the 1.2V supply. Usin a one common reference prevents isturbances between multiple references, which coul enerate spurious components in the output Binary cells The response of the binary current cells shoul be an exactly scale version of the response of the unary cell. An example of the ifference between the output spectrum of sub-optimal scalin an optimize scalin is shown in Fiure The scalin of the binary part is also iscusse in Chapter 9. Three techniques are employe to achieve optimal scalin. The first technique is that each transistor in the unary current cell consists of 2 u unit elements, where u is an inteer number. In this way, binary scalin is as easy as isconnectin a number of the transistor unit elements. Each binary cell has half the unit elements enable compare to the previous binary cell. In the unary current cell, the mixer transistors consist of 8 unit elements each. This means that unit-element scalin is possible up to the thir binary cell (B9, B8 an B7). For the other binary cells the with of the transistor nees to be scale to approach the accurate scalin. The output cascoe transistors consist of 4 unit elements, hence unit-element scalin is possible for B9 an B8. However, the with of the unit element transistors is such that with-scalin is possible an acceptable results are achieve.

136 122 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC 20 B9 layout version 1 B9 layout version 2 40 Differential spectrum [Bm] Frequency [MHz] Fiure 11.11: Spectrum of the simulate back-off output sinal with sub-optimal an optimize B9 layout The secon technique is the scalin of the parasitic capacitances. When the parasitic capacitances are not accurately scale, the time-constant of the noes are not ientical an hence the response is ifferent. The scalin of the parasitic capacitances requires a scalable layout, which is iscusse in Section The thir technique is to make the unary an binary cells ientical for the rivin sinals. In that way, the Data river an the LO istribution tree o not nee to be altere for the binary cells an can be ientical for all current cells. The Data river an the LO istribution tree nee to sense the same input impeance for each unary an binary current cell. However, only a subset of the Data an LO unit transistors are use in the main output branch for the binary cells. The remainin unit transistors are also connecte to the rivin Data an LO sinals, but their rain-source current is use in a replica branch. This replica branch has approximately the same behavior as the output branch such that the total impeance for the rivin sinals is ientical to the unary current cells. A schematic representation of the replica branch is shown in Fiure 11.12, where the biasin an the blee currents are omitte for clarity. The use of a replica branch also ais the scalin of the parasitic capacitances. Since the replica branch has ientical behavior with respect to the output branch, parasitic capacitances between corresponin noes of the replica branch an main branch o not conuct error chare an hence

137 11.3. Output stae 123 I out I out M 8 M 8r 3.3V M 9r M 9 V c V b1 V b1 V c M 4r M 5r M 6r M 7r LO V b1 LO Vb1 LO M 5 M 6 M M 7 4 Data M 2r M 3r Data M 2 M 3 V 2 M 2r M 1 V 1 M 0 M 1r Fiure 11.12: Binary current cell with ultimate replica branch are not important Layout The layout of the output stae is key to achievin a hih spectral purity. Reucin parasitic capacitance values at crucial noes prevents crosstalk, ISI an other error sources which cause non-linear istortion Floorplan output stae The floorplan of the complete output stae is shown in Fiure In this floorplan, the lenth of the RF sinal path is minimize. Therefore, the LO istribution tree, mixer, output cascoe an output tree are close toether. The track of the Data sinal connects the Data rivers to the Data switches. The sample rate of the Data sinal is lower than the LO frequency, an the Data sinal switches only at the input frequency. Hence, the istance of the Data track is less important than the istance of the tracks of the RF sinals. Also less important is the istance between the biasin an current source

138 124 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC array on the one han an the other parts of the output stae on the other han. ~0.9 mm Diital Data Clk LO Data river & latch Data switch & C.S. cascoe Output cascoe & mixer DNWELL ~1.1 mm Measure out Biasin, ecouplin & blee currents Out Current source array Unary Binary Unary Fiure 11.13: Floorplan of the output stae with Data rivers an latches The current cells are positione in vertical slices, where shielin between the slices prevents crosstalk. The binary cells are positione at the center of the current-cell array, while the unary current cells are positione on either sie of the array. The layout of a current cell influences the impact of processin imperfections, e.. ue to shain effects in the processin. In the propose layout, half of the current cells have inversely polarize Data an LO connections. Hence, layout unbalances ue to the processin are compensate when two neihborin cells are both enable. This is true for most cases, since the current-cell array is controlle in a thermometer fashion.

139 11.3. Output stae Floorplan current cell The floorplan of one slice is shown in Fiure 11.14, which is a more elaborate version of the floorplan of Fiure The parasitic capacitance of the internal noes of the current cell nees to be minimize, hence the currentsource cascoe, ata switch, mixer an output cascoe are roupe close toether. Tracks with hih frequency sinals are short while lower-frequency tracks an biasin connections are allowe to be loner. The ecouplin of the locally enerate voltaes an the istribute voltaes is split in two parts: one part close to the sinal path for hih frequency ecouplin an a part further away for the lower frequency ecouplin. The biasin block contains the eneration of the blee currents an the local voltaes for the ates of the current-source cascoe an output cascoes. Latch an river LO tree CS cascoe Data switch Decouplin Mix. Output casc. Output an measurement tree Decouplin Blee current source Biasin Output cascoe biasin Current source array Fiure 11.14: Floorplan of one slice of the output stae, 90 rotate Output cascoe layout The most important parasitic capacitance is at the source of the output cascoe (OutCasc, s in Fiure 11.2), since it experiences the larest couplin to the lare output voltae swin. This capacitance shoul be minimize an shoul be mae maximally scalable for the binary cells. The layout stratey for these requirements is illustrate in Fiure In this fiure, the measurement cascoes an the replica branches are omitte. The blue blocks are the transistors. The sources of those transistors are connecte to the OutCasc,s noe, while the rains are connecte to the out noe which is the output of the Mixin-DAC. The black lines represent layout connections. The lenth of the OutCasc, s connection is partly scalable an partly fixe. The scalin of the parasitic capacitance can be perfecte by tunin the with of the track. Tunin of the track with is also require for the output cascoe of binary current cells B7 to B0.

140 126 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC out out out out out out Dummy s s s s s s #4 s s s s s s #3 s s s s s s #2 #1 s s s s s s s s s s s s Scalable part Dummy s OutCasc,s s OutCasc,s s OutCasc,s s OutCasc,s s OutCasc,s s OutCasc,s Fixe part Unary B9 B8 Fiure 11.15: Layout stratey for the output cascoe Mixer layout The mixer layout is specifically challenin because of the cross connections of the mixer. The layout stratey of the mixer is similar to that of the output cascoe an is illustrate in Fiure In this illustration, the ummy transistors an the replica branches are omitte. This layout stratey is focuse at a scalable OutCasc, s noe, minimal parasitic capacitance at the OutCasc, s noe, an ifferential matchin. Minimal parasitic capacitance of the OutCasc, s noe an scalability of the OutCasc, s noe are both achieve by connectin this noe without horizontal connectin wires, as is the case for the LO an mix,cs noes. However, there still is a part of the OutCasc,s track which has a fixe lenth. Tunin of the with of this track perfects the binary scalin of the parasitic capacitance of this noe. For ifferential matchin, all corresponin noes (LO an LO, OutCasc,s an OutCasc,s, mix,cs an mix,cs) have the same lenth of wirin. However, some tracks see ifferent environments an hence have ifferent parasitic capacitances to ifferent noes. Therefore, sinle ene HD2 is converte to ifferential HD2 ue to non-ieal matchin of these parasitic capacitances.

141 11.3. Output stae 127 OutCasc,s LO OutCasc,s LO OutCasc,s LO OutCasc,s LO OutCasc,s LO OutCasc,s LO OutCasc,s: Fixe part #1 #2 #3 #4 #5 #6 #7 #8 s s s s s s s s s s s s Scalable part mix,cs mix,cs mix,cs mix,cs mix,cs mix,cs Unary B9 Fiure 11.16: Layout stratey for mixer B Layout of cascoe current source, ata switches an biasin The layout of the current source, current source cascoe, ata switches an biasin is aopte from the layout of the baseline DAC. The same approach as for the mixer an the output cascoe is employe: unit elements for scalin, layout of the connection tracks for scalin, an minimization of parasitic capacitances at sensitive noes LO an output tree layout For hih spectral purity, the elay timin errors shoul be minimize, see Chapter 6. Unbalance in the istribution of the LO sinal or output recombination can cause elay timin errors. Hence, a balance tree structure is use to implement these two functions. For the LO istribution tree, the loa of all unary an all binary cells is equal. For the binary cells, this is achieve by utilizin the replica approach which is iscusse in Section The tree structure is base on a binary tree. The principle of the tree, which is aopte from the tree esin of the baseline DAC, is illustrate in Fiure The various metal layers in the chip can be use to exchane lateral area occupation with the number of occupie metal layers. The tree is characterize by the elay between the root an the leafs. The oal of the tree structure is o minimize the elay ifference between the leafs.

142 128 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC Root L1 L2 L3 Leafs L t Fiure 11.17: Principle of the binary tree for the LO an output sinal Each level of the tree (L1, L2,..., Lt) smooths this elay ifference. All levels consist of 2 L connections to the next level, where L is the number of the level. Since the number of cells is 80, which is not a power of two, the last level L t oes not contain 2 t levels, but 80 levels. The hiher t, the lower the elay ifferences between the leafs. The relative elay for the LO tree is shown in Fiure The x-axis is the spatial position of the current cell in the array of current cells, while the y-axis is the elay error with respect to the averae elay. As can be seen in the plot, the binary cells are positione at the center of the currentcell array, while the unary current cells are positione on either sie of the array. These simulation results are obtaine usin RC extractions. For hiher frequencies or hiher accuracy, an EM simulation woul be more appropriate. The oriinal confiuration is a tree with 7 levels an with the position of each connection between levels at the theoretical position. However, even with this tree structure the elays of the 80 leafs are not ientical. Due to ee effects the elay istribution is incline towar the mile. An ue to non-ientical capacitive loa at the binary cells, the elay for the binary cells is ifferent than the elay of the unary cells. One optimization technique that is applie, is to shift the connections between the various levels away from the center of the tree. This compensates for the rotate elay istribution. It can be observe that the elay sprea of the binary cells is larer than that of the unary cells. However, since the influence of the binary cells is much smaller than the influence of the unary cells, the elay sprea of the binary cells is allowe to be orers of manitue larer than for the unary cells. Therefore, the larer elay sprea of the binary cells is acceptable an no compensation is require. The same approach is use to esin the output recombination tree, which is shown in Fiure For the optimization of the output tree, the

143 11.4. LO river Relative elay error [fs] Initial (σ Unary =4.5fs) 25 Optimize (σ Unary =1.8fs) Binary Position Fiure 11.18: Relative elay error of each enpoint of the LO tree to the root, both for initial an optimize layout followin methos are use: shiftin of connections between levels, wienin of the last level, tunin of the leaf wirin of the binary current cells. The output capacitance of the binary cells is not similar to that of the unary cells. Therefore, the with of the wirin between the output of the binary current cells an the last level of the tree is optimize to equalize the RC time constants an remove any excessive elay timin errors. The stanar eviation of the elay errors of the unary part of the LO tree an the output tree are 1.8fs an 7.2fs respectively, which are both smaller than the require 55fs of Section LO river The LO river is require to rive the LO switchin transistors, which are connecte by the LO tree. The LO tree an the LO transistors cause a lare parasitic loa at the output of the LO river. The timin errors between the LO sinals at the ates of the LO transistors is require to be minimal. Therefore, the LO river is a lobal river an connecte to the LO transistors via a balance tree. The LO rive chain consists of two cascae CML rivers, a reulator for the local supply voltae an a reference voltae enerator for the reulator. The schematic of the LO rive chain is iven in Fiure

144 130 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC Relative elay error [fs] Initial (σ Unary =23fs) 120 Optimize (σ Unary =7.2fs) Binary Position Fiure 11.19: Relative elay error of each current-cell output to the root of the output tree, both for initial an optimize layout Reference V 3.3V Reulator M f3 M f2 M r2 I blee,mix M f1 V ref V b1 V 1.2V M r0 M r1 I re M r3 M r4 I biaslo V lohih LO in LO in V indc 100Ω R Lp M p1 Vb1 R Lp M p2 R Lm M m1 V b1 R Lm M m2 LO LO VinDC V 1 M p0 M m0 Pre-river Main river Fiure 11.20: Schematic LO rive chain

145 11.4. LO river Drivers Both the main LO river an the pre-river are implemente usin a CML buffer to prevent sinal-epenency in the supply current. It also enables easy control over the sinal levels an the cross-over point. The rivers use thin-oxie transistors as switches (M p1, M p2, M m1 an M m2 ) to minimize the parasitic capacitances an thus enable hih-spee operation. The LO sinal voltae levels are above 1.2V, hence the bulk voltae of the switchin transistors is the same elevate bulk voltae as the mixer switches in the output stae. The LO frequency of 4GHz requires a low RC time constant for the LO river. The lare LO tree parasitic capacitance, i.e. approximately 1pF, forces a low loa resistance for the CML river. The loa resistor (R Lm ) is chosen to be 20Ω. Since the W/L of the mixer is low, the swin of the LO sinal shoul be lare, i.e. 800mV. This requires a tail current of 40mA throuh M m0. The pre-river only requires I tail =10mA (throuh M p0 ) an R Lp =80Ω for fast operation. The input of the pre-river contains a 100Ω ifferential resistor for termination of the transmission line of the external LO in sinal. The input of the pre-river also contains resistors for the biasin of the input transistor pair, hence external capacitive couplin is preferre. The LO river has a number of iital inputs. The iital input can confiure the LO sinal to be static. In that case, the mixer transistors in the output stae become normal cascoes an the Mixin-DAC becomes a Nyquist DAC. For calibration purposes, the polarity of the static LO sinal can also be controlle. For clarity reasons, the implementin circuits of both functions are not shown in the schematic of Fiure DisturbancesatthesupplyoftheLOrivers(V lohih )coupletotheoutput of the Mixin-DAC throuh two couplin paths. One couplin path is that low frequency isturbances (at f ist ) first mix with the LO frequency, an then appear at the LO sinal. Hence, the output of the Mixin-DAC has isturbances at f in +f LO +f ist. The secon isturbance path is that a hih frequency isturbance at f ist irectly couples to the Mixin-DAC output at f ist. This couplin path mainly causes sinle-ene istortion at the output. For achievin the esire spectral purity, these isturbances nee to be smaller than approximately 10mV. Therefore, the reulator of the local supply voltae is optimize for rejection of isturbances from the 3.3V supply. When expectin a isturbance in the orer of 50mV on the 3.3V power supply, the reulator shoul have a power supply rejection ration (PSRR) of approximately 14B.

146 132 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC Local supply voltae The internal reulator enerates the local power supply V lohih for the LO rivers from the 3.3V supply voltae. The reulator also ensures that the local supply voltae of the LO river remains clean an unistorte. A low output impeance is necessary to prevent moulation of the V lohih ue to variations in the current throuh the LO rivers. The feeback confiuration provies a low output impeance for low frequencies. The secon stae of the reulator is a source follower, which supplies 50mA to the LO rivers an hence has a very lare area an lare parasitic capacitances. Therefore, the banwith of the feeback loop is only 8MHz. The source follower confiuration provies a low output impeance for frequencies above 8MHz. For very hih frequencies, ecouplin of V lohih results in a low output impeance. The ecouplin capacitors are not shown in the schematic. Combinin these three features, the worst case output impeance is 5Ω. The PSRR of the reulator is 15B at the worst corner-case. This is better than the require 14B, hence isturbances below 50mV on the 3.3V power supply will not cause the spectral purity to be worse than the taret Reference enerator The reference V ref for the reulator is enerate from the 1.2V supply an a ioe-connecte transistor. This transistor has the same sizin an layout as a mixer transistor in the output stae. The current throuh the transistor is equal to the blee current I blee,mix. Hence, the reference voltae is: V ref = 1.2V + V s (I blee,mix ). In this way, the voltae at the source of the mixer never excees 1.2V, an the ata switches are protecte aainst an excessive voltae. The ratio of the current mirror in the reference can be proramme throuh a iital interface. By controllin the current throuh the reference ioe, V ref can be proramme for optimal performance Driver for elevate bulk voltae The schematic of the circuit which enerates the elevate bulk voltae is shown in Fiure It is a simple two-stae amplifier. The elevate bulk voltae is approximately 0.6V an is reference to the 1.2V supply an ecouple to the same power supply. This referencin to the 1.2V power supply is because all transistors in the output stae which are connecte to the elevate bulk voltae are also referre to the 1.2V supply. Thanks to the

147 11.6. Data path 133 lare ecouplin capacitor, the output pole is ominant an the amplifier is very stable. The reference current throuh the resistor is prorammable. R ref V 1 V 1.2V M 0 M 6 C ecap M 1 M 2 Vout =V b1 I ref M 3 M 4 M 5 Reference Buffer Fiure 11.21: Schematic for eneratin the elevate bulk voltae 11.6 Data path The ata path consist of a serial interface, iital sinal processin, a prorammable ecoer, latches an rivers. The implementation of these functions are ientical to the implementation in the baseline DAC. The iital sinal processin can be use to apply simple operations, such as: upsamplin, filterin, mixin with a sine-wave. These operations can be applie in the complex sinal omain an hence the two Mixin-DAC cores can operate with I/Q sinalin. The iital sinal processin also contains controllable compensation for mismatch in the analo part of the I/Q paths. The ESD evices of the LO inputs an the iital power supply are connecte to the same power-supply rail. This causes couplin between the LO sinal an the iital supply voltae. Some of the iital operations are execute at 1/8 th of the sample rate, which causes harmonics in the supply voltae at n F S /8. Due to the couplin of the ESD evices, in measurements spurious components at those frequencies can appear in the LO sinal an also in the Mixin-DAC output. Due to time limitations, the ESD omains coul not be separate to prevent this couplin. For the latches an rivers, CML loic is use. This prevents ataepenent current rawn from the power supply an enables control of the crossover point of the Data sinal.

148 134 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC 11.7 Full system simulations The total area of the implementation of one Mixin-DAC core (Mixin- DAC without iital sinal processin) is 1.6mm 2. System level simulations are performe on the complete chip excluin iital sinal processin an with packae moel. The most important circuits are moele with C- extracte moels. A wie view of the resultin spectrum with full-scale sinal is shown in Fiure 11.22, where both the sinle ene an the ifferential output sinal are shown. The main output components are aroun f LO =3.9GHz. A zoomin of the output Nyquist ban above f LO is iven in Fiure The main performance specifications are: IMD3=-82Bc an SFDR RB =78Bc. The SFDR RB is limite by an IMD2 component at the ee of the RB, close to the LO frequency. When omittin the IMD2, the hihest spur is the IMD3 component at -82Bc Sinle ene Differential Differential spectrum [Bm] Frequency [GHz] Fiure 11.22: Wie spectrum of the simulate full-scale output sinal of Mixin-DAC A Funamental limits of the IMD are the output couplin to internal noes an the mismatch of the mixer. The couplin of the output to internal noes is relate to the output cascoe. Increasin the cascoe size improves the cascoe function, but also increases the non-linear capacitance values. Mismatch in the mixer causes timin errors. The mismatch can be reuce by increasin the size of the mixer. This will increase the parasitic capacitances in the mixer which will increase the non-linearity ue to couplin of the output

149 11.8. Conclusion Sinle ene Differential Differential spectrum [Bm] Frequency [MHz] Fiure 11.23: Nyquist spectrum of the simulate full-scale output sinal of Mixin-DAC A voltae to the internal noes. Practical error-sources also limit the performance. The IMD2 can be cause by imperfect balancin of the layout of the current cells, ISI at the source of the mixer an couplin between bon wires an wirin on the chip. Practical limitations on the achieve IMD3 can be ue to capacitive couplin of on-chip sinals. For -16B FS /tone output power, the simulate spectrum is shown in Fiure The main performance specifications are: IMD3=-93Bc an SFDR RB =80Bc. The SFDR in back-off is limite by the matchin of the binary cells. Corner simulations show only small eraation of the performance metrics. The simulation results are close enouh to the formulate tarets to justify fabrication of this esin for verification Conclusion To valiate the propose architecture, a 16 bit 2GSps 4GHz Mixin-DAC is esine. The esin of the output stae is crucial for achievin the esire spectral purity. Usin the correct techniques, the esire performance can be achieve. Crucial techniques are: ivin each current cell an ientical environment,

150 136 Chapter 11. Desin of a hihly linear wie-ban Mixin-DAC 0 20 Sinle ene Differential Differential spectrum [Bm] Frequency [MHz] Fiure 11.24: Nyquist spectrum of the simulate output sinal of Mixin-DAC A in back-off isolatin the current cells from one another, isolatin the internal noes of the current cells from the output sinal, implementin each function of the output stae with a separate level of transistors, usin an elevate bulk voltae for improvin voltae hearoom. The verification simulations show that the expecte performance is close to the taret specifications. The expecte an simulate performance is limite by the couplin of the output to internal noes, output-cascoe capacitances, mismatch-inuce timin errors of the mixer, couplin between sinals ue to the bonwires an on-chip wirin, an matchin of the binary cells.

151 12 Experimental results The esin propose in the previous chapter has been fabricate an measure. This chapter presents the measurement results an compares these results with the simulate performance an with the state-of-the-art performance. The performance limitations are analyze an suestions for improvements are iven. The measurement results show that the propose architecture can achieve hih linearity an lare banwith at GHz frequencies. This chapter is base on a paper submitte to the IEEE ISSCC 2015 conference [81] Introuction The esin presente in Chapter 11 has been fabricate. A photo of the ual-mixin-dac ie with two Mixin-DAC cores an the iital fronten is shown in Fiure This chapter presents the measurement results of that chip. The measurement setup is iscusse in Section The baseban performance (LO river in static state) is iscusse in Section The performance of the Mixin-DAC with the mixer enable, is iscusse in Section 12.4 an Section 12.5 for sinusoial sinals an raio sinals respectively Measurement setup The setup for measurin the Mixin-DAC performance is shown in Fiure The two main parts of the measurement setup are the equipment an the measurement boar Measurement equipment The 16-bit iital ata for the Mixin-DAC is enerate by the ata eneration boar. The output of the Mixin-DAC is observe by a spectrum

152 138 Chapter 12. Experimental results Mixin-DAC core 1 LO river Current-source array switches & cascoes Biasin Mixin-DAC core mm V b1 river Diital front-en 3.7 mm Fiure 12.1: Photo of the fabricate chip Power supplies Measurement PCB Spectrum analyzer ata eneration 16 bit Test chip Clk LO Power splitter Power splitter Sinal enerator Control Phase etector Phase reference Phase Sinal enerator Computer Fiure 12.2: Measurement setup

153 12.2. Measurement setup 139 analyzer. The sample clock an LO sinal are sine-wave sinals, enerate by sinal enerators. As iscusse in Section , the phase between these two sinals is important for linearity. Therefore, the sample clock an LO sinal are both split usin power splitters. One sie is connecte to the Mixin-DAC an the other sie is connecte to a phase etector. The phase etector is actually an oscilloscope which measures the time ifference between the zero-crossins of the two sinals. This time ifference is transferre to the computer, which compares it to the phase reference set by the user. The computer calculates the phase error between the actual clock-lo phase an the esire phase. The user can initiate the phase correction of the LO sinal enerator, so the computer oes not execute phase corrections autonomously urin sensitive measurements. The settins of the ata eneration boar an the Mixin-DAC are confiure usin the computer. Power supplies provie power to the Mixin- DAC Measurement boar The Mixin-DAC measurement boar is use to interface between the measurement equipment an the Mixin-DAC chip. An overview of the schematic of the measurement boar is shown in Fiure Power LO se,a V 3.3V Control LO A 100Ω 50Ω 50Ω TC-43X+ (1:1) V out,a T 1 TCM2-43X+ (2:1) 25Ω V out,se,a Data in TC1-1-13MG2+ (1:1) 100Ω Clk 100Ω T 5 TCM2-43X+ (2:1) 100Ω LO B T 6 V out,b V out,se,a V out,se,b S 1 S 2 T 3 T 2 TC-43X+ (1:1) TCM2-43X+ (2:1) T 4 V out,se,b V out,i/q Clk se LO se,b Fiure 12.3: Measurement boar

154 140 Chapter 12. Experimental results The input an output sinals of the Mixin-DAC are all ifferential, while the inputs an outputs of the measurement equipment are all sinle ene. Therefore, transformer baluns (T 2, T 5, T 6 ) are use to convert the sinals between ifferential an sinle ene. For aitional common-moe rejection at the Mixin-DAC outputs, an aitional (1:1) common-moe transformer (T 1 ) is use. For measurements with I/Q sinalin, a branch which combines the sinle-ene outputs of the two Mixin-DAC cores is implemente with transformers (T 3, T 4 ). This aitional circuitry can be connecte by closin switches S 1 an S 2, but is normally isconnecte to not influence the sinle- Mixin-DAC measurements. All transmission lines are terminate with effective 50Ω. The Clk input of the Mixin-DAC contains an internal 100Ω termination. Toether with the external 100Ω termination an the 1:1 transformer T 5, the input impeance of the Clk in input is 50Ω. The LO A an LO B inputs are internally terminate with 100Ω. Toether with the 2:1 transformer T 6, the input impeance is 50Ω. The Mixin-DAC outputs are not internally terminate. The external termination of 100Ω ifferentially an the 2:1 transformer T 2 result in an output impeance of 50Ω. Since the output connection contains the most sensitive sinal, the output circuit of a sinle Mixin-DAC on the measurement boar is characterize. The output return loss (S22) of the output of the measurement boar with chip an connectin cable is shown in Fiure The S22 shoul be below -10B for oo suppression of the reflections. A possible cause for the two violationsat1ghzan2ghzcanbethattheoutputofthemixin-dacisnot 0 5 S22 S21 Sparameters [B] Frequency [GHz] Fiure 12.4: Scatterin parameters of the measurement boar

155 12.2. Measurement setup 141 a proper transmission line up to the 2x50Ω resistors, but is more capacitive an inuctive ue to the Mixin-DAC output capacitance an bonwires. The reflections cause by suboptimal termination can cause frequency epenent fluctuations in the sinal power an may cause eraation of the measure linearity. The insertion loss (S21) of the measurement boar an cable, from the pins of the Mixin-DAC chip to the output of the cable is also shown in Fiure The hih frequency epenent loss is ue to the loss of the transformers, the tracks on the measurement boar an the connectin cable. A photo of the measurement setup is shown in Fiure Power sources Measurement boar & ata eneration Computer Sinal enerators Spectrum analyzer Phase etector (Oscilloscope) Fiure 12.5: Photo of measurement setup Calibration The Mixin-DAC contains a sort-an-combine calibration metho [3]. This calibration compensates for the static mismatch of the current sources an timin errors of the Data switchin. The principle of the sort-an-combine calibration is to combine unary current cells with opposite errors. In the combine current cell, the errors cancel one another. Hence the combine error is much smaller than the iniviual errors. Due to the combinin of the unary current cells, the effective sementation of the converter is not the aforementione 6MSB + 10LSB, but less MSB unary bits. The combin is one twice, hence the effective sementation is: 4 calibrate MSB unary bits, 2 calibrate binary bits, 10 uncalibrate LSB binary bits. A prorammable ecoer for the binary-to-unary ecoin for the unary current cells executes

156 142 Chapter 12. Experimental results the calibration map, which contains the information about which current cells shoul be use toether. The error sources are measure usin an on-chip measurement circuit. The measure values are transferre to a computer, which calculates the most optimal combination of unary current cells, the calibration map. This map is proramme once in the chip, an is active for the remainin lifetime of the chip Baseban performance First the performance of the Mixin-DAC in baseban moe is measure. For this measurement, the LO river is confiure in static state, hence the mixer transistors only acts as a cascoe an o not mix. The baseban moe of the Mixin-DAC is not the main operatin moe an the esin is not optimize for this operatin moe. Therefore, the performance measurements at baseban are only informative. All measurements are one usin a ual-tone sinal, no separate sinle-tone sinal is enerate for SFDR measurements. The sample rate is 1.5GSps an the input sinal is a ual-tone sinal at 155.0MHz an 155.1MHz. The output spectrum of the full Nyquist ban is shown in Fiure The ual-tone SFDR is 68.1Bc with the HD2 bein the hihest spurious component. The spectrum of the reuce banwith is shown in Fiure 12.7, where the ual-tone SFDR RB in a 300MHz RB banwith, excluin the IMD tones, is 87.1Bc. Further zoomin in, the spectrum aroun the sinal tones in Fiure 12.8 shows that the worst case IMD is the IMD3 at -86.8Bc. The increase of the noise towar the two sinal tones is ue to phase noise of the spectrum analyzer. A sweep over the input frequency shows that the performance is best at low frequencies an worsens for hiher frequencies. The results of the inputfrequency sweep is shown in Fiure For these simulations, a ual-tone input sinal is use. The results for the IMD is as expecte by simulations. At low frequencies, the IMD is constant an is limite by the matchin of the current sources. For hiher frequencies, timin errors limit the performance, which results in a erain IMD for increasin frequency. The harmonic istortion stronly epens on the input frequency. The increase for the near-nyquist frequency suests that the error-source is in the baseban part of the converter. Measurements in the mix moe etermine if that is the case, or if the error-source is output-frequency epenent, see Section an Section

157 12.3. Baseban performance 143 Fiure 12.6: Spectrum of the full Nyquist ban for a ual-tone input sinal in baseban moe (no mixin) Fiure 12.7: Spectrum of the 300MHz RB for a ual-tone input sinal in baseban moe (no mixin) The SFDR is mostly limite by the HD2. Only for frequencies below 100MHz other spurs limit the SFDR. The SFDR RB for frequencies below RB/2 (=150MHz) are limite by the HD components. For hiher frequencies, the eraation for increasin frequencies suest that timin errors cause these spurious components. The total current consumption is approximately 620mA from the 1.2V power supply an 130mA from the 3.3V power supply. Hence, the total power

158 144 Chapter 12. Experimental results Fiure 12.8: Spectrum of the ual-tone output sinal in baseban moe (no mixin) IMD HD2 HD3 an HD4 SFDR RB SFDR Nyquist 75 [Bc] Frequency [MHz] Fiure 12.9: Dual-tone output spectrum in baseban moe (no mixin), F S =1.5GHz, ual-tone SFDR&HD consumption of the test chip is approximately 1.2W. This inclues two Mixin- DAC cores an the iital sinal processin. The power consumption of the analo circuitry is 710mW with two Mixin-DAC cores enable an 380mW with only one Mixin-DAC core enable. Since all circuitry in the Mixin- DAC cores is implemente with CML circuits, the current consumption is frequency inepenent. The same circuits are enable for the baseban moe

159 12.4. Mixin ynamic performance 145 an the mix moe, hence the power consumption in the mix moe is ientical to the power consumption in baseban moe. An overview of the power consumption is iven in Table Table 12.1: Power consumption of the ual-mixin-dac test chip Part 1.2V 3.3V Power Diital circuits 415mA 0mA 498mW Mixin-DAC cores 2x80mA 2x70mA 2x327mW Auxiliary analo circuits 43mA 0mA 52mW Total 1.2W 12.4 Mixin ynamic performance When the mixer is enable, the iital baseban sinal is upconverte to the LO frequency. The spectrum of the output for F S =1.5GSps, f LO =3GHz an a sinle-tone input sinal at f in =155MHz is shown in Fiure These results coincie with the simulation results of Fiure 11.22, althouh with ifferent frequencies. Hence the test chip implements the function of a Mixin- DAC. However, there are number of small ifferences in the spectra. The LO leakae in the measurements is hiher than the simulation results. This can be ue to couplin in the measurement setup or couplin on-chip at a level which is not extracte for capacitive couplin. The output power is lower than the simulate value, which is further iscusse in Section Measurements at RF frequencies are sensitive to external isturbances, see Section The output power is iscusse in Section Optimization of the Mixin-DAC settins an measurement setup results in improve performance, see Section an Section respectively. The resultin performance is iscusse in Section External isturbances When measurin at RF frequencies, sinals from RF transmitters couple to the measurement setup an can cause spurious sinals in the measure sinal. For example, when measurin aroun 1.85GHz, GSM transmitters close to that frequency irectly couple to the measure output voltae. Fiure shows a measurement at 1.845GHz, with external isturbances at 1.855GHz an 1.875GHz.

160 146 Chapter 12. Experimental results flo fout,l=flo-fin f out,h =f LO +f in 2 flo flo+fs 2 flo+fs Fiure 12.10: Output spectrum in mix-moe Fiure 12.11: External interference ue to GSM transmitter Due to these external isturbances, a Faraay cae is use for the measurements at frequencies where other transmitters are active. Aroun 1.5GHz, no stron transmitters are active. Therefore, some of the measurements are execute aroun this frequency.

161 12.4. Mixin ynamic performance Output power The output power of the measure Mixin-DAC is lower than the simulate values. The epenence of the measure output power on the output frequency is shown in Fiure for output frequencies of 0.3GHz to 5.8GHz. The value of the Mixin-DAC sample rate is limite. Therefore, to enerate a wie-ban sinal at this wie rane of output frequencies, multiple ratios between the sample rate F S an the LO frequency f LO are use: f LO = r F S, where r {0.5,1,2,3,4}. In other wors, Fiure combines measurements with multiple ratios, as inicate at the top of the fiure. For each reion with a fixe r, the LO frequency is swept to enerate multiple output frequencies, which consequently also sweeps the sample rate. The input frequency is fixe at f in =155MHz. The measure power is shown as P meas. Both the output power of the low Nyquist ban (at f LO -f in ) an the hih Nyquist ban (at f LO +f in ) are shown, i.e. P meas Low an P meas Hih respectively. [Bm] f LO =½F S f LO =F S f LO =2 F S f LO =3 F S f LO =4 F S P meas Low P meas Hih P comp Low P comp Hih P calc Low P calc Hih Output frequency [GHz] Fiure 12.12: Depenence of the output power on the output frequency Between the output of the Mixin-DAC an the spectrum analyzer, a number of components cause losses: capacitance of the tracks on the measurement boar, transformers on the measurement boar an the cable between the measurement boar an the spectrum analyzer. The loss of these components is measure usin a network analyzer. In Fiure 12.12, the compensate output power is shown as P comp for both the low an hih Nyquist ban.

162 148 Chapter 12. Experimental results TheexpecteoutputpowerisshowninFiure12.12asP calc. Theexpecte output power is calculate usin the known output current (20mA), the 50Ω ifferential effective loa resistance, an estimate loa capacitance of 1.5pF an the response of the zero-orer-hol an mixin. Due to the zero-orerhol transfer characteristic of the DAC an mixin function, a sinc-shape frequency-response is present in the expecte output power. The relative frequency-response ue to this sync-shape also causes the sinal power in the Low an Hih Nyquist bans to be ifferent. This effect is shown in Fiure 12.13, where the frequency-response of the zero-orer-hol an mixin function is shown for various ratios between F S an f LO. The asymmetry of the response is ue to the mixin operation bein a mixin operation with f LO an -f LO. Multiplyin the sinc-shape of the DAC zero orer hol with f LO an -f LO results in the asymmetric response. 0 5 Baseban f LO =F S f LO =2 F S f LO =3 F S 10 f LO =4 F S Response [B] f out /F S Fiure 12.13: Mixin-DAC response ue to zero-orer-hol function The compensate output power is close to the calculate output power for low frequencies an aroun 4 GHz. The ifference at other frequencies is expecte to be cause by frequency-epenent reflections on the PCB an in the measurement setup ue to imperfect impeance matchin. The output power can be improve in a reesin of the Mixin-DAC, where extra attention ispaitotheoutputimpeance. Anoptionforareesinistopositionsomeof the termination resistances on-chip, thereby eliminatin some of the neative effects of the bonwires.

163 12.4. Mixin ynamic performance Biasin optimization The performance of the Mixin-DAC epens on the settins of the bias currents an voltaes. The biasin settin which are optimize, are: LO river tail current I LO Data river tail current I ata LO river supply voltae V lohih Elevate bulk voltae V bulkhih Mixer blee current I blee,mix Output-cascoe blee current I blee,oc MainoptimizationtaretsareIMD,SFDR RB ansfdr.optimizinforthese ifferent optimization tarets often results in ifferent optimal bias settins. For instance, for a oo IMD, the I ata shoul remain at the nominal value, while the SFDR improves when I ata is ecrease. The final biasin value is a trae-off between the optimal IMD, SFDR RB an SFDR Clock - LO phase optimization The phase between the DAC sample clock an the LO sinal influences the spectral purity. Fiure shows a simulation result for chanin the phase of the LO sinal at f LO =4GHz, F S =2GSps an f in =155MHz. In these simulations, the HD3 limits the SFDR. It can be seen that both the IMD3 an the ual-tone SFDR can vary 10B epenin on the phase. There is a repetition with 180 since the alinment of transitions is eterminin the performance, an the actual irection of the transition is less important ue to the ifferential structure of the Mixin-DAC. The phases for the optimal IMD3 of the hih Nyquist ban an the low Nyquist ban are 90 apart. Also the phases of the optimal SFDR in both Nyquist bans are 90 apart. The phases for the optimal SFDR an IMD3 in the hih Nyquist ban coincie. However, the phases for the optimal SFDR an IMD are in anti phase for the low Nyquist ban. The measure performance also shows a epenence on the phase between the clock an LO sinal. The epenence of the IMD an the HD on the clock-lo phase for f LO =1.5GHz F S =1.5GSps an f in =155MHz is shown in Fiure The repetition with 180 is also present in these measurements. The main ifference between the simulation results an these measurement results is that the phases of the optimal IMD an HD in the low Nyuist ban are ientical in the measurements, while they are in anti-phase in the simulations. The causes for this ifference are unknown.

164 150 Chapter 12. Experimental results 95 IMD3 Hih IMD3 Low SFDR Hih SFDR Low 90 [Bc] Clk LO phase [ ] Fiure 12.14: Simulate epenence of the spectral purity on the phase between the clock an the LO sinal [Bc] IMD Hih IMD Low HD Hih HD Low Clk LO phase [ ] Fiure 12.15: Measure epenence of the spectral purity on the phase between the clock an the LO sinal

165 12.4. Mixin ynamic performance 151 These measurements clearly show a stron epenence of the performance on the clock-lo phase. However, ue to the ifferent phase behavior of the equipment, cables, PCB tracks an transformers, externally controllin this phase is challenin. Therefore, in a reesin of the chip, an on-chip synchronization metho woul improve the stability of the measurement results. Since the frequencies of the sample clock an the LO sinal have a well-efine ratio, an on-chip frequency ivier or PLL is also an option worth investiatin Dynamic performance The linearity of the Mixin-DAC is assesse usin sinusoial sinals. This section iscusses the linearity at the typical confiuration an for various values of the input frequency, sample rate an LO frequency Typical frequency There are numerous wireless stanars which use frequencies aroun 1.9GHz, e.. GSM, 3G, 4G. Therefore, the linearity of the Mixin-DAC aroun that frequency is important. For an output frequency of 1.905GHz, the Mixin-DAC uses f LO =1.75GHz, F S =1.75GSps an f in =155MHz. The output in the hih Nyquist ban is use. The spectrum of the full Nyquist ban is shown in Fiure 12.16, where the input sinal is a sinle-tone sinal. The power of the sinle-tone sinal is -14.9Bm at the input of the spectrum analyzer. Correctin for the losses of the measurement setup, the sinal power is calculate to be -8.0Bm at the output of the Mixin-DAC. The SFDR is 66.3Bc, limite by the HD2 component. The HD2 is expecte to be cause by imperfect symmetry of the mixer layout in the output stae. The secon larest spurious component is the HD3 at -69.7Bc. The spectrum of the RB of 300MHz is shown in Fiure 12.17, where the input sinal is a sinle-tone sinal. Since the HD2 component falls outsie this RB, the SFDR RB value of 75.1Bc is much better than the SFDR value. The SFDR RB is limite by a spurious component at f LO +F S /8-f in = MHz. Some of the iital circuits operate at F S /8. Its isturbance on the power supply couples via the ESD circuits to the LO input, which causes this mixinprouct, seesection11.6. Otherspuriouscomponentsare: f LO +F S /4- f in =2032.5MHz (-78Bc), an HD12 at 1860MHz (-80Bc). When omittin the spurious components associate with the iital sinal processin, the SFDR RB is 80Bc. The spectrum of a two-tone sinal is shown in Fiure The IMD5 is

166 152 Chapter 12. Experimental results Fiure 12.16: Spectrum of the full Nyquist ban at f LO =1.75GHz, F S =1.75GSps an a sinle-tone sinal at f in =155MHz Fiure 12.17: Spectrum of the 300MHz RB at f LO =1.75GHz, F S =1.75GSps an a sinle-tone sinal at f in =155MHz the most ominant o-orer IMD at -83.9Bc. The ominance of the IMD5 over IMD3 suests that mismatch errors cause these non-linear istortion. Also the relatively hih HD12 in the SFDR RB with respect to the simulation implies the ominance of mismatch errors. This is further iscusse in

167 12.4. Mixin ynamic performance 153 Section The thermal noise power is -168Bm/Hz at 10MHz from the output frequency. Fiure 12.18: Spectrum aroun the output sinal at f LO =1.75GHz, F S =1.75GSps an a ual-tone sinal aroun f in =155MHz Input frequency epenence Measurin at various input frequency values shows which part of the Mixin-DAC is limitin the performance. The measurement results for F S =1.5GSps an f LO =1.5GHz are shown in Fiure For low f in values, the IMD is below -80Bc, the HD3 an HD4 are below -75Bc. For increasin f in, the HD values erae. This applies to both the hih an low Nyquist ban. Hence, the cause of the HD is in the baseban part of the Mixin-DAC, e.. the Data switches or the capacitance at the rain of the Data switches. The IMD for f in <150MHz epens more on the output frequency than on the f in value. Hence, the cause for this non-linear istortion is in the RF part of the Mixin-DAC, e.. the mismatch of the mixer switches or the parasitic capacitance at the source of the output cascoe. For the exemplary application of multicarrier GSM, the linearity at f LO =1.5GHz is near the taret -85Bc. However, to maintain this linearity, the input frequency shoul be limite to approximately 150MHz. These results clearly show that the propose architecture achieves hih linearity in a lare banwith.

168 154 Chapter 12. Experimental results IMD HD2 HD3 an HD4 SFDR RB SFDR Nyquist [Bc] f LO f out [GHz] f in [MHz] Fiure 12.19: Sweep over the input frequency in mix moe, F S =1.5GSps, f LO =1.5GHz Output frequency epenence The flexibility of the Mixin-DAC architecture enables the eneration of an RF output sinal from baseban to multi-ghz frequencies. To emonstrate this capability, Fiure shows the performance for output frequencies of GHz. To cover this rane, the ratio between F S an f LO shoul be between 1 an 4. The F S is between 1.1GSps an 1.75GSps while the f LO is GHz. The input frequency is always 155MHz. For each value of f LO, the confiuration of the ata river bias current an the LO river bias current are altere in a rane of 6% an 12% respectively for the best performance. For each ata point, also the clock-lo phase is optimize. The IMD an the SFDR RB oes not stronly epen on the output frequency for frequencies below 1.9GHz an 1.7GHz respectively. Hence, the error sources in the baseban part of the Mixin-DAC limit the linearity. For hiher frequencies, the IMD an SFDR RB epen on the output frequency. For these frequencies, the non-linearity is cause by error sources in the RF partofthemixin-dac.thesfdrisalmostconstantforf out <4GHz, limite by the HD2, HD3 or HD4. These HD components are cause by effects in the baseban part of the Mixin-DAC. Above 4 GHz, both the HD spurs an the SFDR worsen, limite by error sources in the RF part of the converter. The peak in the HD2 value aroun 3.2GHz suests that there are two HD2-

169 12.4. Mixin ynamic performance 155 f LO =1 F S f LO =2 F S f LO =3 F S IMD HD2 HD3 an HD4 SFDR RB SFDR Nyquist [Bc] Frequency [GHz] Fiure 12.20: Sweep over the output frequency, F S = GSps, f LO = GHz, f in =155MHz eneratin effects, which can cancel one another. To analyze which error-source causes the IMD to erae for frequencies above 1.9GHz, a ither sinal is ae to the input ata. A ither sinal is a ranom sinal, which has no correlation with the esire input sinal. The oal of ain a ither sinal is to ranomize which current cells are use for a specific value of the esire ual-tone input sinal. When there are cell-epenent error sources which cause non-linear istortion, the istortion is converte to noise. The amplitue of the ual-tone input sinal is ecrease by 6B to allow for the ither sinal with a total amplitue of -6B FS. The resultin IMD is shown in Fiure For a iscussion on the relationship between the input-sinal power an the linearity, see Chapter 9 an Section These measurement results show that the IMD can be better than -80Bc for frequencies between 1.9GHz an 3.5GHz when usin ither. Note that the input sinal effectively experiences a 15 bit converter ue to the amplitue reuction of 6B of the input sinal. The IMD performance up to 3.0GHz is inepenent of the output frequency. From 2.5GHz up to the maximum measure frequency of 5.3Ghz, the ither IMD is more than 10B better than the IMD without ither. These measurement results clearly emonstrate that the most ominant error source above 1.9GHz is a cell-epenent error source. Examples of this type of error source are: timin errors in the mixer;

170 156 Chapter 12. Experimental results Without ither With ither 85 IMD [Bc] Output frequency [GHz] Fiure 12.21: IMD with an without ither for various output frequencies timin errors in the LO istribution tree; timin errors in the output recombination tree. It is unknown which of these error sources is the most ominant. These errorsources can be ue to imperfect esin or ue to process variations. For errors ue to imperfect esin, e.. timin errors in the istribution tree, a reesin can enable a solution. For errors ue to process variation, e.. timin errors ue to mixer mismatch, a calibration metho can be use to measure an correct the timin errors of the mixer. However, this requires the measurement accuracy of the timin-error measurement circuit to be in the orer of 55fs, see Section 6.5. An exemplary applicable calibration metho is the sort-ancombine calibration alreay present in the Mixin-DAC implementation. For the exemplary application of multicarrier GSM, the IMD value is near the require -85Bc for output-frequency values up to 1.9GHz. However, if the cell-epenent error-source woul be compensate, the IMD performance up to approximately 3.5GHz is satisfactory. The hih IMD up to almost 4GHz closely matches the simulation results. The cell-epenent error-sources can be compensate by ain a ither sinal to the input ata or in a new implementation, e.. by timin-error calibration of the RF part of the Mixin-DAC. However, measurements show that the absolute value of the Noise Spectral Density (NSD) (in Bm/Hz) eraes with rouhly 6B when ain ither. This aitional noise is cause by the HD an IMD components which have been ranomize an appear as noise.

171 12.4. Mixin ynamic performance 157 The measure thermal NSD (without ither) for various output-frequency values is shown in Fiure For these measurements, an LNA is use between the output of the measurement boar an the spectrum analyzer to reuce the impact of the spectrum-analyzer noise. Due to the low noise power an the lare attenuation of the measurement setup, the noise of the measurement setup limits the measure noise above f out =1.7GHz. The NSD up to 1.7GHz is -157B FS /Hz an it is expecte that the NSD of the Mixin- DAC is ientical for all other output frequency values. This NSD value is close to the require -162B FS /Hz for the exemplary application of multicarrier GSM. 130 NSD limite by measurement setup ue to sinal a enua on NSD [Bm] [B FS ] Output frequency [GHz] Fiure 12.22: Thermal noise spectral ensity for various outputfrequency values Input-power epenence Since multicarrier transmitters typically operate in back-off, the performance with a reuce input-sinal power is important (see Chapter 9). There are two types of responses of the non-linearity to the value of the inputsinal power. Decreasin the input-sinal power improves the IMD if the ominant istortion is cause by a non-linear element, such as for instance a sinle transistor. The IMD eraes for ecreasin input-sinal power if the istortion is cause by cell-epenent effects. The spectral purity for various values of the input-sinal power is shown in Fiure In this measurement, F S =1.5GSps, f LO =1.5GHz, f in= 155MHz

172 158 Chapter 12. Experimental results an the hih Nyquist ban is use. A lower input power means that less unary current cells are use, that the effective sementation chanes to less unary bits, an that the relative importance of the cell-epenent error sources increases. At f LO =1.5GHz, the IMD an SFDR RB almost linearly epen on the input power, hence the ominant error source at this frequency is cell-epenent, as sueste in the previous section. The error-source which enerates the HD is not the most ominant error-source at f LO =1.5GHz. However, the eraation of the HD above 10B FS back-off shows that there are cell-epenent error sources which can influence the HD at the riht conitions. This coincies with the conclusions in the previous section, where the HD eraes for hih output frequency values, an with the iscussion of the sementation in Chapter IMD HD2 HD3 an HD4 SFDR RB [Bc] Backoff [B ] FS Fiure 12.23: Dynamic performance for various values of the iital input power (F S =1.5GSps, f LO =1.5GHz, f in= 155MHz, hih Nyquist ban) Temperature epenence The measurement boar incluin the ata eneration boar was place in an controlle-temperature environment to evaluate the performance over temperature. The results of an ambient temperature sweep from -35 C to 125 C are shown in Fiure In this measurement, F S =1.5GSps, f LO =1.5GHz, f in= 155MHz an the hih Nyquist ban is use. There are no IMD results for temperatures above 95 C because the ataeneration boar faile to operate above these frequencies. However, because

173 12.4. Mixin ynamic performance IMD HD2 HD3 an HD4 SFDR RB SFDR Nyquist [Bc] Temperature [ C] Fiure 12.24: Dynamic performance for various values of the temperature (F S =1.5GSps, f LO =1.5GHz, f in= 155MHz, hih Nyquist ban) the Mixin-DAC chip can inepenently enerate sinle-tone sinals, there are HD an SFDR results for the complete temperature rane. The IMD eraation above 40 C is ue to the IMD3; the other IMD components slihtly improve from -83Bc at -35 C to -88Bc at 80 C. The cause of the IMD other than the IMD3 is mismatch inuce timin errors. Mismatch becomes smaller for hiher temperatures, hence timin errors are smaller for hiher temperature improvin the IMD. The cause of the IMD3 eraation is expecte to be transistors in the output stae of the Mixin- DAC leavin their saturation reion. When the LO hih voltae (V lohih ) an the Data river bias current are slihtly increase, the IMD3 at 95 C improves from -74Bc to beyon -90Bc. The SFDR RB is expecte to also suffer from this transistor not bein in saturation. The shape of the HD2 curve suest that there are two HD2 effects which cancel one another, which is also observe in Section The other HD components only weakly epen on the temperature. The power consumption is almost inepenent of the temperature. The total current consumption varies less than 4% for the temperature rane of -35 C to 80 C.

174 160 Chapter 12. Experimental results Multiple samples For analyzin the robustness of the Mixin-DAC performance, 15 samples are measure. All measurements use ientical clock-lo phase an ientical biasinconfiuration. The historam of the IMD an the SFDR RB is shown in Fiure In this measurement, F S =1.5GSps, f LO =1.5GHz, f in= 155MHz an the hih Nyquist ban is use IMD SFDR RB # occurrences [%] [Bc] Fiure 12.25: Historam of IMD an SFDR RB for 15 samples with ientical confiuration (F S =1.5GSps, f LO =1.5GHz, f in= 155MHz, hih Nyquist ban) The performance of the elaborately iscusse sample (#5) is: IMD=-82Bc an SFDR RB =82Bc. The meian of the 15 samples are IMD=-75Bc an SFDR RB =81Bc. Sample #5 has an averae SFDR RB, but it is the best sample with respect to its IMD. A possible cause of this sinle oo IMD for sample #5 is that the clock-lo phase an the biasin confiuration is optimize for this specific sample. However, when applyin the same optimization metho to another sample (#12), the IMD3 only improves slihtly, from -74Bc to -76Bc, which is worse than the oriinal sample #5. But the IMD5, HD2, HD3 an HD4 of sample #12 are similar or better than sample #5. Timin errors ue to mismatch o not cause this worse IMD3 because then also the IMD5 woul be worse, which is not the case. However, the etermination of the reason for the worse IMD3 requires further investiation. The historam of the LO leakae is shown in Fiure It can be observe that the chips have two iscrete values of the LO leakae: -22Bm

175 12.5. Raio sinals 161 or aroun -51Bm. There is a lare correlation between the LO leakae value an the value of the HD2 an HD4 in each sample. Hence, one of the causes for the LO leakae is an unbalance in the ifferential sinals. The other cause for a hih LO leakae is expecte to be the calibration alorithm. The Mixin-DAC contains a number of reunant current cells such that the calibration alorithm can select the current cells with the best behavior, as iscusse in Section 11.2 an Section The floorplan of the output stae incorporates inversely polarization of half of the current cells, as iscusse in Section This inversion of the polarization is one by connectin the LO tree with inverse polarity to the mixer in the mirrore current cells. When the calibration alorithm selects an equal number of inversely polarize an straiht current cells, the LO leakae of those two types of current cells cancel one another. This results in a low LO leakae. When the number of the two types of current cells are not equal, the LO leakae is not cancele an a hih LO leakae is observe. # occurrences [%] P LO [Bm] Fiure 12.26: Historam of LO leakae for 15 samples with ientical confiuration (F S =1.5GSps, f LO =1.5GHz, f in= 155MHz, hih Nyquist ban) 12.5 Raio sinals The measurement of real raio sinals shows the usability of the Mixin- DAC for transmitters. GSM sinals have a relatively small banwith, but require a hih spectral purity. WCDMA an LTE are stanars which require

176 162 Chapter 12. Experimental results more sinal banwith, especially in a multicarrier setup. However, the require spectral purity is lower than that of GSM. For all raio stanars, the require spurious-component free banwith is lare. The typical full-scale output current of the Mixin-DAC is 20mA, but it is prorammable up to 51mA. For the sinle-carrier raio sinals, the noise of the Mixin-DAC an the measurement setup limits the performance. Therefore, confiurin the Mixin-DAC for a hiher output power at the expense of linearity results in a better ACLR (Ajacent Channel Leakae Ratio). For multi-carrier raio sinals, intermoulation proucts can limit the ACLR an hence the linearity is more important Multicarrier intermoulation To emonstrate the excellent intermoulation performance of the Mixin- DAC, a 13-tone sinal is measure at 2.0GHz output. The measure spectrum is shown in Fiure The reason for the low level of the intermoulation spurs is ue to the 13 tones actin as a sort of itherin sinal for the other tones, thereby spreain the enery of the istortion spurs (see Section ). In this fiure, there is a spur at f LO +F S /8 (=1.97GHz) present, which is maske by one of the sinal tones. Since the clock-relate spurs are not cause by an error in the Mixin-DAC core but are cause by the iital circuits, these clock-relate spurs are not relevant. The SFDR RBi n a 300MHz banwith, excluin the clock spur, is 81Bc. This shows that the linearity of the Mixin-DAC is sufficient to accommoate multicarrier sinals without bein limite by intermoulation of the carriers GSM A sinle-carrier GSM sinal is shown in Fiure 12.28, toether with a part of the GSM spectral mask. Fiure shows the same GSM sinal with the remainin part of the GSM mask. The valiation of conformance to the GSM mask is split in these two parts since the spectrum analyzer can only hanle a limite number of ifferent levels in the spectral mask. These measurements use an LNA to lower the impact of the spectrum-analyzer noise. The GSM sinal satisfies the spectral mask up to ±20MHz from the carrier. This valiates the excellent phase noise an thermal noise, which are sufficiently low to satisfy the sinle-carrier GSM requirements. At more than 20MHz from the carrier, various spurious components violate the spectral mask. However, most of these spurs are also present when the Mixin-DAC is ile, an hence are expecte to be external isturbances couplin to the measurement setup.

177 12.5. Raio sinals Bc 300 MHz Fiure 12.27: 13-tone output sinal emonstrates low intermoulation (f LO =1.75GHz, F S =1.75GSps, an a 13-tone sinal aroun f in =250MHz, hih Nyquist ban) Fiure 12.28: GSM sinal at 1.625GHz an GSM mask close to thesinal(f S =1.5GSps, f LO =1.5GHz, f in= 125MHz, hihnyquist ban) The equivalent NSD at 20MHz from the GSM carrier in Fiure is calculate to be -141B FS. This oes not correspon with the measure NSD of -157B FS of Section Possible reasons for this ifference are in the spectrum analyzer. The attenuation of the spectrum analyzer is 14B to prevent non-linear istortion of the spectrum analyzer to limit the GSM measurement. This increases the relative weiht of the noise of the spectrum

178 164 Chapter 12. Experimental results Fiure 12.29: GSM sinal at 1.625GHz an GSM mask far away from the sinal (F S =1.5GSps, f LO =1.5GHz, f in= 125MHz, hih Nyquist ban) analyzer. Furthermore, the settins of the spectrum analyzer when measurin the GSM sinal are optimize for ynamic rane an linearity an not for low noise. Finally, the phase noise of the spectrum analyzer is -145Bc at 10MHz, which is close to the calculate -141B FS noise floor. A 3-carrier GSM sinal is shown in Fiure Since the noise floor is much hiher than expecte from the earlier measure NSD of Section , the noise violates the spectral mask. At the frequencies of the IMD3 of the GSM carriers, sliht increase in noise can be observe ue to the limite IMD3 of the Mixin-DAC ACLR of WCDMA an LTE The measurement of the ACLR of WCDMA an LTE sinals is limite by the noise of the measurement setup. Therefore, for most ACLR measurements the output current is increase typically to 38mA. This improves the ratio between the output-sinal power an the noise floor, thereby increasin the ACLR. Althouh increasin the output current reuces the linearity, it usually oes not erae the ACLR since the ACLR is limite by noise an not by non-linearity. The spectrum of a 1-channel LTE sinal is shown in Fiure The peak-to-averae ratio of the LTE sinal is 11B. Therefore the output power is 11B lower than the maximum sinle-tone output power to prevent clippin. The measure ACLR is -69Bc for f out =2GHz. Since the output power increases for lower frequencies, the ACLR for lower frequencies is better.

179 12.5. Raio sinals 165 Fiure 12.30: Multicarrier GSM sinal at 1.805GHz to 1.824GHz (F S =1.0GSps, f LO =2.0GHz, f in= MHz, low Nyquist ban) Fiure 12.31: Sinle-channel ACLR of a LTE sinal at 2.0GHz (F S =1.75GSps, f LO =1.75GHz, f in =250MHz, hih Nyquist ban) A 4-channel LTE sinal is shown in Fiure Since the carriers a up in amplitue, the output power is 12B lower than the power of the 1- channel sinal. To maximize the sinal to noise ratio, an LNA is use in the measurement setup to amplify the input sinal of the spectrum analyzer. Since the ACLR is limite by the noise, the 4-channel ACLR of -58Bc is approximately 12B lower than the 1-channel LTE sinal. TheLTEACLRat4.1GHzis-73Bc, seefiure ThisACLRsimilar

180 166 Chapter 12. Experimental results to the ACLR at 2GHz since the output power at 4GHz is similar to the 2GHz output power, see Section Fiure 12.32: 4-channel ACLR of a LTE sinal at 2.0GHz, measure with LNA (F S =1.75GSps, f LO =1.75GHz, f in =250MHz, hih Nyquist ban) Fiure 12.33: Sinle-channel ACLR of a LTE sinal at 4.1GHz (F S =0.983GSps, f LO =3.932GHz, f in =155MHz, hih Nyquist ban) The ACLR epenence on the input frequency is shown in Fiure By choosin a hih f in, the istance of the output frequency to the LO leakae