Embedded Systems and Software. Analog to Digital Conversion

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1 Embedded Systems and Software Analog to Digital Conversion Slide 1

Successive Approximation (SAR) conversion Single-Slope conversion Dual-Slope

2 Analog to Digital Conversion Analog or continuous signal Discrete-time or digital signal Other terms ADC, A/D Many different techniques Flash conversion Successive Approximation (SAR) conversion Single-Slope conversion Dual-Slope conversion Delta encoding conversion Sigma Delta conversion Image from Wikipedia Slide 2

Somewhat ironically, DACs a key sub-circuit in in some ADCs VV OOOOOO = 0 1 2 1 1 4 1 1 8

3 Digital to Analog Converter (DACs) Digital-to-Analog Converters are inherently simpler to construct. Somewhat ironically, DACs a key sub-circuit in in some ADCs VV OOOOOO = = VV OOOOOO = = VV OOOOOO = = Simple 4-bit DAC VV OOOOOO = RR RR (BB 3) RR 2RR BB 2 BB XX = 0 or 1 RR 4RR BB 1 RR 8RR BB 3 Slide 3

4 Flash Converters Brute-force approach Fastest ADC available Expensive Power Hungry Limited to 8/10 bits Slide 4

5 Successive Approximation (SAR) Slide 5

6 Sigma Delta Slide 6

7 Comparison of ADC Types Sigma Delta SAR Flash Bits of Resolution Sigma Delta SAR Flash K 10K 100K 1M 10M 100M Maximum Conversion (Hz) Slide 7

8 Bits of Resolution Slide 8

9 ADC on ATmega88 The ADC on the ATmega88 is multiplexed to up to 6 inputs The analog power supply must be clean and within ±0.3V of VCC Slide 9

10 Using the ADC Use either ADC5 or ADC4 (ADC5) (ADC4) Suggested pin assignment for ADC/LCD lab Slide 10

11 The ADC sub system has many components Slide 11

12 10- or 8-bit conversion engine Slide 12

13 The analog power supply must be clean to ensure accurate conversions Slide 13

14 An internal reference of 1.1 V is available Slide 14

15 Or one can supply an external reference voltage Slide 15

16 The multiplexer logic selects one of 6 (28-pin packages) or one of 8 (SMT packages) Slide 16

17 The ADMUX register determines which ADC input is routed to the ADC Slide 17

18 The 10-bit conversion result goes into two registers, namely ADCH and ADCL Slide 18

19 These bits determines the conversion clock frequency Slide 19

20 If desired, one can have the ADC generate an interrupt when it is done with a conversion Slide 20

21 Control bits ADEN enables ADC ADSC starts a conversion Slide 21

22 The ADCSRA Register The ADC control and status register A (ADCSRA) configures the ADC In single-conversion mode, writing 1 here starts a conversion Set when a conversion has completed Determines the conversion clock Writing 1 here turns the ADC ON Enables auto triggering Enables Conversion Complete interrupt Slide 22

The ADMUX Register The ADMUX determines what external

Selects voltage reference 1 Left Adjust 0 Right Adjust

23 The ADMUX Register The ADMUX determines what external pin is routed to the conversion engine. It also selects the ADC voltage reference and left/right adjustment of the conversion result. Selects voltage reference 1 Left Adjust 0 Right Adjust Selects which analog input is connected to ADC 0b0000 ADC0 0b0101 ADC5 (i.e., PC5) Slide 23

24 The ADCSRB Register The ADC control and status register B (ADCSRB) configures what triggers a conversion Used by Analog Comparator (not ADC) Determines what triggers an ADC conversion Slide 24

25 ADC Conversion Clock The ADC uses an Successive Approximation (SAR) technique and the conversion clock affects the accuracy. The ATmega88 documentation states that for maximum accuracy, the ADC conversion clock frequency must lie between 50 khz and 200 khz. If only 8-bit accuracy is required, the ADC conversion clock frequency can be higher. The ADC has several modes: single conversion, triggered conversion, free-running conversion. Depending on the mode, conversion time is between 13 and 25 ADC clock cycles. Slide 25

26 ADC Conversion Clock Question What is the highest 10-bit sample rate on an Atmega88 with a 10-MHz clock Answer The system clock is not relevant (assuming it is high enough). The highest ADC clock for 10-bit conversion is 200 khz. An ADC clock cycles is 1 200,000 = 50 μμs. Assuming the ADC conversion mode is such that it takes 13 clock for a conversion, it means the ADC can make a conversion so faster than once every 65 μμs. This means the maximum sample rate is 1 5 μμs = 15.4 khz. In practice the sample rate will be lower because there is overhead grabbing and processing the conversion results. Slide 26

27 ADC Timing - Single Conversion Mode ADC Clock ADCEN ADSC ADCH ADCL The first conversion takes 25 ADC clock cycles Note - clock here refers to the ADC clock Slide 27

28 ADC Timing - Single Conversion Mode ADC Clock ADCEN ADSC ADCH ADCL Subsequent conversions take 13 clock cycles Note - clock here refers to the ADC clock Slide 28

29 ADC Timing Auto Triggered Conversion Mode ADC Clock Tigger ADATE ADCH ADCL Subsequent conversions take 13 clock cycles Note - clock here refers to the ADC clock Slide 29

30 ADC Timing Free Running Conversion Mode ADC Clock ADSC ADCH ADCL Conversions take 3 clock cycles Note - clock here refers to the ADC clock Slide 30

31 Conversion Times Slide 31

The ADC Conversion Result The ADC conversion result is a 10-bit number and is related to VV IIII (the analog input voltage) and VV RRRRRR (the selected reference voltage) as follows AAAAAA = VV IIII

32 The ADC Conversion Result The ADC conversion result is a 10-bit number and is related to VV IIII (the analog input voltage) and VV RRRRRR (the selected reference voltage) as follows AAAAAA = VV IIII 1024 VV RRRRRR 0x000 Represents analog ground and 0x3FF ( = 1023 decimal) represents VV RRRRRR minus 1 LSB The ATmega88P is an 8-bit controller while two bytes are required to hold a 10-bit conversion. There are two registers, namely ADCH and ADCL where the results are stored Slide 32

33 The ADC Conversion Result The result of the conversion is stored in two registers, namely ADCH ( high or most significant bits) and ADCL ( low or least significant bits) The result can be left-adjusted or right-adjusted, depending on the ADLAR bit in the ADMUX register. Consider the 10-bit decimal number 0x2B9 = 0b Left-Adjusted x x x x x x ADCH ADCL Right-Adjusted x x x x x x ADCH ADCL Slide 33

34 Left/Right Adjust The ADLAR bit in ADMUX the left/right adjustment of the conversion result. 1 Left Adjust 0 Right Adjust 10-bit conversion result with ADLAR = 0 10-bit conversion result with ADLAR = 1 Slide 34

35 The ADC Conversion Result Question The ADC used a 5-V reference and performs a 10-bit conversion on a 4.8 V input voltage. What are the contents of the ADCH and ADCL register assuming the conversion result is (a) left adjusted, and (b) right adjusted? Answer Slide 35

36 Correctly Reading the ADC Result It is important to read the ADC conversion registers in the proper order From the ATmega88P documentation: When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. Slide 36

Configuration Example 1 // ADC Clock frequency: 250.

37 Configuration Example 1 // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Free Running The bits below set up the ADC to behave like this #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)); ADMUX = ADC_VREF_TYPE; ADCSRA = (1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); unsigned int read_adc(unsigned char adc_input) { ADMUX = adc_input ADC_VREF_TYPE; delay_us(10); // For stabilization of ADC input voltage } ADCSRA =(1<<ADSC); // Start the AD conversion while((adcsra&(1<<adif))==0) // Wait for AD conversion to complete ; ADCSRA =(1<<ADIF); return ADCW; Slide 37

38 Configuration Example 1 // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Free Running #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)); ADMUX = ADC_VREF_TYPE; ADCSRA = (1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); Check with the documentation and convince yourself that these settings match the comments above unsigned int read_adc(unsigned char adc_input) { ADMUX = adc_input ADC_VREF_TYPE; delay_us(10); // For stabilization of ADC input voltage } ADCSRA =(1<<ADSC); // Start the AD conversion while((adcsra&(1<<adif))==0) // Wait for AD conversion to complete ; ADCSRA =(1<<ADIF); return ADCW; Slide 38

The adc_input variable selects the ADC input pin.

(1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); 0b0101

39 Configuration Example 1 // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Free Running Call this function to read the ADC value. The adc_input variable selects the ADC input pin. For example #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)); ADMUX = ADC_VREF_TYPE; ADCSRA = (1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); 0b0101 ADC5 (i.e., PC5) unsigned int read_adc(unsigned char adc_input) { ADMUX = adc_input ADC_VREF_TYPE; delay_us(10); // For stabilization of ADC input voltage } ADCSRA =(1<<ADSC); // Start the AD conversion while((adcsra&(1<<adif))==0) // Wait for AD conversion to complete ; ADCSRA =(1<<ADIF); return ADCW; Slide 39

40 Configuration Example 1 // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Free Running #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)); This comes from careful reading of the ADMUX = ADC_VREF_TYPE; ADCSRA = (1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); documentation ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); unsigned int read_adc(unsigned char adc_input) { ADMUX = adc_input ADC_VREF_TYPE; delay_us(10); // For stabilization of ADC input voltage } ADCSRA =(1<<ADSC); // Start the AD conversion while((adcsra&(1<<adif))==0) // Wait for AD conversion to complete ; ADCSRA =(1<<ADIF); return ADCW; Slide 40

41 Configuration Example 1 // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Free Running #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)); ADMUX = ADC_VREF_TYPE; ADCSRA = (1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (0<<ADIE) (1<<ADPS2) (0<<ADPS1) (1<<ADPS0); ADCSRB=(0<<ADTS2) (0<<ADTS1) (0<<ADTS0); unsigned int read_adc(unsigned char adc_input) { ADMUX = adc_input ADC_VREF_TYPE; Note that we are returning two bytes: delay_us(10); // For stabilization of ADC input voltage } ADCL and ADCH. In assembly language you have to make sure you ADCSRA =(1<<ADSC); // Start the AD conversion while((adcsra&(1<<adif))==0) read // Wait the bytes for in AD the conversion correct order to complete ; ADCSRA =(1<<ADIF); return ADCW; Slide 41

// ADC initialization // ADC Clock frequency: 1000.

42 // ADC initialization // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Timer0 Overflow #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)) ADMUX=ADC_VREF_TYPE; ADCSRA =(1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (1<<ADIE) (0<<ADPS2) (1<<ADPS1) (1<<ADPS0); ADCSRB =(1<<ADTS2) (0<<ADTS1) Note (0<<ADTS0); that we are returning two bytes: interrupt [ADC_INT] void adc_isr(void) { unsigned int adc_data; } adc_data=adcw; // Read the AD conversion result // Place your code here Configuration Example 2 In this example, we configure the ADC to be triggered every time TIMER0 overflows. Once the ADC conversion is complete, the ADC complete ISR is fired ADCL and ADCH. In assembly language you have to make sure you read the bytes in the correct order Slide 42

43 Configuration Example 2 In this example, we configure the ADC to be triggered every time TIMER0 overflows. Once the ADC conversion is complete, the ADC complete ISR is fired // ADC initialization // ADC Clock frequency: khz // ADC Voltage Reference: AVCC pin // ADC Auto Trigger Source: Timer0 Overflow This sets the ADC Interrupt Enable bit and enables the ADC conversion complete ISR #define ADC_VREF_TYPE ((0<<REFS1) (1<<REFS0) (0<<ADLAR)) ADMUX=ADC_VREF_TYPE; ADCSRA =(1<<ADEN) (0<<ADSC) (1<<ADATE) (0<<ADIF); ADCSRA = ADCSRA (1<<ADIE) (0<<ADPS2) (1<<ADPS1) (1<<ADPS0); ADCSRB =(1<<ADTS2) (0<<ADTS1) (0<<ADTS0); interrupt [ADC_INT] void adc_isr(void) { unsigned int adc_data; } adc_data=adcw; // Read the AD conversion result // Place your code here Slide 43

44 Review - ATmega88 Memory Map This is where the program is placed. Program variables Here one can place bootloader code, which is a small program that can have the controller reprogram itself. For example, to download new firmware. Slide 44

SRAM Adresses Some location in SRAM have

datasheets show the equivalent SRAM address

45 SRAM Adresses Some location in SRAM have what one can think of as synonyms, namely both a absolute SRAM address and another address within, say, I/O space The Atmel datasheets show the equivalent SRAM address in parenthesis I/O register Equivalent SRAM Slide 45

Accessing Various Parts of SRAM Different instructions access various parts of SRAM Instructions such as LDI access the general purpose registers IN and OUT instructions access

46 Accessing Various Parts of SRAM Different instructions access various parts of SRAM Instructions such as LDI access the general purpose registers IN and OUT instructions access locations/registers in I/O space STS and LDS access other SRAM locations Note that the ADC registers have only an SRAM address. Thus, one must use STS and LDS instructions to access these registers Slide 46

47 Code Snippets Below are some code snippets for accessing ADC registers. Modify these to suit your needs. ldi r23,0b0000_0101 ; Select PC5 on the ATmega88 sts ADMUX,r23 ldi r23,0b1100_0100 ; Enable, set, and start prescaler to 16 sts ADCSRA,r23 ; Start conversion lds r23,adcl lds r24,adch ; Read low byte of conversion into r23 ; Read high byte of conversion into r23 Slide 47

48 Aliasing and Nyquist The points below are the samples from a sine wave Voltage t Slide 48

49 Reconstruction of the sine wave Aliasing and Nyquist Voltage t Slide 49

50 But why not this reconstruction? Aliasing and Nyquist Voltage t Slide 50

51 Aliasing and Nyquist Both (an many others) are valid reconstructions if we don t exclude higher frequencies Voltage t In other words, if we don t eliminate (filter out) high frequencies, their samples become undistinguishable from low frequency samples. The high frequencies alias as low frequency signals. Slide 51

6πt) ( πt) Frequency f = 3 Hz Frequency f = 0.

52 Aliasing and Nyquist Sampling at 2.5 Hz (period = 0.4 s) the following signals are indistinguishable y( t) = sin y( t) = sin ( 6πt) ( πt) Frequency f = 3 Hz Frequency f = 0.5 Hz In fact, with sampling frequency of 2.5 Hz one can only correctly sample signal below the Nyquist frequency 2.5/2 = 1.25 Hz. Slide 52

53 Slide 53

EE 308: Microcontrollers

EE 308: Microcontrollers Timers Aly El-Osery Electrical Engineering Department New Mexico Institute of Mining and Technology Socorro, New Mexico, USA April 2, 2018 Aly El-Osery (NMT) EE 308: Microcontrollers