University of Nairobi. Project Title A F OUR CHANNEL-D MICROCONTROLLER BASED DATA ACQUISITION SYSTEM WITH A SERIAL INTERFACE TO THE PC

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1 University of Nairobi Project Title A F OUR CHANNEL-D MICROCONTROLLER BASED DATA ACQUISITION SYSTEM WITH A SERIAL INTERFACE TO THE PC Project Index (Number): PRJ061 By Candidate Name LENNOX ABONG O OGOLA Candidate Reg. Number F17/2040/2004 Supervisor: MR.COLLINS OMBURA Examiner: DR. H. ABSALOMS OUMA Project report submitted in partial fulfillment of the requirement for the award of the degree of Bachelor of Science in Electrical and Electronic Engineering of the University of Nairobi Date of Submission 20 th May, 2009 Department of Electrical and Information Engineering 1

2 DEDICATION To my beloved mum, Ruth Ogola. 2

3 AKNOWLEDGEMENTS I appreciate the support from my family, during my learning and the project session. Special thanks to my supervisor, Mr. Charles Ombura both technical and supervisory. I give much gratitude to Prof. Elijah Mwangi for introducing me to microcontroller applications which was very useful in my project. Much thanks also to Mr. Vincent Musau for being available for microcontroller consultation during my project. Fellow students and the entire University of Nairobi for the conducive learning environment, thanks a lot. 3

4 ABSTRACT In this project A Four Channel D Microcontroller based Data Acquisition System with a Serial Interface to the PC addresses the need to have acquired digital data fast enough to handle digital information which can comfortably be used with other digital devices, and to have the data acquired for display for the user. This project addresses a major key issue in the industrial processing data acquisition and control of plants. The necessary plant parameters are usually; fluid levels, temperatures, pressure, rate of flow of fluids; also applicable in weather focusing to obtain the weather measurements. This system makes data acquisition very easy and improves the efficiency of machine decision making where it is to interact with other devices. The project comes in handy to solve the problem of operators acquiring data manually from the analog devices they operate thus it is a relief to the operator. 4

5 CONTENTS Page Number COVER.... i DEDICATION......ii ACNOWLEDGMENT.... iii ABSTRACT.....iv CONTENTS...1 INTRODUCTION CHAPTER ONE: PROJECT OVERVIEW Sensors Digital signal conditioning Interfacing sensors to microcontrollers Programming the AVR- Atmega RS-232 Serial communication...14 CHAPTER TWO: PROJECT DESIGN IMPLEMENTATION...24 PART ONE: Appratus Hardware Development Schematic circuit diagram...26 PART TWO: The system program for AVR Atmega168 microcontroller The program simulation...30 CHAPTER THREE: RESULTS ANDANALYSIS Results and analysis evaluation...33 CHAPTER FOUR: CONCLUSION AND RECOMMENDATIONS...37 COSTING Limitations and design bottlenecks...38 APPENDIX...39 REFERENCES

6 INTRODUCTION Digital control systems are used in a wide variety of industries to increase productivity and efficiency. Industries that use digital control systems include food processing, oil refinery and steel production. Most of the physical parameters are analog. Digital systems must be able to convert these analog signals into digital form for processing by the computer and other digital systems. This is the job of the data acquisition system. In the sense the data acquisition system is the eyes and ears of the digital computer. The computer must also be able to convert its digital control actions into analog form for input to the analog actuators. The data distribution system is the hands and arms of the digital computer Digital Data Acquisition Most modern electronic systems have digital processing as the core. Yet the world we live in is essentially analogue. Thus, we need devices to convert from real world analogue domain to the digital domain. This is the function of the data acquisition system (DAS).The fig.1 below illustrates the basic elements of a generic DAS. Fig.1 The fundamental operation of the DAS is to sample the analogue signal at periodic intervals. These sampled values are then assigned a digital value. This is known as quantization. The quantized values are then coded for transmission. In this project the process of sampling has a first step in the digital data acquisition. Thereafter the output from the microcontroller output is fed into the line driver MAX232N which sends signals to the DB9/F of the PC. The PC receives the data through a serial port interface and displays it using the VB.NET program. 6

7 CHAPTER ONE: PROJECT OVERVIEW 1.1 Sensors Sensors are measuring instruments; they can measure any value within their range of measurement. The range is defined by the lower range limit and the upper range limit. As the name implies the range consists of all the values between the lower range limit and the upper range limit. The span is the difference between the upper and the lower limit. Span=Upper limit lower limit Resolution, dead band and sensitivity are different characteristics that relate in different ways to an increment of measurement. When the measured variable is continuously varied over the range, some measuring instruments change their output in discrete steps rather than in a continuing manner. The resolution of this type of measuring instrument is a single step of the output. Resolution is usually expressed as a percentage of the output span of the instrument. Sometime the size of the steps varies through the range of the instrument. In this case the largest resolution, expressed as a percentage of output span, is a hundred divided by the number of steps over the range of the instrument. Average Resolution (%) =100/N N = the total number of steps. The dead band of a measuring instrument is the smallest change in the measured variable that will result in measurable change in the output. Obviously, a measuring in device cannot measure changes in the measured variable that are smaller than its dead band. Threshold is another name for the dead band. The sensitivity of a measuring device is the ratio of the change in the output divided by the change in the input that caused the changes in the output. Sensitivity and gain are both defined as a change in the output divided by the corresponding change in the input. However, sensitivity refers to static values, whereas gain usually refers to the amplitude of sinusoidal signals. The LM35DZ (temperature sensor) measures between -40degrees centigrade to 85degrees centigrade, thus its span =125 degrees centigrade. Operation The reliability of a measuring device is the probability that it will do its job for a specified period of time under a specified set of conditions. The conditions included limits on the operating environment, the amount of the over range, and the amount of drift of the output. Over range is any excess in the value of the measured variable above the upper range limit or below the lower range limit. Over range limit is hence the maximum over range that can be applied to a measuring instrument without causing damage or permanent change in the performance of the device. Drift is an undesirable change over a specified period of time. Zero drift is a change in the output of the measuring instrument while the measured variable is held constant at its lower limit. Sensitivity drift is a change in the sensitivity of the instrument over the specified period. 7

8 Process variable sensors include: i. Temperature sensors i.e. thermistor, LM35DZ temperature sensor, thermocouple, radiation pyrometer ii. Flow rate sensors i.e. differential pressure, turbine, vortex shedding. iii. Pressure sensors i.e. strain gauge diaphragm, Bourdon element. iv. Level sensors i.e. displacement float, static pressure. Static Characteristics These describe the accuracy of the measuring device at room condition with the measured variable either constant or changing very slowly. Accuracy is the degree of conformity of an output of a measuring device to the ideal values of the measured variable determined by some standard. Accuracy is measured by testing the measuring instrument with a specified condition. The test is repeated a number of times and the accuracy is given as the maximum positive and negative error (deviation from ideal). The error is defined as the difference between the measured and the ideal value. Error=Measured Value-Ideal Value The repeatability of a measuring instrument is a measure of the dispersion of the measurements (the standard deviation) of another measure of dispersion. Repeatability is the maximum difference between several outputs for the same input when approached from the same direction in full range traversal. Reproducibility is the maximum difference between a number of outputs for the same input taken over an extended period of time, approaching from both directions. Dynamic Characteristics These describe the performance of the measuring instrument when the measured variable is changing rapidly. Most sensors do give an immediate, complete response to a sudden change in the measured variable. The sensor requires a certain amount of time before the complete response is indicated by the output. The amount of time required depends on the resistance, capacitance, and mass of inertance and the dead time of the instrument. Sensor Signal conditioning A measuring instrument consists of two ports, a primary element (or sensor) and a signal conditioner. The primary element uses some characteristics of its material and construction to convert the value of a measured variable into an electrical, mechanical, or fluidic signal. The output of the primary element may be small voltage or an electrical resistance. It may be a force, displacement, pressure or some other phenomenon. No matter what form it takes, the primary element output depends on the value of the measured variable. The output of the primary is a measure of the variable it is sensing, but it is seldom in a form suitable for transmission signal, hence a conditioner is required to convert it into a suitable value. 8

9 The standard transmission signals are 4-20mA electric current or 3-15 psi pneumatic pressure. The tasks of the signal conditioner are: i. Isolation and impedance conversion ii. Amplification and analog to analog conversion iii. Noise reduction and filtering iv. Linearization v. Data sampling vi. Digital to analog conversion vii. Analog to digital conversion SAMPLING Sampling is the acquisition of a continuous signal at discrete time intervals and is a fundamental concept in real-time signal processing. A requirement for sampling is the following: Sampling frequency must be at least twice as great as the highest message signal Frequency (f M) if the original signal is to be recoverable Aliasing may be reduced by the use of a low-pass, PRE-ALIAS filter to attenuate the high frequency components of a signal that lie outside the band of interest before sampling; and then sampling the signal at a rate higher than 2f M per second. Practical Sampling A physical signal cannot be band-limited in frequency as this would mean that it exists over all time-not limited in time (property of the FT-Fourier Transform). Since physical signals are of finite duration it implies that they must have frequency components over the whole frequency spectrum. However a physical signal does exist such that the amplitude of the frequency spectrum above a certain frequency is so small that it is negligible. We see that another requirement for sampling is that: Frequency spectrum of the signal be insignificant above the frequency f s 2 where f s is the sampling frequency. f Frequency s is called the NYQUIST frequency. 2 This is also known as Shannon s Sampling Theorem (also called Nyquist Sampling Theorem). Formally stated the Theorem says that: A band-limited signal of finite energy, which has no (significant) frequency components higher than Fm Hertz, is completely described specifying the values of the signal at instants of time separated by at most 1/2Fm seconds. Alternatively, 9

10 A band-limited signal of finite energy, which has no (significant) frequency components higher than Fm Hertz, may be completely recovered from knowledge of its samples taken at a rate of 2Fm per second. The rate 2f M is called the Nyquist rate. We thus note that when the sampling frequency f s exceeds the Nyquist rate, all replicas of X (f) in X s (f) move further apart and there is no problem recovering x (t) from the sampled version x s (t) Sampling With a Zero Order Hold. The Sampling theorem has been explained in terms of impulse-train sampling. However, in practice, narrow large-amplitude pulses which approximate impulses are relatively difficult to generate and transmit. It is often more convenient to generate the sampled signal in a form known as a zero-order hold. This system samples x (t) at a given time instant and holds that value until the next instant. x(t) Zero Order x o (t) Fig.2 The reconstruction of x (t) from the output of a zero-order hold can be achieved by low pass filtering. However, the required filter no longer has constant gain in the pass band. Let us try to develop this filter characteristic curve. We note that x o (t) can be generated by impulse train sampling followed by an LTI system with a rectangular impulse response as shown below: δ Ts ( t) x(t) x p (t) 1 h 0 (t) x o (t) 0 T Fig.3 10

11 x(t) x p (t) x o (t) Fig.4 To reconstruct x (t) from x o (t) we consider processing x o (t) with an LTI system with impulse response x r (t). We need to specify H r (jw) so that r (t) = x (t). We note that this will only be true if the cascade combination of h 0 (t) and h r (t) is the ideal low pass filter H (jw). δ(t) H (jw) X (t) Xp (t) 1 h 0 (t) Xo (t) Hr (t) R (t) 0 T Fig.5 Or similarly H (jw) = H 0 (jw).h r (jw) But we know that the spectrum of h0 (t) is: 11

12 H 0 ( jw) Hence it is required that H r ( jw) = e T jw 2 T = e 2 = T e = T e 2sin T jw 2 T jw 2 T jw 2 T jw T jw wt w / 2 2sin wt wt / 2 wt sin c( ) 2π sin c( ft ) 2 e H ( jw) = 2sin( wt / 2) w 2 e H ( jw) = T sin c( wt / 2π ) / 2 For example, With cutoff frequency of w s /2 radians, the ideal magnitude and phase for the reconstruction filter following a zero-order hold is as below: H r (jw) H r (jw) 1 π/2 (2) w s 2 w s 2 W w s 2 -π/2 w s 2 W Fig.6 We note that the actual realization of equation (2) is not possible without an approximation. In fact in many situations the output of the zero-order hold is considered an adequate approximation to the original signal by itself. Alternatively in some applications we may wish to perform a smoother interpolation between sample values. Two important forms of data reconstruction exist: 1. Interpolation (suitable for data transmission systems) 2. Extrapolation (suitable for feedback systems) Extrapolation is interpolation extended to points outside the convex hull of a dataset. Interpolation values at a point outside the convex hull of an input dataset are referred to as extrapolated values. 12

13 1.2. Digital signal conditioning Filtering, linearization, calibration, and conversion to engineering units can be accomplished by a microprocessor working with the digitized samples. Digital signal processing makes it possible to extract additional information from the signal. Digital filtering consists of computing some type of weighted average of the current sample and previous samples. Digital linearization and calibrations are accomplished by storing factory calibration data in some type of read only memory for use by the microprocessor. Digital calibration produces accuracies that cannot be achieved by analog calibration, with the added benefit of using the actual engineering units for the calibrated signals. Data Sampling This is a process in which a switch connects momentarily to an analog signal in a sequence of pulses separately by evenly spaced increments of time called the sampling interval. It can also be seen that data sampling is the result obtained by multiplying the analog signal by a series of pulses with amplitude of 1; a very narrow pulse width and a period equal to the sampling interval. The sample and hold circuit is used to hold a sample of an analog signal as it is converted to a digital signal by an analog to digital converter. It operates in two modes: the sampling or tracking mode when the switch is closed and the holding mode when the switch is open. The ideal sample and hold takes a sample in zero time and holds the signal value indefinitely with no degradation of the signal. This circuit is called a zero-order sample and hold circuit. A practical sample and hold circuit varies from the ideal in a number of parameters. The following are some parameters of a practical sample and hold circuit: 1. Acquisition time: is the time from the instant the sample command is given until the output is within a specified band of the input. This is determined by the size of the input resistor and the holding capacitor. These two elements form a first-order lag with a time constant equal to the product of the resistance times the capacitance. Time constant=t=rinc 2. An acquisition time equal to five times the time constant is enough for the output to reach 99.3% of the total change to the new input value. This assumes the input is constant during the sampling period. 3. The aperture time is the time it takes for the switch to open. It is the time between the hold command and the time the switch is completely open. 4. The decay rate of change of the output in the holding mode. It is caused by leakage through the capacitor and small current that enters the OP amp through the inverting input. 5. All the signal information in the original form is can be recovered if it is sampled at least twice during each cycle of the highest-frequency that occurs in the original then the minimum sampling rate is given by the following equation. Minimum sampling rate=fs (min) =2fh 13

14 Data Conversion The sensors are interfaced to the microcontroller using analog to digital converters. These are data converters which form the interface between the analog and the digital domains. The analog to digital converter (ADC or A/D) converts analog signals into digital code. The digitalto-analog converter (DAC or D/C) converts digital code into analog voltage levels. The inputs to an A/D converter are analog voltage that can have any value from zero to its full scale (FS) range. The output, however, can have only a finite number of output codes, each defining a state of the ADC. The resolution of an A/D converter is defined as the number of bits in the output code. If n is the number of bits, then 2 n is the number of the output states. Thus a 3-bit ADC has 2 3 =8 states. In between each pair of steps is a transition that makes the change from one output to another. There is always one less transition than the number of states; hence an n-bit ADC has 2 n - 1 transitions. At any state, there is a small range of input voltages that forms a step that extends from one transition to the next. This range of values is called the quantization size or width of the code. The ideal width of each interior step is designated as Vlsb, where lsb signifies least significant bit. Resolution is sometimes expressed in terms of Vlsb. This value of Vlsb is equal to the full-scale range of the input divided by the number of outputs states. Resolution=Vlsb=FS/2 n Where, FS-full scale, 2 n transition states On each step, there is an error, called quantization error-that ranges from Vlsb/2 on the night. Quantization error=-fs/16 or +FS/16 for 3-bit ADC. Analog to digital converter The function of the ADC is to produce a digital code word that accurately represents the level of the analog input voltage. The various A/D are: i. Binary counter techniques that use a binary counter connected to D/A counter and a comparator to generate the digital word that represents an analogy input. ii. The successive approximation technique sequentially compares a series of binary weighted values with the analog input to generate a digital word that represents the analog voltage. iii. The single slope technique uses s fixed rate variable time ramp voltage to generate a digital word that represents the analog input voltage. iv. The flash or parallel technique compares the analog input voltage with a set of reference voltages to generate the digital word that represents the analog input. 14

15 Interfacing sensors to microcontrollers The fig.7 below shows how to interface AVRs with external devices which acquire data and send to it or execute commands from it. Fig.7 Programming the AVR Atmega88 The AVRstudio4 software is used to write the project code in assembly language programming language. The code is then burnt into the microcontroller using the ISP programming interface by running the avrdude as shown. Running AVRDUDE Avrdude is a command line program, so you'll have to type in all the commands. 15

16 Under Windows, open up a command window, select Run... from the Start Menu and type in cmd and hit OK. Now in the new terminal window type in avrdude you should get this response, which is basically a simple list of what avrdude can do. AVRDUDE options There are a lot of options, they are reviewed as: -p <partno>: This is just to tell it what microcontroller its programming. For example, if you are programming an atmeg88, use m88 as the partnumber -b <baudrate>: This is for overriding the serial baud rate for programmers like the STK500. Don't use this switch, the default is correct. -B <bitrate>: This is for changing the bitrate, which is how fast the programmer talks to the chip. If your chip is being clocked very slowly you'll need to talk slowly to it to let it keep up. It'll be discussed later, for now don't use it. -c <programmer>: Here is where we specify the programmer type, if you're using an bsd for the ISP forprogramming. -P <port>: This is the communication port to use to talk to the programmer. It might be COM1 for serial or LPT1 for parallel or USB for, well, USB. -F: This overrides the signature check to make sure the chip you think you're programming is. The test is strongly recommended as it tests the connection, so don't use this switch. -e: This erases the chip, in general we don't use this because we auto-erase the flash before programming. -U <memtype>:r w v:<filename>[:format]: OK this one is the important command. It s the one that actually does the programming. The <memtype> is either flash or eeprom memory. The r w v means you can use r (read) w (write) or v (verify) as the command. The <filename> is, well, the file that you want to write to or read from. And [: format] means there s an optional format flag. We will always be using "Intel Hex" format, so use i.so, for example. If you wanted to write the file test.hex to the flash memory, you would use -U flash:w:test.hex:i. If you wanted to read the eeprom memory into the file "eedump.hex" you would use -eeprom:r:eedump.hex:i -n: This means you don't actually write anything, its good if you want to make sure you don't send any other commands that could damage the chip, sort of a 'safety lock'. -V: This turns off the auto-verify when writing. We want to verify when we write to flash so don't use this. -u: If you want to modify the fuse bits, use this switch to tell it you really mean it. -t: This is a 'terminal' mode where you can type out commands in a row. Don't use this, it is confusing to beginners. -E: This lists some programmer specifications, don't use it. -v: This gives you 'verbose' output...in case you want to debug something. If you want you can use it, but in general we won't. -q: This is the opposite of the above, makes less output. bsd= serial port banging, reset=!dtr sck=rts mosi=txd miso=cts -P <port> This switch tells avrdude where to look for your programmer. If you are using a USB connected device, you can just use -P usb or, leave it out. The programmer automatically knows when the programmer is a USB device. 16

17 -U <memtype>:r w v:<filename>[:format]: OK we're at the important part. This is where we actually get around to telling avrdude how to put the data onto the chip. This command is rather complex, but we'll break it down. <memtype> - can be flash, eeprom, hfuse (high fuse), lfuse (low fuse), or efuse (extended fuse) r w v - can be r (read), w (write), v (verify) <filename> - the input (writing or verifying) or output file (reading) AVR target board ready to go, we'll be using an atmega88 in this example but of course you should substitute the chip you're using (in which case the code will probably not do anything). Make sure the device is powered, either by batteries or a wall plug or by the programmer if the programmer can do it. Download the prog.hex file and place it in C:\ (Windows) or your home directory (Mac). Type in avrdude -c bsd pm88 -U flash:w:prog.hex Avrdude should go through the following steps: 1. Initializing the programmer (you wont see this if it works) 2. Initializing the AVR device and making sure its ready for instructions 3. Reading the device signature (0x1e910a) which confirms that the chip you specified in the command line (attiny2313) is in fact the chip that the programmer is connected to. 4. Erasing the chip 5. Reading the file and verifying its a valid file 6. Writing the flash 7. Verifying the flash What can go wrong: AVR initialization failed if the programmer is not properly connected to the chip, you'll get the following message: initialization failed, rc=-1 Double check connections and try again, or use -F to override this check. Don't use -F to override the check, even though it is suggested! This means that the programmer couldn't talk to the chip. If you are using a "simple" programmer such as a serial or parallel port bitbang programmer, it could mean the programmer is at fault. Otherwise, it usually means the programmer is OK but it could not find the chip. Check that the chip is powered, plugged into the socket or programmer properly, the programming cables are plugged in correctly, the header is wired correctly, etc. 99% of the time, it is a problem with wiring running this command avrdude -c bsd pm88 -U flash:w:test_leds.hex RS-232 SERIAL COMMUNICATION Introduction to RS-232 Serial Port RS-232 was created to interface between Data Terminal Equipment and Data Communications Equipment (DCE) employing serial binary data interchange. Therefore, DTE is the terminal or computer and the DCE is the modem or other communication device, Serial Transmission Methods The table1 below shows the serial transmission methods used in communication between the computers and devices. 17

18 SERIAL (RS232) NULL MODEM CABLE (DB9-DB9). PINOUT AND SIGNALS FOR BUILDING A SERIAL (RS232) NULLMODEM CABLE Use this cable between two DTE devices (for instance two computers). DB9 pin D-SUB female to PC1 DB9 pin D-SUB female to PC2 DB9-1 DB-2 Receive Data 2 3 Transmit Data Transmit Data 3 2 Receive Data Data Terminal Ready Data Set Ready + Carrier Detect System Ground 5 5 System Ground Data Set Ready + Carrier Detect Data Terminal Ready Request to Send 7 8 Clear to Send Clear to Send 8 7 Request to Send AVR serial commnucation (USART0) The serial interface has the following features Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data Overrun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode 18

19 Double Speed Asynchronous Communication Mode The USART can also be used in Master SPI mode, Power Reduction USART bit, PRUSART0, in Minimizing Power Consumption must be disabled by writing a logical zero to it. Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal).xcki Input from XCK pin (internal Signal). Used for synchronous slave operation xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation fosc XTAL pin frequency (System Clock). Internal Clock Generation The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(ubrrn+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. Prescaling Down-Counter /2 UBRRn/4 /2 19

20 There must be calculation of the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Notably the baud rate is defined to be the transfer rate in BAUD- Baud rate (in bits per second, bps), fosc System Oscillator clock frequency. UBRRn are the contents of the UBRRnH and UBRRnL Registers. Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. External Clock External clocking is used by the synchronous slave modes of operation. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited. Notably the fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Synchronous Mode XCKn Timing. The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. When UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it 20

21 can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Bits inside brackets are optional. Frame Formats St Start bit, always low (n) Data bits (0 to 8). P Parity bit can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: -Peven Parity bit using even parity -Podd Parity bit using odd parity -dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. The ATmega48/88/168 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of PortA. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ± 0.3V from VCC. Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. The Power Reduction ADC bit, PRADC, in Minimizing Power Consumption must be disabled by writing a logical zero to enable the ADC. The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. Analog to Digital Converter Operation The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is 21

22 presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Starting a Conversion A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in Minimizing Power Consumption by writing a logical zero to it and writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing By default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 khz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 khz. The prescaling is set by the ADPS bits in ADCSRA. The 22

23 prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. When the bandgap reference voltage is used as input to the ADC, it will take a certain time for the voltage to stabilize. If not stabilized, the first value read after the first conversion may be wrong. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of a first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. It is thus advisable not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care is taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: a. When ADATE or ADEN is cleared. b. During conversion, minimum one ADC clock cycle after the trigger event. c. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. 23

24 In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as AVCC, internal 1.1V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedance voltmeter. Note that VREF is a high impedance source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. ADC Noise Canceller The ADC features a noise canceller that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceller can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 kω or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to 24

25 only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fadc/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI (Electromagnetic Interference) which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network. c. Use the ADC noise canceller function to reduce induced noise from the CPU. d. If any ADC [3..0] port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 10μH 100nF Analog Ground Plane) Offset Error Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB.Gain Error Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 Integral Non-linearity (INL) Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Differential Non-linearity (DNL) Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value, always ±0.5 LSB. Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ±0.5 LSB. ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is where VIN is the 25

26 voltage on the selected input pin and VREF the selected voltage reference (it is seen that 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB). ADMUX ADC Multiplexer Selection Register Bit 7:6 REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Bit 5 ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. Bit 4 Res: Reserved Bit This bit is an unused bit in the ATmega48/88/168, and will always read as zero. Bits 3:0 MUX3:0: Analog Channel Selection Bits REFS1 REFS0 ADLAR MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value Voltage Reference Selections for ADC REFS1 REFS0 Voltage Reference Selection 0 0 for AREF, Internal Vref turned off 0 1 for AVCC with external capacitor at AREF pin 1 0 are Reserved 1 1 for Internal 1.1V Voltage Reference with external capacitor at AREF pin. The value of these bits selects which analog inputs are connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). ADCSRA ADC Control and Status Register A Bit 7 ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion. Bit 6 ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. Input Channel Selections Bit 5 ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. Bit 4 ADIF: ADC Interrupt Flag 26

27 This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read- Modify- Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. Bit 3 ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. Bits 2:0 ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. ADCL and ADCH The ADC Data Register ADLAR = 0 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. ADC9:0: ADC Conversion Result These bits represent the result from the conversion. ADCSRB ADC Control and Status Register B Bit 7, 5:3 Res: Reserved Bits These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when ADCSRB is written. Bit 2:0 ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the Bit Read/Write R R/W R R R R/W R/W R/W Initial Value trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. 27

28 CHAPTER 2: PROJECT DESIGN AND IMPLEMENTATION The concepts expressed in the previous chapters are employed here in the design and implementation of the project. The hardware development and the software development have been covered here. Apparatus -A personal computer -Sensors (LM35DZ Temperature sensor) -VB.NET development tools -AVR Atmega168 Microcontroller -AVRstudio4 assembler -MAX232N line driver -9v Battery Voltage Regulator -Capacitors 22pF (2), 10nF (5), 100nF (4) -LED -Resistors (10K), (0.1k) -Limrose board -16MHz crystal oscillator Choosen Platform The design was mainly based on windows platform. Data Acquisition Design Procedure Expected end Results At the end of the design and implementation, a user should be able to read the data acquired from the sensors over the personal computer. As for the room temperature the user should read degrees centigrade depending on the room temperature. Other sensor parameters should acquired as the sense specifications. Software Development 1. Specifying software: The software was stated here explicitly with details of its functions i.e. how the user will interact with and control the system. The graphical user interface VB.NET program was 28

29 developed to assist the user view the data acquired by the system. Equally the program for the microcontroller was also developed. Where this interface failed to install, the windows HyperTerminal was used which also received the acquired data as expected. The Graphical User Interface: The V.NET was used where four windows were developed to display the data for each channel acquired from the sensors. It was provided with command windows to choose the particular serial port of the computer where the system has been connected. When the system is connected it acknowledges that it has been connected, indicates the data being sent. The AVR Atmega168 program 2. Designing software: The AVRstudio4 was used to write the program for the microcontroller. 3. Editing and translation: This was done using the AVR assembler; errors detected by the assembler were quickly corrected by editing the source file and reassembling, (Build and Run command in the AVR Studio4 Assembler).Mostly syntax errors also called assembler-run-time errors occurred. 4. Preliminary Testing: a run-time error does not appear until the program was executed by a simulator. A debugger was used in the assembler (AVR sutudio4). The debugger included features which executed the program until, a certain address (a breakpoint) was reached and single stepping through instructions while displaying the CPU registers, the program-counter, status bits and input output ports. HARDWARE DEVELOPMENT Specifying the hardware: Assigning quantitative data to system functions I/O ports; numbers of sensors. Designing Hardware: Using Express PCB and circuitmaker traxmaker to draw the schematic diagram. Building and prototype: Used the breadboard and wire wrapping method for prototype. Preliminary testing: The first test was taken in the absence of any application software. Stepwise testing was used.ie. -visual checks -continuity checks using the Digital Multimeter -Direct current measurements for outputs of the integrated circuits used. Integration and Verification -The hardware and the software were combined together.i.e. interfacing the AVR microcontroller with the appropriate support circuitry for the project design; this enables the microcontroller to interact with peripheral devices like the personal computer. The sensors, line driver, capacitors, resistors, inductors and jumpers,db9/f connector were all connected. The program code for the microcontroller was also burnt into it. 29

30 30 THE SCHEMATIC CIRCUIT DESIGN PB0/ICP1/CLKO/PCINT0 14 PB1/OC1A/PCINT1 15 PB3/MOSI/OC2A/PCINT3 17 PB2/SS/OC1B/PCINT2 16 PD6/AIN0/OC0A/PCINT22 12 PD5/T1/OC0B/PCINT21 11 PD4/T0/XCK/PCINT20 6 PD3/INT1/OC2B/PCINT19 5 PD2/INT0/PCINT18 4 PD1/TXD/PCINT17 3 PD0/RXD/PCINT16 2 PB4/MISO/PCINT4 18 PB5/SCK/PCINT5 19 PB7/TOSC2/XTAL2/PCINT7 10 PB6/TOSC1/XTAL1/PCINT6 9 PC6/RESET/PCINT14 1 PC5/ADC5/SCL/PCINT13 28 PC4/ADC4/SDA/PCINT12 27 PC3/ADC3/PCINT11 26 PC2/ADC2/PCINT10 25 PC1/ADC1/PCINT9 24 PC0/ADC0/PCINT8 23 AVCC 20 AREF 21 PD7/AIN1/PCINT23 13 U1 ATMEGA88 T1IN 11 R1OUT 12 T2IN 10 R2OUT 9 T1OUT 14 R1IN 13 T2OUT 7 R2IN 8 C2+ 4 C2-5 C1+ 1 C1-3 VS+ 2 VS- 6 U2 MAX232 PACKAGE=CONN-DIL16 ERROR TXD 3 RXD 2 CTS 8 RTS 7 DSR 6 DTR 4 DCD 1 RI 9 P1 COMPIM P_PORT=COM1 P_STOPBITS=1 C1 1U C2 1U C3 1U VOUT 2 U3 LM VOUT 2 U4 LM VOUT 2 U5 LM VOUT 2 U6 LM35

31 THE SYSTEM PROGRAM FOR ATMEGA168 Using Assembly language programming The ADC Conversion Flow Chart Fig.8 The flow chart shows the routine to start A/D conversion. It preloads the counter with and starts counting up at frequency XTAL/8 (XTAL- crystal oscillator used). The conversion complete flag (The T-flag in the status register) is then cleared. The code was written and tested using the AVRstudio4, the files below:.hex and the.asm were obtained. This was the.asm file //A Four Channel D microcontroller based data acquisirion System //with a serial interface to the PC //AVR atmega168 microcontroller used //Assembler AVRstudio4 //Lennox Abong'o Ogola //F17/2040/2004.INCLUDE"m168def.INC".DEF mp=r16.def mp1=r17.def tc0_inc=r1.def counter=r2.def adc_counter=r25.org $000 rjmp main.org $001 ret.org $002 reti.org $003 reti.org $004 reti 31

32 .org $005 reti.org $006 reti.org $007 reti.org $008 reti.org $009 reti.org $00A reti.org $00B reti //jmp tc0.org $00C reti.org $00D reti //jmp USART_RX.org $00E reti //jmp USART_UDRE.org $00F reti.org $010 reti.org $011 reti.org $012 reti.org $013 reti.org $014 reti.org $015 rjmp ADC_interupt ;adc interrupt.org $016 reti.org $017 reti.org $018 reti.org $019 reti ADC_interupt: ; ADC interrupt label, and in mp,adcl0 ; loading ADC conversion ADCL0 to mp register for transmission rcall USART_TX ldi mp,8 in mp,adch0 ;loading the ADC conversion ADCH0 to mp reg. for transmission rcall USART_TX ldi mp,4 ;looping through the ADC channels cp mp,adc_counter brne inc_counter ldi adc_counter,0 rjmp call_admux inc_counter: inc adc_counter call_admux: rcall ADMUX_reset reti ADMUX_reset: mov mp,adc_counter ldi mp1,0b or mp,mp1 sts ADMUX,mp ldi mp,0b

33 sts ADCSRA,mp ret main: LDI mp1,high(ramend) ; Stack initialization OUT SPH,mp1 LDI mp1,low(ramend) OUT SPL,mp1 ldi adc_counter,0 ; initialize the adc channel counter until 4 ldi mp,0b ;1st adc channel is enabled, others enabled automatically sts ADMUX,mp sei ; enable baud rate registers ldi mp1,12; load value 103 for 9600 baud rate sts UBRR0L,mp1 ; from conversion table datasheet ldi mp1,0 ; UBBRH loaded with zero sts UBRR0H,mp ; enable USART parameters databits,parity, etc ldi mp1,0b ; enable RXCIE,TXCIE,UDRE,RXEN,TXNE,0(b databits 011 UCSRC),0,0 sts UCSR0B,mp1 ; USART Control Status Register B ldi mp1,0b ; Select UCSRC,Asyc mode,no parity(00) sts UCSR0C,mp1 ; one stop bit,8bits data(11), Asy mode ADC_conversion: ; initiating ADC data conversion ldi mp,0b sts ADCSRA,mp loop: nop rjmp loop USART_TX: ; Data transmission sts UDR0, mp reti The Hex file : FC : EC : DC : : B121D000B11FD004E : F490E001C D F10ECA0 : B00937C000FE600937A E0D2 : EBF1FEF1DBF1CE01093C40010E00093E3 33

34 : C50008E00093C C00015FF6D : FCCF0093C60056 : FF The program simulation Fig.9.0 The fig.9 shows the AVRstudio4 window that was used to program the AVR Atmega microcontroller. The processor window, the debug environment and the simulation window were all used within the programming. The response of the various registers could be observed from the window as the program was being executed within the simulator. 34

35 Fig.9.1 The fig.9.1 shows more of the programming environment, the serial transmission register, UDRE0-USART Data Register empty was being simulated. 35

36 Fig.9.2 The programming window showing interrupt vector space for the code, the ADC Interrupt Flag is also shown. When the flag was high it indicated an input from the ADC channels of the input sensor, this triggered an interrupt to initiate conversion of the received data. 36

37 CHAPTER THREE: RESULTS AND ANALYSIS This focuses on the results obtained for data acquisition system displayed over the computer graphical user interface. The following results were obtained using the Windows HyperTerminal. CHANNEL_1 TEMPERATURE READINGS Fig.10.0 The fig.10.0 shows the readings of the LM35DZ temperature sensor, measuring the room temperature. In this case the channel 1 of the data acquisition system was used. The average temperature reading was = Total sum of the readings/the number of the readings =972/36 =27 degrees centigrade. 37

38 CHANNEL_2 TEMPERATURE READINGS Fig.10.1 The fig.10.1 shows the readings of the LM35DZ temperature sensor, measuring the room temperature. In this case the channel 2 of the data acquisition system was used. The average temperature reading was = Total sum of the readings/the number of the readings =624/24 =26 degrees centigrade. 38

39 CHANNEL_3 TEMPERATURE READINGS Fig.10.2 The fig.10.2 shows the readings of the LM35DZ temperature sensor, measuring the room temperature. In this case the channel3 of the data acquisition system was used. The average temperature reading was = Total sum of the readings/the number of the readings =648/24 =27 degrees centigrade. 39

40 CHANNEL_4 TEMPERATURE READINGS Fig.10.3 The fig.10.3 shows the readings of the LM35DZ temperature sensor, measuring the room temperature. In this case the channel 4 of the data acquisition system was used. The average temperature reading was = Total sum of the readings/the number of the readings =672/24 =28 degrees centigrade. On average the room temperature was the average of the three readings = ( )/4 =27 degrees centigrade. 40

41 CHAPTER FOUR: CONCLUSION AND RECOMMENDATION CONCLUSION The four channel-d microcontroller based data acquisition system was designed and implemented successfully. The design and implementation was based on the connecting the data acquisition stem to the personal computer through a serial communication port and devising software to carry out the data processing and display to the computer. The results obtained for the data acquisition system enabled the user to determine the measured values of the particular device by clicking on the particular window for the sensor. The user can therefore tell the readings of the sensors with ease and fast enough given that the rate of data sending is high enough. The system allows an immediate response to any change in the parameters of the phenomena being measured, thus any alterations in the sensor readings is displayed immediately. The limitations of the software both the microcontroller and the graphical user interface were analyzed and possible solutions given. The limitations were mainly on the largest number of channels that would be comfortably be accommodated by the microcontroller, since the Atmega168 has limited ADC channels. RECOMMENDATIONS To enhance documentation of the data acquired and efficiency with reference to records of the data acquired, a database would be created to store the data. The addition of more sensors is encouraged to ensure that the microcontroller ADC input pins are wholly used. I would also recommend the duplex communication environment to enable the user make decision to the microcontroller based on the data acquired. 41

42 COSTING The project costs $50 The main cost is incurred is on the4 AVR microcontroller and the sensors. Limitations and design bottlenecks The major limitation was the graphical user interface created, it was constantly interfered with by the antivirus. However, the windows HyperTerminal was used instead to acquire the data. APPENDIX Appendix A: AVR datasheet 42

43 43

44 Appendix B: LM35DZ temperature sensor. Block diagram-the internal circuitry 44