ATmega 16. Dariusz Chaberski
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1 ATmega 16 Dariusz Chaberski
2 Obudowy 2
3 Schemat blokowy 3
4 4
5 5
6 Pamięć EEPROM The EEPROM Address Register The EEPROM Data Register 6
7 The EEPROM Control Register EERIE: EEPROM Ready Interrupt Enable EEMWE: EEPROM Master Write Enable EEWE: EEPROM Write Enable EERE: EEPROM Read Enable 7
8 System przerwań wektory przerwań 8
9 Lokalizacja wektorów przerwań General Interrupt Control Register IVSEL: Interrupt Vector Select IVCE: Interrupt Vector Change Enable 9
10 Przerwania zewnętrzne MCU Control Register ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 10
11 ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 MCU Control and Status Register ISC2: Interrupt Sense Control 2 11
12 General Interrupt Control Register INT1: External Interrupt Request 1 Enable INT0: External Interrupt Request 0 Enable INT2: External Interrupt Request 2 Enable INTF1: External Interrupt Flag 1 INTF0: External Interrupt Flag 0 INTF2: External Interrupt Flag 2 12
13 8-bit Timer/Counter0 with PWM 13
14 Output Compare Unit 14
15 Compare Match Output Unit 15
16 Clear Timer on Compare Match (CTC) Mode 16
17 Fast PWM Mode 17
18 Phase Correct PWM Mode 18
19 Diagramy czasowe dla trybów non-pcpwm (bez preskalera) 19
20 z preskalerem 8 20
21 z preskalerem 8 ustawianie OCF0 21
22 z preskalerem 8 ustawianie OCF0 dla trybu CTC 22
23 Timer/Counter Control Register 0 FOC0: Force Output Compare WGM01:0: Waveform Generation Mode COM01:0: Compare Match Output Mode CS02:0: Clock Select 23
24 Compare Output Mode, non-pwm Mode Compare Output Mode, Fast PWM Mode 24
25 Compare Output Mode, Phase Correct PWM Mode Clock Select 25
26 Timer/Counter Register Output Compare Register 26
27 Timer/Counter Interrupt Mask Register OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable TOIE0: Timer/Counter0 Overflow Interrupt Enable Timer/Counter Interrupt Flag Register OCF0: Output Compare Flag 0 TOV0: Timer/Counter0 Overflow Flag 27
28 Timer/Counter0 and Timer/Counter1 Prescalers 28
29 Special Function IO Register PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 29
30 External Clock Source 30
31 16-bit Timer/Counter1 31
32 Counter Unit 32
33 Input Capture Unit 33
34 Output Compare Units 34
35 Compare Match Output Unit 35
36 Clear Timer on Compare Match (CTC) Mode 36
37 Fast PWM Mode 37
38 Phase Correct PWM Mode 38
39 Phase and Frequency Correct PWM Mode 39
40 Timer/Counter Timing Diagram, Setting of OCF1x, No Prescaling, double buffering modes 40
41 Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler 8, double buffering modes 41
42 Timer/Counter Timing Diagram, no Prescaling, various modes When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM 42
43 Timer/Counter Timing Diagram, with Prescaler =8, various modes When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM 43
44 Timer/Counter1 Control Register A COM1A1:0: Compare Output Mode for Channel A COM1B1:0: Compare Output Mode for Channel B FOC1A: Force Output Compare for Channel A FOC1B: Force Output Compare for Channel B WGM11:0: Waveform Generation Mode 44
45 Timer/Counter1 Control Register B ICNC1: Input Capture Noise Canceler ICES1: Input Capture Edge Select WGM13:2: Waveform Generation Mode CS12:0: Clock Select 45
46 Compare Output Mode, non-pwm 46
47 Compare Output Mode, Fast PWM 47
48 Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM 48
49 WGM13:0: Waveform Generation Mode 49
50 Clock Select Bit Description 50
51 Timer/Counter 1 Output Compare Register 1 A 51
52 Output Compare Register 1 B Input Capture Register 1 52
53 Timer/Counter Interrupt Mask Register Timer/Counter1, Input Capture Interrupt Enable Timer/Counter1, Output Compare A Match Interrupt Enable Timer/Counter1, Output Compare B Match Interrupt Enable Timer/Counter1, Overflow Interrupt Enable 53
54 Timer/Counter Interrupt Flag Register Timer/Counter1, Input Capture Flag Timer/Counter1, Output Compare A Match Flag Timer/Counter1, Output Compare B Match Flag Timer/Counter1, Overflow Flag 54
55 8-bit Timer/Counter2 with PWM and Asynchronous Operation 55
56 Asynchronous Status Register AS2: Asynchronous Timer/Counter2 TCN2UB: Timer/Counter2 Update Busy OCR2UB: Output Compare Register2 Update Busy TCR2UB: Timer/Counter Control Register2 Update Busy 56
57 Timer/Counter Prescaler 57
58 Analog to Digital Converter 58
59 ADC Auto Trigger Logic 59
60 ADC Prescaler 60
61 ADC Timing Diagram, First Conversion (Single Conversion Mode) 61
62 ADC Timing Diagram, Single Conversion 62
63 ADC Timing Diagram, Auto Triggered Conversion 63
64 ADC Timing Diagram, Free Running Conversion 64
65 ADC Conversion Time 65
66 ADC Power Connections 66
67 Differential Measurement Range 67
68 ADC Conversion Result 68
69 ADC Multiplexer Selection Register REFS1:0: Reference Selection Bits 69
70 MUX4:0: Analog Channel and Gain Selection Bits 70
71 ADC Control and Status Register A ADEN: ADC Enable ADSC: ADC Start Conversion ADATE: ADC Auto Trigger Enable ADIF: ADC Interrupt Flag ADIE: ADC Interrupt Enable 71
72 ADPS2:0: ADC Prescaler Select Bits 72
73 The ADC Data Register ADLAR = 0 ADLAR = 1 73
74 Special FunctionIO Register ADTS2:0: ADC Auto Trigger Source 74
75 Serial Peripheral Interface 75
76 SPI Master-Slave Interconnection 76
77 SPI Control Register SPIE: SPI Interrupt Enable SPE: SPI Enable DORD: Data Order MSTR: Master/Slave Select CPOL: Clock Polarity CPHA: Clock Phase 77
78 SPR1, SPR0: SPI Clock Rate Select 1 and 0 78
79 SPI Status Register SPIF: SPI Interrupt Flag WCOL: Write COLlision Flag SPI2X: Double SPI Speed Bit SPI Data Register 79
80 CPOL and CPHA Functionality 80
81 SPI Transfer Format with CPHA = 0 81
82 SPI Transfer Format with CPHA = 1 82
83 Two-wire Serial Interface 83
84 TWI Bit Rate Register TWI Control Register TWINT: TWI Interrupt Flag TWEA: TWI Enable Acknowledge Bit TWSTA: TWI START Condition Bit TWSTO: TWI STOP Condition Bit TWWC: TWI Write Collision Flag TWEN: TWI Enable Bit TWIE: TWI Interrupt Enable 84
85 TWI Status Register TWS: TWI Status TWPS: TWI Prescaler Bits 85
86 TWI Data Register TWI (Slave) Address Register 86
87 Interfacing the Application to the TWI in a Typical Transmission 87
88 88
89 Status Codes for Master Transmitter Mode 89
90 Formats and States in the Master Transmitter Mode MT 90
91 Status Codes for Master Receiver Mode 91
92 Formats and States in the Master Receiver Mode 92
93 Status Codes for Slave Receiver Mode 93
94 94
95 Formats and States in the Slave Receiver Mode 95
96 Status Codes for Slave Transmitter Mode 96
97 Formats and States in the Slave Transmitter Mode Miscellaneous States 97
98 Possible Status Codes Caused by Arbitration 98
99 Analog Comparator 99
100 Special Function IO Register ACME: Analog Comparator Multiplexer Enable 100
101 Analog Comparator Control and Status Register ACD: Analog Comparator Disable ACBG: Analog Comparator Bandgap Select ACO: Analog Comparator Output ACI: Analog Comparator Interrupt Flag ACIE: Analog Comparator Interrupt Enable ACIC: Analog Comparator Input Capture Enable ACIS1, ACIS0: Analog Comparator Interrupt Mode Select 101
102 ACIS1/ACIS0 Settings 102
103 Analog Comparator Multiplexed Input 103
104 System Clock and Clock Options 104
105 Clock Sources - Device Clocking Options Select 105
106 Crystal Oscillator 106
107 External RC Oscillator 107
108 Calibrated Internal RC Oscillator 108
109 External Clock 109
110 Start-up Times for the Crystal Oscillator Clock Selection 110
111 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection 111
112 Start-up Times for the External RC Oscillator Clock Selection 112
113 Start-up Times for the Internal Calibrated RC Oscillator Clock Selection 113
114 MCU Control Register Power Management and Sleep Modes SM2..0: Sleep Mode Select Bits 2, 1, and 0 SE: Sleep Enable 114
115 Active Clock Domains and Wake Up Sources in the Different Sleep Modes 115
116 System Control and Reset 116
117 Reset Characteristics 117
118 Power-on Reset MCU Start-up, /RESET Tied to VCC 118
119 MCU Start-up, RESET Extended Externally 119
120 External Reset During Operation 120
121 Brown-out Reset During Operation 121
122 Watchdog Reset During Operation 122
123 MCU Control and Status Register JTRF: JTAG Reset Flag WDRF: Watchdog Reset Flag BORF: Brown-out Reset Flag EXTRF: External Reset Flag PORF: Power-on Reset Flag 123
124 Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time 124
125 Watchdog Timer 125
126 Watchdog Timer Control Register WDTOE: Watchdog Turn-off Enable WDE: Watchdog Enable WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 126
127 Watchdog Timer Prescale Select 127
128 Assembly Code Example 128
129 C Code Example 129
130 Fuse Bits Fuse High Byte 130
131 Fuse Low Byte 131
132 Program And Data Memory Lock Bits Lock Bit Byte 132
133 LB Mode 133
134 BLB0 Mode 134
135 BLB1 Mode 135
136 USART 136
137 Clock Generation Logic, Block Diagram 137
138 Parity Bit Calculation 138
139 Equations for Calculating Baud Rate Register Setting 139
140 Synchronous Mode XCK Timing 140
141 USART Initialization (ASM) 141
142 USART Initialization (C) 142
143 Sending Frames with 5 to 8 Data Bit (ASM) Sending Frames with 5 to 8 Data Bit (C) 143
144 Sending Frames with 9 Data Bit (ASM) Sending Frames with 9 Data Bit (C) 144
145 Receiving Frames with 5 to 8 Data Bits (ASM) Receiving Frames with 5 to 8 Data Bits (C) 145
146 Receiving Frames with 9 Databits (ASM) 146
147 Receiving Frames with 9 Databits (C) 147
148 Asynchronous Clock Recovery Asynchronous Data Recovery 148
149 Stop Bit Sampling and Next Start Bit Sampling 149
150 USART I/O Data Register 150
151 USART Control and Status Register A RXC: USART Receive Complete TXC: USART Transmit Complete UDRE: USART Data Register Empty FE: Frame Error DOR: Data OverRun PE: Parity Error U2X: Double the USART Transmission Speed MPCM: Multi-processor Communication Mode 151
152 USART Control and Status Register B RXCIE: RX Complete Interrupt Enable TXCIE: TX Complete Interrupt Enable UDRIE: USART Data Register Empty Interrupt Enable RXEN: Receiver Enable TXEN: Transmitter Enable UCSZ2: Character Size RXB8: Receive Data Bit 8 TXB8: Transmit Data Bit 8 152
153 USART Control and Status Register C URSEL: Register Select UMSEL: USART Mode Select (Asynchronous Operation/Synchronous Operation) UPM1:0: Parity Mode (Enabled, Even Parity / Enabled, Odd Parity) USBS: Stop Bit Select UCSZ1:0: Character Size (5-bit, 6-bit, 7-bit, 8-bit, 9-bit) UCPOL: Clock Polarity 153
154 USART Baud Rate Registers L and H URSEL: Register Select UBRR11:0: USART Baud Rate Register 154
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