8-bit Microcontroller. Application Note. AVR080: ATmega103 Replaced by ATmega128

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1 AVR080: ATmega103 Replaced by ATmega128 Features ATmega103 Errata Corrected in ATmega128 Improvements to Timers and Prescalers Oscillators and Selecting Start-up Delays Improvements to External Memory Interface Improvements to te ADC Improvements to SPI and UART Canges in Programming Interface Added JTAG Interface and On-cip Debug System Features not Available in ATmega103 Compatibility Mode 8-bit Microcontroller Application Note Introduction Te ATmega128 as two operating modes accessed as fuse options. Tis application note is a guide, wic will elp current ATmega103 users convert existing designs to te ATmega128 and gain access to new features contained in tat device. Te ATmega103 compatibility mode is selected wit te M103C fuse setting. In tis mode, te ATmega128 functions as an ATmega103. Wen leaving te M103C fuse unprogrammed, all new features described below are supported. Gaining access to tese features may require some canges to te existing software. Additionally, te electrical caracteristics of te ATmega128 are different including an increase in operating frequency because of a cange in process tecnology. Ceck te dataseet for detailed information. ATmega103 Erratas Corrected in ATmega128 Te following items from te Errata Seet are corrected: Refer to ATmega103 Errata Seet for a more detailed description of te Erratas. Power Consumption During Slowly Rising Supply ATmega128 power consumption is independent of power rising time. UART Looses Syncronization if RXD Line is Low wen UART Receive is Disabled Te UART is replaced wit a USART, wic does not ave tis problem. Te starting edge of a reception is only accepted as valid if te Receive Enable bit in te USART control register is set. Releasing Reset Condition Witout Clock ATmega128 as a new reset interface were an external reset pulse causes an internal reset even toug te condition disappears before any valid clock is present. Rev. 1

2 Wake-up from Power-save Executes Instructions Before Interrupt SPI Can Send Wrong Byte Incorrect Clearing of XTRF in MCUSR Reset During EEPROM Write SPI Interrupt Flag can be Undefined after Reset Skip Instruction wit Interrupts Read Back Value During EEPROM Polling MISO Output During In- System Programming Te ADC as No Free-running Mode ATmega128 executes te Interrupt routine as te first instruction after wake-up from Power-save mode. If an enabled interrupt occurs wile te ATmega128 is in a sleep mode, te MCU wakes up. Te MCU is ten alted for four cycles, executes te interrupt routine, and resumes execution from te instruction following SLEEP. In ATmega128, tere is no need to wait for te previous transfer to complete before writing te next byte into te SPI Data Register wen operating in Master mode. Te POR and XTRF flag can be cleared individually in ATmega128. If a Reset or Power-off occurs during an EEPROM write, te current location may be incorrect, but ATmega128 will not corrupt any oter locations tan te one being written. ATmega128 resets te SPI interrupt flag to zero (0). ATmega128 interrupts always store te correct return address, also wen interrupting a skip instruction skipping a two-word instruction. In ATmega128, te Read Back Value during EEPROM polling is always $FF. ATmega128 tri-states te MISO Output during In-System Programming. Te In-System Programming interface is still using PE0 and PE1 for serial data in and serial data out, respectively. Te ATmega128 supports Free-running mode. 2 AVR080

3 AVR080 Improvements to Timer/Counters and Prescalers Differences Between ATmega128 and ATmega103 For details about te improved and additional features, please refer to te dataseet. Te following features ave been added: Te Prescalers in ATmega128 can be reset. Variable top value in PWM mode. Pase and Frequency correct PWM mode in addition to te Pase correct PWM mode. Overflow PWM mode. Most of te improvements and canges apply to all te Timer/Counters and te description below is written in a general form. A lower case x replaces te output cannel (A or B for Timer/Counter1, N/A for Timer/Counter0 and Timer/Counter2), wile n replaces te Timer/Counter number (n = 0, 1, or 2). TCNT1 Cleared in PWM Mode In ATmega103 tere are 3 different PWM resolutions - 8, 9, or 10 bits. Toug only 8, 9, or 10 bits are compared, it is still possible to write values into te TCNT1 register tat exceed te resolution. Tus, te Timer/Counter as to complete te count to 0xffff before te reduced resolution becomes effective (i.e, if 8-bit resolution is selected and te TCNT1 register contains 0x0100, te top value (0x00ff) will not be effective until te counter as counted up to 0xffff, turned, and counted down to 0x0000 again). In ATmega128 tis as been canged so tat te unused bits in TCNT1 are being cleared to zero to avoid tis unintended counting up to 0xFFFF. In te ATmega128, te TCNT1 register never exceeds te selected resolution. OCR1xH Cleared in PWM Mode Te most significant bits in te TCNT1 register will be cleared at te first positive edge of te prescaled clock. 8-bit PWM: TCNT1H[7:0] = 0 9-bit PWM: TCNT1H[7:1] = 0 10-bit PWM: TCNT1H[7:2] = 0 TCNT1H not cleared. Clearing OCR1xH in PWM mode is sligtly different from clearing TCNT1. Te ATmega103 clears te most significant bits if 8, 9, or 10 bits PWM mode is selected, but only te 6 most significant bits. Tus, if 0xffff is written to OCR1x in PWM-mode and read OCR1x back, 0x03ff is read regardless of wic PWM mode tat is selected. In ATmega128 te number of cleared bits depends on te resolution. Te most significant bits in OCR1AH and OCR1BH are cleared wen tey are updated at te TOP-value of te counter. 8-bit PWM: OCR1xH[7:0] = 0 9-bit PWM: OCR1xH[7:1] = 0 10-bit PWM: OCR1xH[7:2] = 0 Te six most significant bits in te OCR1AH and OCR1BH are cleared regardless of te resolution. 3

4 Clear Timer/Counter on Compare Matc wit Prescaler (Applies to all Timer/Counters) Te relation between a Clear on Compare matc and te internal counting of te Timer/Counter as been canged. Te Clear on Compare matc in te ATmega103 clears te Timer/Counter after te first internal count matcing te compare value, wereas te ATmega128 clears after te last internal count matcing te compare value. See Figure 1 and Figure 2 for details on clearing, flag setting, and pin cange. Example: OCRnx = 0x02 wen prescaler is enabled (divide clock by 8). Figure 1. Setting Compare Flag/Pin for ATmega128 (1) TCNTn Pin/Flag Note: 1. Indicates were te Compare flag/pin will be set. Figure 2. Setting Compare Flag/Pin for ATmega103 (1) TCNTn Pin/Flag Note: 1. Indicates were te Compare flag/pin will be set. Setting of Output Compare Pin/Flag wit Prescaler Enabled (Applies to all Timer/Counters) Te relation between an Output Compare and te internal counting of te Timer/Counter as been canged. Output Compare in te ATmega103 sets te Output Compare pin/flag after te first internal count matcing te compare value, wereas te ATmega128 sets te Output Compare pin/flag after te last internal count matcing te compare value. See Figure 3 and Figure 4 for details on Output Compare flag setting and pin cange. Example: OCRnx = 0x02, prescaler enabled (divide clock by 8) Figure 3. Setting Compare Flag/Pin for ATmega128 (1) TCNTn Pin/Flag Note: 1. Indicates were te Compare flag/pin will be set. Figure 4. Setting Compare Flag/Pin for ATmega103 (1) TCNTn Pin/Flag Note: 1. Indicates were te Compare flag/pin will be set. 4 AVR080

5 AVR080 Write to OCR1x in PWM Mode, Cange to Normal Mode Before OCR1x is Updated at te Top, Read OCR1x (Applies to 16-Bit Timer/Counter Only) As described in te dataseet, te OCR1x registers are updated at te top value wen written. Tus, wen writing te OCR1x in PWM mode, te value is buffered in a temporary register wic is latced until te Timer/Counter reaces te top. If PWM mode is left after te temporary register is written, but before te real Output Compare registers are updated, te beavior differs between ATmega128 and ATmega103. If te OCR1x register is read before te update is done, te actual compare value is read not te OCR1x buffer. If te OCR1x register is read before te update is done, te value in te OCR1x buffer is read. For example, te value read is te one last written (to te OCR1x buffer), but since te Timer/Counter never reaced te top value, it was not latced into te OCR1x register. Tus te value tat is used for comparisson is not necessarily te same as being read. Note: Tis applies to 16 bits Timer/Counter only, for 8 bits Timer/Counter, te temporary register value is read for bot devices. Remember old OCx-pin Level OCR0 or OCR2 Equal Extreme Value in TCNT0 or TCNT2 Respectively (Applies to 8-bit Timer/Counter Only) Oscillators and Selecting Start-up Delays If COM1x1 and COM1x0 canges from "01" to "00" and a compare matc occurs wen te COM1x1:COM1x0 value is "00": Te level of te OCx-pin before disabling te Output Compare mode is remembered. Re-enabling te Output Compare mode will cause te OCx-pin to resume operation from te state it ad wen it was disabled. All Output Compare pins are initialized to zero on Reset. OCx is cleared for 16 bits Timer/Counter. For 8 bits Timer/Counter, te state of te Output Compare pin is unknown wen re-enabling te Output Compare. Only te 8-bit Timer/Counters in te ATmega103 are initialized to zero on Reset. According to te values in COMn1 and COMn0, OCn will be cleared or set wen canging te COMn bits. Te response on te output differs from ATmega128 to Wen canging COMn bits setting, te output pin (OCn) canges accordingly to te COMn bits after a compare matc as occurred. Wen canging COMn bits setting, te output pin (OCn) canges immediately. For te 16 bits Timer/Counter1, neiter ATmega128 nor ATmega103 cange te output before a compare matc occurs. ATmega128 provides more oscillators and start-up time selections tan ATmega103. In, te start-up delays from Power-down mode and Power-save mode depend on te CPU clock frequency. During Wake-up from Power-down mode and Power-save mode, te ATmega128 uses te CPU frequency to determine te Wake-up delay, wile ATmega103 determines te delay from te WDT oscillator frequency (except SUT = 00). Follow te guidelines from te section System Clock and Clock Options in te ATmega128 dataseet to find appropriate start-up values. 5

6 Special attention must be payed wen canging te fuses in In-System Programming mode. In-System Programming is dependent on a sysem clock. If wrong oscillator setting is programmed, it may be impossible to re-enter In-System Programming mode due to missing system clock (parallel programming mode must ten be used). Improvements to External Memory Interface Improvements to ADC Improvements to SPI and USART Canges in EEPROM Write Timing Programming Interface Te combined Address/Data port in ATmega128 outputs Data until a new address is set up. Refer to te ATmega128 Dataseet for details on te canged timing. Te ADC in ATmega128 supports Free-running mode. To improve accuracy, a single conversion now takes one additional cycle. ATmega128 supports bot left adjusted and rigt adjusted 10-bit results. Te ADC in ATmega128 supports differential and amplified measurements. Bot SPI and USART ave new double-speed modes wic allow iger communication speed. Te UART in ATmega103 as been replaced by a USART in ATmega128. Te ATmega128 USART is compatible wit te ATmega103 UART wit one exception. Te two-buffer receive register acts like a FIFO and te following must be kept in mind: Te UDR must only be read once for eac incoming data, if reading more tan once, te next level of FIFO will be read. Te error flags (FE and DOR) and te 9t data bit (RXB8) are buffered wit te data in te receive buffer. Terefore te status bits must always be read before te UDR register is read. Oterwise, te error status will be lost. In ATmega103, te EEPROM write time is dependent on voltage, typically 2.5 V CC = 5V and 4 V CC = 2.7V. In ATmega128, te EEPROM write time is 8.2 ms regardless of V CC. Some canges ave been done to te programming interface, especially in te In-System Programming interface. Tis as been done to support all te additional fuses in ATmega128. Te timing requirements are uncanged. See te ATmega128 dataseet for details. Te parallel programming algoritm is canged. Te most significant cange is tat te PAGEL pin on ATmega128 is located on PD7, wile BS2 is located on PA0. On ATmega103 te opposite pin-mapping was cosen (PAGEL pin on PA0, wile BS2 was mapped to PD7). Tis cange as been done to make it possible to use te same programmer for all new AVR devices. In parallel mode, te ATmega128 supports page programming of te EEPROM. Note tat te additional fuses and lock-bits also require a cange in te fuse writing algoritm. Te timing requirements for parallel programming ave been canged. See te ATmega128 dataseet for details. Te STK500 supports bot In-System Programming and parallel programming of te ATmega AVR080

7 AVR080 JTAG Interface and On-cip Debug System Te ATmega128 provides a JTAG interface, wic can be used for programming, boundary-scan, and On-cip debug. Refer to dataseet for details. Note tat te JTAG interface is also available in ATmega103 compatibility mode. Oter Differences Signature Byte Verifying te EEPROM at Hig Voltages During Programming Verifying EEPROM In-System Serial Programming at Voltages Below 3.4V Te ATmega128 as a Signature Byte different from te one used in ATmega103. Tere are no restrictions on te supply voltage or system frequency as long as operated inside te voltage and frequency range prescribed in te dataseet for te ATmega128. Tere are no restrictions on te supply voltage or system frequency as long as te device is operated inside te voltage and frequency range prescribed in te dataseet for te ATmega128. Tere are no restrictions on te supply voltage or system frequency as long as te device is operated inside te voltage and frequency range prescribed in te dataseet for te ATmega128. 7

8 Features not Available in ATmega103 Compatibility Mode Te compatibility fuse makes te ATmega128 compatible to ATmega103. But wit te compatibility fused programmed, some of te new features in ATmega128 become unavailable. Te following features are not supported wen te ATmega128 is used in te ATmega103 compatibility mode: TWI - Two Wire Interface module. USART1 - Te additional second USART. Prescaler Reset on Timer/Counters. Boot Loader Capabilities (SPM - Self Programming Memories). Advanced External Memory Control (more wait-states, configurable number of bits are assigned to address ig byte, different wait-states settings for different pages of external memory). Additional Output Compare register (OCR1C) for Timer/Counter1. Timer/Counter3 (16-bit Timer/Counter identical to Timer/Counter1). PortC is general I/O (digital output only in ATmega103). PortF is general I/O (analog/digital input only in ATmega103). PortG (alternate functions only in ATmega103). If any of te features above are needed or wanted and te compatibility fuse is left unprogrammed, tis introduces several differences between ATmega128 and ATmega103 wic do not exist as long as te compatibility fuse is programmed: Address space 0x0060-0x00FF is dedicated extended I/O, not internal SRAM. Address space 0x0100-0x10FF is dedicated internal SRAM (ATmega128 supports 4096 locations of internal SRAM compared to 4000 in ATmega103), tus te external memory starts at address 0x1100 (external memory on ATmega103 starts at address 0x1000). PortC is not initialized upon reset to drive 0x00, but it is tri-stated as all oter ports. Te ALE, RD, and WR pins (PG2:0) are not configured as output until te XRAM is enabled. Te TOSC1 and TOSC2 (PG4:3) pins are configured as digital input pins after reset, not 32 khz oscillator unless AS0 bit is written. A timed sequence must be followed to cange Watcdog Timer prescaler settings by software. In te MCUCSR register, all RESET flags are present in te register, not only EXTRF and PORF as in ATmega103. Te UART will ave an extra input buffer wic allows one more data byte to be received before te data overrun flag (DOR) is set. 8 AVR080

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8-bit Microcontroller. Application Note. AVR085: Replacing AT90S8515 by ATmega8515. Features. Introduction. AT90S8515 Errata Corrected in ATmega8515

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