Microcomputers. Digital Signal Processing

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1 Microcomputers Analog-to-Digital and Digital-to-Analog Conversion Lecture 7-1 Digital Signal Processing Analog-to-Digital Converter (ADC) converts an input analog value to an output digital representation. This digital data is processed by a microprocessor and output to a Digital-to-Analog Converter (DAC) the converts an input binary value to an output voltage. Lecture 7-2 1

2 Vocabulary ADC (Analog-to-Digital Converter) converts an analog signal (voltage/current) to a digital value DAC (Digital-to-Analog Converter) converts a digital value to an analog value (voltage/current) Sample period for ADC, time between each conversion Typically, samples are taken at a fixed rate Vref (Reference Voltage) analog signal varies between 0 and Vref, or between +/- Vref Resolution number of bits used for conversion (8 bits, 10 bits, 12 bits, 16 bits, etc). Conversion Time the time it takes for a analog-to-digital conversion Lecture 7-3 An N-bit ADC Vref Maps a voltage (Vin) to a digital code ADC_code 2 N -1 Vin ADC_code [0 to 2 N -1] ADC_code = (Vin/Vref) x 2 N 0 V Vin is always considered less than Vref, so Vin/Vref is always < 1.0. Any fractional part of the code is truncated. 0 Lecture 7-4 2

3 Example: A 10-bit ADC Vref = 4 V Maps a voltage (Vin) to a digital code ADC_code 1023 Vin = 3.0 V ADC_code = V ADC_code = (Vin/Vref) x 2 N = (3 V/4 V) x 1024 = 0.75 x 1024 = Lecture 7-5 Going from Code to Voltage Vref = 4.0 V ADC_code = (Vin/Vref) x 2 N ADC_code/2 N x Vref = Vin 1023 Vin = V ADC_code = 555 Vin = ADC_code/2 N x Vref = 555/1024 x 4 V 0 V = = ~ Lecture 7-6 3

4 ADC Resolution For an N-bit ADC, the smallest input voltage that can be resolved is 1 LSb, or: 1/2 N * (Vref+ - Vref-) Where Vref+ is the positive reference voltage and Vref- is the negative reference voltage. We will use Vref- = 0 V, and refer to Vref+ as simply Vref, so this simplifies to 1/2 N * Vref For Vref = 4 V, and N = 4, what is 1 LSb? 1/2 4 * 4 V = 1/16 * 4 V = 0.25 V Lecture 7-7 Example: 10-bit ADC Resolution Vref = 4.0 V 1023 Vin = ADC_code = 769 V Vin = 3.0 V ADC_code = LSB voltage = 1/2 N x Vref = 1/1024 x 4 V 0 V = V = ~ 3.9 mv 0 Lecture 7-8 4

5 ADC, DAC Equations ADC: Vin = input voltage, Vref+ = reference voltage, Vref- = 0 V. N = number of bits of precision Vref Vin/ Vref * 2 N = output_code output_code/ 2 N * Vref = Vin 1 LSB = Vref/2 N Vin ADC output code N DAC: Vout = output voltage, Vref = reference voltage, Vref N = number of bits of precision Vout/ Vref * 2 N = input_code input_code/ 2 N * Vref = Vout 1 LSB = Vref/2 N input code N DAC Vout Lecture 7-9 Sample ADC, DAC Computations If Vref = 5V, and a 10-bit A/D output code is 0x12A, what is the ADC input voltage? Vin = output_code/2 N * Vref = (0x12A)/2 10 * 5 V = 298/1024 * 5 V = 1.46 V (ADC Vin) If Vref = 5V, and an 8-bit DAC input code is 0xA9, what is the DAC output voltage? Vout = input_code/2 N * Vref = (0xA9)/2 8 * 5 V = 169/256 * 5 V = 3.3 V (DAC Vout) If Vref = 4V, and an 8-bit A/D input voltage is 2.35 V, what is the ADC output code? output code = Vin/ Vref * 2 N = 2.35 V/ 4 V * 2 8 =.5875 * 256 = = 150 = 0x96 (ADC output code) Lecture

6 Digital-to-Analog Conversion For a particular binary code, output a voltage between 0 and Vref Vref D[7:0] Vout DAC Assume a DAC that uses an unsigned binary input code, with 0 < Vout < Vref. Then D = Vout = 0V D = Vout = Vref(1/256 ) (one LSB) D = Vout = Vref(2/256)... D = Vout = Vref(255/256) (full scale) Lecture 7-11 DAC Output Plot Vout Output signal increases in 1 LSB increments. 4/256 Vref 3/256 Vref 2/256 Vref 1/256 Vref Input code Lecture

7 An N-bit DAC 2 N -1 Maps a digital code (DAC_code) to a voltage (Vout) Vref DAC_code Vout Vout = DAC_code/2 N x Vref 0 0 V Lecture 7-13 A 1-bit ADC Vref analog signal Vdd R Vref/2 Vin + - Vout=Vdd if Vin > Vref/2 Vout=0 if Vin < Vref/2 R digital signal comparator Lecture

8 Counter Ramp ADC Control logic use a counter to apply successive codes 0,1,2,3,4... to DAC (Digital-to-Analog Converter) until DAC output is greater than Vin. This is SLOW, and have to allocate the worst case time for each conversion, which is 2 N clock cycles for an N-bit ADC. Lecture 7-15 Successive Approximation ADC Initially set VDAC to ½ Vref, then see if Vin higher or lower than VDAC. If > ½ Vref, then next guess is between Vref and ½ Vref, else next guess is between ½ Vref and GND. Do this for each bit of the ADC. Takes N clock cycles. Lecture

9 Successive Approximation Example Given a 4-bit Successive Approximation ADC, and Vref = 4 V. Let Vin = V. Clear DAC input to 0b First guess, DAC input = 0b1000 = 8, so Vdac = 8/2 4 * 4 V = 8/16 * 4 V = 2 V. Vdac (2 V) < Vin ( V), so guess of 1 for MSb of DAC was correct. 2. Set next bit of DAC to 1, DAC input = 0b1100 = 12, so Vdac = 12/16*4= 3V. Vdac (3 V) < Vin ( V), so guess of 1 for bit2 of DAC was correct. 3. Set next bit of DAC to 1, DAC input = 0b1110 = 14, so Vdac = 14/16*4= 3.5V. Vdac (3.5 V) > Vin ( V), so guess of 1 for bit1 of DAC was incorrect. Reset this bit to Set last bit of DAC to 1, DAC input = 0b1101 = 13, so Vdac = 13/16*4 = 3.25V. Vdac (3.25 V) > Vin ( V), so guess of 1 for bit0 of DAC was incorrect. Reset this bit to 0. Final ADC output code is 0b1100. Check result: output code = Vin/Vref * 2 N = /4 * 16 = = 12 (truncated). Lecture 7-17 A 2-bit Flash ADC R R R R Vin + - 3/4Vref Vin + - 1/2Vref Vin + - 1/4Vref A B C A B C D1 D (other codes don t cares) D[1:0] Fast, conversion time is settling time of comparators and digital logic. Encoding logic Lecture

10 A 3-bit Flash ADC Lecture 7-19 ADC Architecture Summary Flash ADCs Fastest possible conversion time Requires the most transistors of any architecture N-bit converter requires 2 N -1 comparators. Commercially available flash converters up to 12 bits. Conversion done in one clock cycle Successive approximation ADCs Use only one comparator Take one clock cycle per bit High precision (16-bit converters are available) Lecture

11 Commercial ADCs Key timing parameter is conversion time how long does it take to produce a digital output once a conversion is started Up to 16-bit ADCs available Separated into fast/medium/low speed families Serial interfaces common on medium/low speed ADCs For high-precision ADCs, challenge is keeping system noise from affecting conversion Assume a 16-bit DAC, and a 4.1V reference, then 1 LSB = 4.1/2 16 = 62 V. Lecture 7-21 Flash DAC Eliminates large capacitive load at one node. Large capacitive load N-bit DAC requires 2 N resistors! Lecture

12 R-2R Ladder DAC Resistor ladder divides the Vref voltage to a binary weighted value 4- bit value, with the 4-bits equal to X3 X2 X1 X0 If the switch Xn is connected to Vref, then that bit value is 1, if the switch Xn is not connected to Vref, then that bit value is 0. Majority of DACs use this architecture as requires far less resistors than flash DACs. Lecture 7-23 Sample DAC Computations If Vref = 5V, and the 8-bit input code is 0x8A, what is the DAC output voltage? input_code/2 N * Vref = (0x8A)/2 8 * 5 V = 138/256 * 5 V = 2.70 V (Vout) If Vref = 4V, and the DAC output voltage is 1.25 V, what is the 8-bit input code? Vout/ Vref * 2 N = 1.25 V/4 V * 2 8 = * 256 = 80 = 0x50 (input_code) Lecture

13 Commercial DACs Either voltage or current DACs Current DACs require an external operational amplifier to convert to voltage Precision up to 16 bits Key timing parameter is settling time - amount of time it takes to produce a stable output voltage once the input code has changed We will use an 8-bit voltage DAC with a SPI interface from Maxim semiconductor Lecture 7-25 PIC24 ADC The PIC24 C has an onboard ADC Successive approximation 10-bit (default) or 12-bit resolution Reference voltage can be Vdd or separate voltage (min AVSS V) Multiple input (more than one input channel) Clock source for ADC is either a divided Fosc, or an internally generated clock. The ADC clock period (Tad) cannot be less than 76 ns for 10-bit mode, or 118 ns for 12-bit mode. The internally generated clock has a period of ~ 250 ns (~ 4 MHz). Lecture

14 PIC24 ADC Block Diagram Note that different ANx inputs are mapped to different Channels, so have to select both a Channel and an ANx input. Lecture 7-27 Conversion Time Total conversion time is sampling time + conversion time Sampling looks at the input voltage and uses a storage capacitor to acquire the input. This time is configurable; we will use a conservative 31 Tad periods which is the maximum for the PIC24. Conversion time is Number of bits + 31 Tad periods. So, for these settings, takes 31 (sampling) + 12 (bits) + 2 = 45 clock periods. Using the internal clock (250 ns), one conversion takes about µs (88.9 khz). Lecture

16 Configuring the ADC (cont.) Configures for internal ADC clock, uses manual sample start/auto conversion u16_ch0positivemask selects the ANx input from Channel 0 to convert Uses AVDD, AVSS as references Parameter u8_autosampletime sets the number of sample clocks u8_use12bits determines if 12-bit or 10-bit conversion is done Lecture 7-31 Starting a Conversion, Getting result: uint16_t convertadc1(void) { uint8_t u8_wdtstate; sz_lasttimeouterror = "convertadc1()"; u8_wdtstate = _SWDTEN; // save WDT state _SWDTEN = 1; // enable WDT since we block SET_SAMP_BIT_ADC1(); // start sampling NOP(); // takes one clock to clear previous // DONE flag, delay before checking. WAIT_UNTIL_CONVERSION_COMPLETE_ADC1(); // wait for conversion to finish _SWDTEN = u8_wdtstate; // restore WDT sz_lasttimeouterror = NULL; // reset error message return(adc1buf0); } In this mode, tell ADC to start sampling, after sampling is done the ADC conversion is started A status bit is set when the conversion is finished Lecture

17 MAXIM 548 DAC SPI interface DAC output R/2R DAC Lecture 7-33 Max548A SPI Command Format First Byte: DAC command byte Second Byte: Command data Command byte to do conversion: 0x09 (0b ) Data is the value to convert. Lecture

18 Function for doing a DAC conversion #define CONFIG_SLAVE_ENABLE() CONFIG_RB3_AS_DIG_OUTPUT() #define SLAVE_ENABLE() _LATB3 = 0 // low true assertion #define SLAVE_DISABLE() _LATB3 = 1 void writedac (uint8_t dacval) { SLAVE_ENABLE(); // assert Chipselect line to DAC iomasterspi1(0b ); // control byte that enables DAC A iomasterspi1(dacval); // write DAC value SLAVE_DISABLE(); } Lecture 7-35 Testing the ADC and DAC Read the voltage from the potentiometer via the PIC24 ADC, write this digital value to the DAC The DAC output voltage should match the potentiometer voltage The MAX548 is an 8-bit DAC with a SPI port 3.3 V MAX V PIC24HJ32GP202 VDD OUTA LDAC# AN0 RB3 CS# GND SDO1 (RP6) DIN SCK1 (RP7) SCLK DAC Output Potentiometer has three pins - middle pin is the wiper, connect the end pins to Vdd/Gnd (ordering does not matter). Lecture

19 Potentiometer Vdd A variable resistor. Tie outer two legs to Vdd/GND. Voltage on middle leg will vary between Vdd/GND as potentiometer is adjusted, changing the position of the wiper on the resistor. Lecture 7-37 adc_spidac_test.c void configdac() { CONFIG_SLAVE_ENABLE(); SLAVE_DISABLE(); } // chip select for DAC // disable the chip select int main (void) { uint16_t u16_adcval; uint8_t u8_dacval; float f_adcval; float f_dacval; configbasic(hello_msg); CONFIG_AN0_AS_ANALOG(); configadc1_manualch0(adc_ch0_pos_samplea_an0, 31, 1); configspi1(); configdac(); Use input AN0 on Channel 0 as ADC input Support function, configures for manual sampling, auto conversion Number of sampling periods, 31 Value of 1 selects 12-bit mode, 0 selects 10-bit mode. Lecture

21 What do you have to know? Vocabulary DAC R/2R architecture ADC Flash, Successive approximation architectures PIC24 ADC How to configure Acquisition, Conversion time How to start do conversion, read result MAX548A DAC usage Lecture

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