1. R-2R ladder Digital-Analog Converters (DAC). Connect the DAC boards (2 channels) and Nexys 4 board according to Fig. 1.

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1 Analog-Digital and Digital-Analog Converters Digital Electronics Labolatory Ernest Jamro, Maciej Wielgosz, Piotr Rzeszut Dep. of Electronics, AGH-UST, Kraków Poland, R-2R ladder Digital-Analog Converters (DAC). Connect the DAC boards (2 channels) and Nexys 4 board according to Fig. 1. Fig. 1. The DAC and Nexys 4 boards connection. Actual mode of operation and parameters of the application are presented on the 7-segment display. You can control the application using 5 push-buttons: Up, Downt, Right BTNR, Left BTNL, Centre BTNC). Functions of the buttons and meaning of symbols presented on displays are described below introducing each application. If you hold each button longer, the value changes faster.

2 1.1. Quantization Connect the DAC outputs with a oscilloscope and configure FPGA chip with file: C:/TC/AC_CA/TC_01.bit (if the file does not exist, please download and unzip the attachment in the specified location). This FPGA configuration stimulates the DAC with sine and saw-tooth waveform with frequency equal to 100Hz and different resolution on CH2. On CH1 the bit resolution is constant and equals 7-bit. Display waveform: SIN/SAW Resolution in bits: 7 1 Increase number of bits Change waveform Decrease number of bits Observe oscilloscope waveform for Ch1, Ch2 and quantization error (Ch2 - Ch1 use MATH button, Operation: ) for different bit resolution and sawtooth and sine waveforms. Measure the 1 LSB (Least Significant Bit) value for different resolutions. Is the quantization error limited by 1 LSB? Bit LSB Formula for: 1 LSB:... The main source of distortions is quantization. For which resolution distortions are difficult to be observed on the oscilloscope? Set sine waveform with 3-bit resolution. Then, set FFT mode on the oscilloscope by pressing Menu MATH and then changing operation to FFT, Source: CH2. Fast Fourier Transform (FFT) mode means that X-axis represents frequency and Y-axis represents amplitude in db. Set X-axis resolution to 50Hz/div. Estimate roughly the distance between 100Hz signal amplitude and the next largest (noise) amplitude in db. Then change DAC resolution to 5 and then to 6-bit and determine roughly the distance between the signal and quantization noise amplitudes. Determine the relationship between resolution and Signal to Noise Ratio (SNR). Note 1: Correct calculation of SNR requires a proper sum of every noise (harmonic) amplitudes, nevertheless for the rough noise (harmonic) estimation only the largest noise amplitude is taken into account. Note 2: DC-component should be disregarded. Bit SNR Formula for SNR:..

3 2. Errors Configure the FPGA with the file, TC_02.bit, which generates sawtooth waveform. Observe obtained oscilloscope waveforms for different error settings. In order to obtain more stable waveforms set trigger mode to falling slope. Compare the obtained oscilloscope waveforms. Define the error types. CH2 signal is always ideal reference signal. Set the same level of zeros of CH1 and CH2 on the oscilloscope, so the waveforms should overlay. Display Error code Error change Error change Error code A0 Error description A1 A2 A3 b0 b1 b2 b3

4 3. Digital Analog Sigma-Delta and Pulse Width Modulator (PWM) Configure the FPGA with file: TC_03.bit. On channel CH1 sigma-delta and on channel CH2 PWM DAC converters outputs are obtained. Trigger the oscilloscope with the PWM channel. Display Constant input value for DAC Sampling frequency [Hz] in scientific notation (ex. 3.05E3 = 3.05*10 3 Hz) / Symbol of saw tooth waveform Increase input value for DAC Increase frequency Switch between constant Decrease frequency input value and saw tooth generation Decrease input value for DAC For lowest frequency (approx. 3kHz) compare obtained waveforms for the PWM and sigmadelta DAC for different input data equal to: 1, 2, 3, 4, 8, 14. Record waveforms for a selected input data. Describe the difference between the PWM and sigma-delta. Increase the frequency (6.25MHz or 12.5 MHz) so that almost DC signal is obtained (a parasitic low-pass filter filters the signal). Observe the difference between PWM and sigmadelta output, and different digital input values. The difference is the lager for input value equal to 8 (midrange). Explain the obtained result. Change setting to internal generation of saw-tooth signal inside FPGA (press BTNC). In order to obtain a stable oscilloscope view use Run/Stop button on the oscilloscope. Change the freq. to e.g. 25 MHz (button BTNL). Change oscilloscope time base to observe 16 PWM cycles. Then lower the frequency to e.g. 3 MHz and enlarge time base to zoom in to the obtained waveforms for different digital input values.

5 4. ADC converters In this chapter the following converters are tested:: 1. Ramp compare 2. Tracking 3. SAR (Successive Approximation Register) Configure FPGA chip using TC_05.bit file. CH1 channel is output of the programmable waveform generator i.e. analog input to the ADC. Using push-buttons and SW0 switch it can be configured to provide constant value in range of 0-3.3V (power supply voltage) with 8-bit resolution. In order to properly trigger the oscilloscope for constant value (not sine or sawtooth waveform) a 3.3 V spike is added to this channel. Also by setting SW0 to 1 (right bottom corner of the board), generation of sine or saw tooth waveform can be enabled. The frequency of the waveform is displayed. CH2 channel is output of the 4-bit DAC, that is a part of the ADC converter. CH1 and CH2 could have been connected to differential input of the FPGA chip, which would have operated as a comparator, but in order to reduce number of external connections digital comparator inside FPGA chip is being used. The application demonstrates operation of the three types of ADC mentioned above. They are being clocked using 5kHz signal (please note this is not sampling frequency, but clock frequency for each ADC).

6 Display ADC type Generator oputput vlaue Generator waveform Waveform frequency [Hz] in scientific notation (np. 3.05E3 = 3.05*10 3 Hz) Increase generator output value Change waveform (Sin/Saw.) Decrease waveform Change ADC type Increase waveform frequency frequency SW0 (right bottom corner) Decrease generator output value Change waveform (Sin/Saw.) 1 Sin/Saw. generator 0 constant output value A) Set generation of sawtooth waveform at 10Hz, select A, b and C ADC and each time observe CH2 waveform on oscilloscope. Trigger the oscilloscope using CH1. If necessary use RUN/STOP button. Determine type of the ADC for each letter-code. A b C ADC code ADC type B) Set a few constant values (ex. 10 (0x0A), 128 (0x80), 255 (0xFF) and observe vaweforms for each type of ADC. Save some waveforms. What can you say about conversion time for each ADC type? C) Set generation of sawtooth waveform at 10 Hz. Trigger oscilloscope using falling slope of generator signal (CH1). How different types of ADCs react at this slope? (Optional) For each ADC increase generator frequency. What can you observe? At which frequency each ADC is no longer working properly? (Optional) Set type A ADC, generate sine at 5kHz. Turn off visibility of CH1. Trigger using CH2. What can you see on CH2? What is the frequency of CH2 waveform (measure using cursors in STOP mode when having problems with triggering)? How do we call this phenomenon?

7 5. Design exercised After the above laboratory tasks have been accomplished mark 3.0 is guaranteed. One of the selected (by the tutor) design exercised may be further designed. In the design any library module can be employed, e.g. adder, counter, Mark 4.0 1) design digital transponder employed in the 3-bit FLASH ADC. Comparators outputs can be set by SW switches, digital DAC outputs (3 bit bus) are indicated by LED. 2) Design PWM DAC. Output digital 1-bit data should be fed to B18 FPGA pin. The voltage waveform of this pin can be observed on the oscilloscope. 3) Employing the binary weighted or R-2R ladder DAC generate one form the follows: a) sawtooth, b) triangle waveforms. 4) Design tracking ADC. Mark 5.0 5) Design sigma-delta DAC, bit resolution is defined by the tutor. Input value is defined by SW switches. 6) Employing ready-to-use Look-Up-Table with the sine function (file rom_sin.vhd) design a sine waveform generator employing the binary weighted or R-2R ladder DAC (simulation only). 7) Design SAR ADC.