Analog Digital Converter

Transcription

1 Analog Digital Converter - Overview Analog Digital Conversion - Operation Modes: Single Mode vs. Scan mode - Registers for Data, Control, Status - Using the ADC in Software - Handling of Interrupts Karl-Ragmar Riemschneider Processor Systems 1

2 Analog Signals and Internal Representation Processor Systems 2

3 Analog to Digital Conversion - Function of Two Dimensions! Processor Systems 3

4 Digital to Analog Conversion - Function of Two Dimensions! Processor Systems 4

5 Analog to Digital Conversion - Quantization in Two Dimensions Processor Systems 5

6 Digital to Analog Conversion - "staircase" effect Processor Systems 6

7 Typical Solution: Equidistant Steps in Time and Voltage Discreet Approximation of Analog Value with Quantization Errors Processor Systems 7

8 H8S/ A/D Converter Features 10-bit resolution - successive approximation method eight input channels - analog multiplexer reference voltage (Vref) pin to define the voltage range minimum conversion time: 6.7 µs per channel at 20 MHz system clock single mode: Single-channel A/D conversion 7.27 µs per channel at MHz system clock scan mode: continuous A/D conversion of a group channels (1 to 4 channels) conversion results are held in four 16-bit data registers - one register for one channel available integrated sample and hold function conversion start events: 1) software or 2) timer conversion start trigger (TPU or 8-bit timer) 3) an external signal (A/D trigger signal) on the ADTRG pin A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion Processor Systems 8

9 Block Diagram of the A/D Converter Processor Systems 9

10 Programmers Point of View Processor Systems 10

11 A/D Converter Registers Processor Systems 11

12 Accessing A/D Conversion Result Data Step 1: read sequences 10 bit resolution: Value 1: Step1, Step 2, - combine both to a 16 bit value in SW Value 2: Step1, Step 2, - combine both to a 16 bit value in SW... Step 2: or short read sequence 8 bit resolution (least significant two bits ignored) Value 1: Step1 use as 8 bit value in SW Value 2: Step1 use as 8 bit value in SW Processor Systems 12

13 A/D Converter Data Registers High/Low (ADDRxH, ADDRxL) ADC result (10 bit resolution) (fixed) Value (16 bit) for further processing Value (10 bit) => Quantization steps of 64 in terms of binary numbers Processor Systems 13

14 Example of use ADDRxH/ADDRxL #include <mpp1.h> /* delivers ADDRAH, ADDRAL macros */ void main(void){ unsigned short an0; an0 = ADDRAH << 2; /* Step1 : Read ADDRAH in lower 8 bits of a short and shift up 2, copy result short variable an0 */ an0 = ADDRAL >> 6; /* Step 2: Read now ADDRAL (from temp), shift it bit 6 down = shift out all zeros set lowest 2 bits with bitwise "or" in the variable an0, let all other bits unchanged */ Processor Systems 14

15 A/D Converter Operation Modes Operation Modes of the Analog Digital Converter Single Mode Scan Mode One channel + One conversion only Select with SCAN Bit = 0 *) ADST Bit = 1 starts ONE conversion ( clears automatically) On completion Flag ADF is set to 1 ( clearing by SW, not automatically) *) in A/D Control/Status Register ADSCR one group of channels (group = 1 channel min. to 4 channels max.) continuous conversion Select with SCAN Bit = 1 *) ADST Bit = 1 starts conversions ( not cleared automatically) ADST Bit = 0 stops conversions completion of the group the flag ADF is set to 1 ( clearing by SW, not automatically) *) in A/D Control/Status Register ADSCR Processor Systems 15

16 Fixed Correspondence of Analog Input Pins (ANx) and ADC Data Registers Pair (ADDRnH/ADDRnL) Processor Systems 16

17 ADC Status/Control Register ADSCR - Single Mode only Start/Stop Status Flag Control Bits for select of Channel Selection of the Analog Input Pin ANx Processor Systems 17

18 Analog Input Channels and Corresponding ADDR Registers (Scan Mode only) Define Members of the group Define the active group Possible Groups Member for scan mode: Group 0: AN0, AN0 + AN1, AN0 + AN1+ AN2, AN0 + AN1+ AN2 + AN3 Group 1: AN4, AN4 + AN5, AN4 + AN5+ AN6, AN7 + AN8+ AN9 + AN Processor Systems 18

19 Single Mode Flow (Example) Initializing: Select Single mode (SCAN = 0), Select Input channel AN1 (CH2 = 0, CH1 = 0, CH0 = 1), Interrupt service only: The A/D interrupt is enabled (ADIE = 1), Start: Start A/D conversion (ADST = 1). Conversion: When A/D conversion is completed, the result is transferred to ADDRB. Flag set: At the same time: the ADF flag is set to 1 => The ADST bit is auto-cleared to 0, and the A/D converter goes to a idle state. Interrupt service only: Step (3) If ADF = 1 and ADIE = 1 request of ADI interrupt is requested. If accepted the A/D interrupt handler starts. Flag Read: If the Software detects ADF is set to 1; (or the interrupt handler runs) Flag Reset: read ADDRB, then writes 0 to the ADF flag. Software Read: The Software has to do further (or the interrupt handler) reading and processes result (ADDRB). Restart: Software ADST set to 1 (or the interrupt handler at the end). Goto Step "Conversion" Processor Systems 19

20 Single Mode Example Processor Systems 20

21 Scan Mode Flow (Example) Initialization: Select Scan Mode (SCAN = 1), Conversion: First Channel Sec. Channel Third Channel Flag set Select Scan group 0 (CH2 = 0), Select Analog input channels AN0 to AN2 (CH1 = 1, CH0 = 0), Interrupt service only: Set ADIE bit to 1 Start A/D conversion (ADST = 1) When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Conversion of the second channel (AN1) starts automatically the result is transferred to ADDRB. Conversion of the third channel (AN1) starts automatically the result is transferred to ADDRC. Interrupt service only: If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion group ends. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. Loop As long as the ADST bit remains set to 1: Go to Step "Conversion" or Stop Restart When the ADST bit is by Software cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Go to Step "Conversion" Processor Systems 21

22 Scan Mode Example Processor Systems 22

23 A/D Counter Clocks States are derived from System Clock (3 Examples) selectable prescaled clocks - ADC can internal scale CLK by 2 (CKS-Bit) TPU SCI ADC *) TPU SCI ADC *) TPU SCI ADC *) Processor Systems 23

24 AD Conversion Timing Processor Systems 24

25 AD Conversion Time Scan Mode: In the second and all subsequent conversions the conversion time t conv is fixed slow successive approximation: define internal prescale of clk/2 with setting of CKS = 0: t d =0, t spl = 63 and t conv = 256 [all in system clock states] fast successive approximation: define internal use of clk with setting CKS = 1 : t d = 0, t spl =31 and t conv = 128 [all in system clock states] Single Mode or in the first Cycle of Scan Mode the conversion time t conv varies marginally (AD conversion start delay t D varies due to different access time of ADCSR) t d =??, t spl =31 / 63 and t conv =?? [all in system clock states] Processor Systems 25

26 Conversion time Example at MHz Clock Scan Mode: In the second and all subsequent conversions the conversion time t _conv is fixed if CKS = 0 : 256 system clock states => 128 x ns = µs if CKS = 1 : 128 system clock states => 128 x ns = µs In Single Mode or in the first Cycle of Scan Mode see table: 259 clk states 266 clk states 131 clk states 134 clk states Processor Systems 26

27 A/D control status register ADCSR Processor Systems 27

28 A/D Conversion Control Register Processor Systems 28

29 External Trigger Input Timing - Example Trigger Delay Trigger Delay: defined hardware function 2 system clock rising edges and one falling edge min. time > 1.5 system clock states max. time < 3 system clock states approx. time > 2 system clock states Processor Systems 29

30 A/D Converter Interrupt Source ADI starts the interrupt service routine (ISR) which: => is a part of the controller application software (called interrupt handler) => reads ADDRAH and ADDRAL => and processes (or stores) the results Processor Systems 30

31 Equidistant Sampling & Equidistant Value Quantisation Equidistant Sampling (time) => Required from the most signal processing methods (filters, transforms...) => Systematic error: Max. Resolution Sampling Periods max. 1/2 delta t => errors: (sampling) time jitter, not often: sampling time drifts (R/C Sources) Equidistant Value Quantization => Required from binary arithmetic => Systematic error: Quantization max. 1/2 LSB => other Errors: Offset, Nonlinerarity, Fullscale Error (Factor), Missing Codes Processor Systems 31

32 Example 1 of ADC settings Vref = 5 V, AVss = 0 V, AVcc > 5 V, delta t = tconv = 128 x clk period (CKS=1) Processor Systems 32

33 Example 2 of ADC settings Vref = 3 V, AVss = 0 V, AVcc > 3 V, delta t = tconv = 256 x clk period (CKS=0) Processor Systems 33

34 A/D Converter Value Precision Terms Resolution ((Vmax-Vmin) / Number of Steps) Offset error ("Non zero value") Full-scale error ("Non Max value") Quantization error (1/LSB) Nonlinearity error (excluding offset error, full-scale error, or quantization error) Absolute error (includes the offset error, full-scale error, quantization error, and nonlinearity error) Relative error = Absolute error / value Relative error Full scale = Absolute error / Max value Processor Systems 34

35 Systematic Error - Quantization (1/2 LSB) Processor Systems 35

36 Adding 1/2 LSB with respect to the Quantization Error The digital output DO is expressed by the following formula: Processor Systems 36

37 Few other Errors of an ADC (Static view only) Processor Systems 37

38 Pins of A/D Converter Processor Systems 38

39 Analog signals are much more "sensitive" then digital! Processor Systems 39

40 Exercise Please see separated presentation Processor Systems 40