ARFTG - Microwave Measurement Conference. System Modeling and Measurement for High Accuracy Verification

Transcription

1 ARFTG - Microwave Measurement Conference System Modeling and Measurement for High Accuracy Verification December 1st - 4th, 29, Broomfield/Boulder, Colorado

2 OUTLINE PART I : Pulsed IV and S parameters for GaN HEMT compact models presented by T. Reveyrand (XLIM) PART II : Load Pull Measurement setups presented by T. Gasseling (AMCAD Engineering)

3 PART I : Pulsed IV and S parameters for GaN HEMT compact models T. Reveyrand (XLIM)

4 Pulsed IV measurement system for GaN HEMT compact modeling

5 Instrumentation Compact modeling activities (Pulsed) Load-Pull measurement setup Pulsed IV & [S] measurement setup (incl. Thermo-chuck) Commercially available tools through the independent company AMCAD Engineering Agilent Channel Partner PNA-X based setups

6 Pulsed S parameters Vds (t) RF small signal Vds i S(1,1) S(2,2) freq (4.GHz to 4.GHz) freq (4.GHz to 4.GHz) Vds 5 ns 55 ns 1 µs 2 ns 25 ns t db(s(2,1)) db(s(1,2)) freq, GHz freq, GHz phase(s(2,1)) phase(s(1,2)) freq, GHz 2 4 freq, GHz

7 1.4 2x5um Id (A) Quiescent point Vgs = V Vds = V Quiescent point Vgs = -8. V Vds = V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Pulsed S parameters Lag identification.2 Intrinsic parameters extraction Vds (Volts) 1.4 2x5um Id (A) Quiescent point Vgs = -8. V Vds = V Quiescent point Vgs = -8. V Vds = 25 V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Ib (A) x5um Quiescent point Vgs = -8. V Vds = V Quiescent point Vgs = -8. V Vds = 25 V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vgs=+2. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds (V) Vds (Volts)

8 Commercially available system from AMCAD Engineering VNA (Optional) BiasT T DUT BiasT T 5Ω 2Ω V I Input Pulse generator Pulse IV meas. Unit V I Output Pulse generator Pulse IV meas. Unit

9 Pulsed I(V) and S2P measurements Thermal chuck & Pulsed IV and S parameter measurement system used for model extraction.5 4 GHz 1A/24V 2 ns to 1 ms pulses - 65 to 2 C Dynamic measurements from a quiescent bias point For each pulsed bias point, the complete S2P parameters (,4-4GHz) are recorded

10 Pulsed IV measurement system for GaN HEMT compact modeling

11 Frequency dependant elements extraction Set of extrinsics parameters Linear Model Extraction Simulated Annealing Optimization Measured [S] parameters { Y12} + Re{ Y22} De-embedding Intrinsics parameters calculus from intrinsic admittance matrix Gd = Re Gm = ( A + B )( 1+ Ri Cgs ω ) - Rgd = 2 ( Re{ Y12} + Gdgd) Re{ Y12} + Gdgd { } Cgd ω Im Y12 No Fit? Yes S(2,2) S(1,1) freq (2.GHz to 35.GHz) db(s(1,2)), db(s(2,1)) Phase(S(1,2)), Phase(S(2,1)) S(2,1) S(1,2) freq, GHz S(1,2) S(2,1) freq, GHz Au point de polarisation de l application visée First step of Nonlinear Model Extraction COMPLETED

12 Mesure Modele x75 POLAR Vgs=-4.41 V, Vds= V, Id =+.163 A Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts Cgs _1D Vgs 6,E-13 5,E-13 4,E-13 3,E-13 2,E-13 1,E-13,E+ Mesure Modele Cgd_1D Vgd 1,4E-13 1,2E-13 1,E-13 8,E-14 6,E-14 4,E-14 2,E-14,E+ 1,6 1,55 1,5 1,45 1,4 1,35 1,3 1,25 1,2 y = -,24x + 1, ,5E-14 3,E-14 2,5E-14 2,E-14 1,5E-14 1,E-14 5,E-15,E+ y= 1,6E-16+1,4973E-16*EXP(T/26,3157) ARFTG - Microwave Measurement Conference Modeling Étapes de process modélisation Non-linear Model Extraction db (S(1,2)) db (S(2,1)) Small Modèle Signal petit-signal Model Modèle I-V Model I-V Nonlinear Capacités capacitances NL Modèle Thermal thermique model Modèles Trapping de effects pièges S(1,1) 1) ; S(2,2) freq, GHz Phase (S(1,2)) Phase (S(2,1)) freq, GHz freq, GHz freq, GHz Ids (A) Vds (V) Id en Amperes Cgs (F) Cgd (F) Idss Is_gs 6.E-2 5.9E-2 5.8E-2 5.7E-2 5.6E-2 5.5E-2 5.4E-2.E+ 2.E-6 4.E-6 6.E-6 8.E-6 1.E-5 k Vds + k + Vgs_int Rfill Vgs Vds Rempty C Vds freq (2.GHz to 4.GHz) Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Dgs=f(Vgs) Dgd=f(Vgd) Ids=f(Vgs,Vds) Cgs=f(Vgs) Cgd=f(Vgd) Dgs=f(Vgs) Dgd=f(Vgd) Ids=f(Vgs,Vds,T) Rs=f(T) Rd=f(T) Rgd=f(T) Ids=f(Vgs_pièges,Vds,T) Ids=f(Vgs_trap,Vds,T)

13 V GSN Id Tajima V = 1+ GS = 1 I 1 m ( t ) DSS ( m 1 e ) τ Vφ V P Modeling IV curves Id en Amperes V GSN 1 m [ ] ( ) 2 mvgsn VDSN 1 1 ( 1 avdsn bv e e ) DSN 8x75 POLAR Vgs=+.163 V, Vds=+1.97mV, Id =-.55mA Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts

14 Id en Amperes Capacitances Cgs et Cgd extracted from [S] parameters along the optimal load-line 8x75 POLAR Vgs=-4.41 V, Vds= V, Id =+.163 A Cycle de charge utilisé pour Load-line for Cgs and l extraction des capacités Cgs et Cgd Cgdextraction Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts Cgs=f(Vgs) Cgd=f(Vgd) Quiescent Point de polarisation bias point de repos Equations Mesure Modele Cgs_1D 6,E-13 5,E-13 4,E-13 3,E-13 2,E-13 1,E-13,E Vgs Mesure Modele Cgd_1D Vgd 1,4E-13 1,2E-13 1,E-13 8,E-14 6,E-14 4,E-14 2,E-14,E+ Cgs=C+(C1-C).(,5+,5.tanh(a.(Vgs+Vm))) -C2.(,5+,5.tanh(b.(Vgs+Vp))) Cgs (F) Cgd (F)

15 Vg 1 2 Vs 1 Vg 2 Vd ARFTG - Microwave Measurement Conference Non-linear Models for designers Vscgd MODEL_diode_breakdown_gd X8 Iavdg=6e-5 alpha_dg=.8 beta4_dg= beta3_dg= beta2_dg= beta_dg= Classical Non linear Model MODEL_diode_gd X9 Is_gd=2.5e-16 Ngd=2.48 R Rfuite R=7e4 Ohm Vgcgd MODEL_Cgd X13 C=9.95e-14 C1=7.17e-14 C2=-7.99e-14 a= b=.124 Vm=27.16 Vp=12.6 Vd_int Vgcgd I_Probe Ids_int MODEL_Cgs X15 Linear element C= e-13 C1= e-12 C2=1.37e-13 a=1.398 b=1.61 Vm=5.518 Vp=3.892 MODEL_Tajima X16 tau=2.15e-12 idss=1.99 vp=5.1 vdsp=3 vphi=.11 A=.5 B=. M=4 P=.34 W=.55 beta_gmd=.335 alpha_gmd=.882 vgm=33 vdm=22 Vs_int C Cds C= ff Nonlinear element MODEL_diode_gs X12 Is_gs=2.5e-16 Ngs=2.7

16 Non-linear Models for designers PAE % vgs_ext=1. vgs_ext=2. vgs_ext=. vgs_ext=-1. vgs_ext= Ids.5. vgs_ext=-3. vgs_ext=-4. vgs_ext=-5. vgs_ext=-6. vgs_ext=-8. vgs_ext=-7. Gain (db) P in_ db m LP I-V Vds db S(1,2) db S(2,1) 2 1 [S] freq, GHz freq, GHz S(1,1), S(2,2) 4 15 Phase S(1,2) Phase S(2,1) 1 5 freq (2.GHz to 4.GHz) freq, GHz freq, GHz

17 Therm al effec t Modelling Thermal Simulations Self Heating Extraction = f(t) Zth [ C/W] HEMT 1t8x75_35µm - 7W/mm_3 C 24 GaN1.2µm/SiC44µm/AuSn45µm/Al2mm ANSYS 4 FIT RC 2 1.E-3 1.E-2 1.E-1 1.E+ 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 temps [µs] Exponential expansion : RC cells behavior R1 R2 R3 R4 R5 TEMP = 22,8.(1-e-t/τ1) + 21,7.(1-e-t/τ2) + 7.(1-e-t/τ3) + C1 C2 C3 C4 C5 I = P dissipée U=T chuck_ C T C

18 Therm al effec t Modelling IV several temperatures IV parameters versus temperature Id en Amperes Id en Amperes x75 POLAR Vgs=+.163 V, Vds=+1.97mV, Id =-.55mA Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts Rs, Rd Idss y =.49x Rd Rs Equations.2.8 y =.29x Thermal parameters Access Resistances Current Source Vds en Volts T C Measure / IV 25 C - Diodes.. Rs= Rs + α _Rs.T Rd= Rd 8x75 POLAR Vgs=+.165 V, Vds=+9.79mV, Id =-.44mA α_rd.t Vgs=+1. V 1.16 Vgs= +.nv Idss= Idss.6 Vgs=-1. V 1.14 Vgs=-2. V + Idss t.t Vgs=-3. V y = -.8x Vgs=-4. V 1.12 P=P Vgs=-5. V Vgs=-6. V 1.1 +P t.t.4 Vgs=-7. V Vgs=-8. V 1.8 Ngs=Ngs Ngs t.t Ngd=Ngd +Ngd t.t Isgs=Isgs T C +Isgs t.e (T/Tsgs) Isgd=Isgd +Isgd t.e (T/Tsgd) Measure / IV 15 C.

19 Vg 1 2 Vs 1 Vg 2 Vd ARFTG - Microwave Measurement Conference Vscgd INPUT : Dissipated power Thermal Block OUTPUT : Temperature Vgcgd MODEL_diode_breakdown_gd X8 Iavdg=6e-5 alpha_dg=.8 beta4_dg= beta3_dg= beta2_dg= beta_dg= MODEL_diode_gd X9 Is_gd=2.5e-16 Ngd=2.48 R Rfuite R=7e4 Ohm MODEL_Cgd X13 C=9.95e-14 C1=7.17e-14 C2=-7.99e-14 a= b=.124 Vm=27.16 Vp=12.6 Vd_int Vgcgd I_Probe Ids_int MODEL_Cgs X15 Linear element Nonlinear element Thermal element C= e-13 C1= e-12 C2=1.37e-13 a=1.398 b=1.61 Vm=5.518 Vp=3.892 MODEL_Tajima X16 tau=2.15e-12 idss=1.99 vp=5.1 vdsp=3 vphi=.11 A=.5 B=. M=4 P=.34 W=.55 beta_gmd=.335 alpha_gmd=.882 vgm=33 vdm=22 Vs_int C Cds C= ff MODEL_diode_gs X12 Is_gs=2.5e-16 Ngs=2.7

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21 Trapping effec t Modelling Gate- and drain-lag model topology (for ONE trap) Trapping effect on the current modeled with a modification of the control voltage (= Vgs) - Creates transients on Vgs = Current transients - Charging state of the capacitance = charging state of the traps - Fills through Rcapture, releases through Rémission Fills and releases model of traps (diode) Processing: null offset, current dependencies, etc. Easy tuning of the amplitude Fundamental effect : fill / release trapping time constants are different modeled with an envelope detector Circuits number = Modeled traps number 3 parameters to extract per circuit : Rcaption, Rrelease, k

22 Trap model parameters extraction Trapping effect Modelling Current transient measurement, Negative pulse on Vds (emission) Obtaining : - numbers of traps - emission time constants - relative amplitude of each trap! Avoid thermal effects during measurement ONLY ONE MEASUREMENT TO OBTAIN ALL THOSE PARAMETERS

23 Model Validity : Large Signal power optimal load impedance Load.8 PAE(%) 4 2 Traps ON Traps OFF Measurements Pin (dbm) IDS (ma) 25 2 Zload (. to.) Pin (dbm) reseau_iv_sdd..ids_int.i cycle Phase (Gamma_in) indep(cycle) X1.Vd_int Pin (dbm) Gain(dB) Pin (dbm) Pout (W) Pin (W) Mag (Gamma_in) Pin (dbm)

24 The current slope phenomenon 22 IDS (ma) Pin (dbm) Charging state of the traps (Drain-lag)

25 The current slope phenomenon 22 IDS (ma) Pin (dbm) Charging state of the traps (Drain-lag)

26 The current slope phenomenon 22 IDS (ma) Pin (dbm) Charging state of the traps (Drain-lag)

27 The current slope phenomenon 22 IDS (ma) Pin (dbm) 2.5 Charging state of the traps (Drain-lag) Saturation = Auto-bias

28 Completed Nonlinear Model

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30 PART II : Load Pull Measurement setups T. Gasseling (AMCAD Engineering)

31 Load Pull for PA Design : LPPD The needs Existing architectures Load Pull for Model Validation : LPMV Specific needs Measurement definition Specific Architecture News trends Time domain measurements for model validation

32 Load Pull used for PA Design : LPPD The needs Existing architectures Load Pull used for model validation : LPMV Specific needs Measurement definition Specific Architecture News trends Time domain measurements for model validation

33 Load Pull for PA Design The needs: From the target definition (Pout, Efficiency, Gain ect.) Power performances versus Zsource and Z load ISO-circles plot -> Determination of optimal operating conditions Transistor performances evaluation associated to given operating conditions for the design of PA. Transistor model validation

34 Load Pull for PA Design LPPD architecture Microwave Source Power Amplifier Input Coupler DUT Power Meter Input Tuner Output Tuner Power Meter The LPPD setups have been developed in order to find the transistor s optimal source and load impedances for defined and fixed operating conditions

35 These LPPDs setups can be used for: Transistor performances evaluation for given operating conditions (transistor + setup combination) Determination of optimal load impedances : useful for PA design when nonlinear models are not available These LPPDs setups can not be used for: A determination of the intrinsic transistor characteristics useful for transistor model validation.

36 Can a LPPD setup measure Power Added Efficiency? The answer is: NO. A passive load pull system measures the source power (available) toward the input of the DUT and the power delivered by the DUT to the load. If a directional coupler is used to measure the power returned by the DUT to the source, in order to assess the really absorbed power by the DUT, then the loss of the input tuner and the coupler can only be calculated if we know the large signal input impedance of the DUT. However: If the DUT is perfectly input matched and only then, the Efficiency measured equals the Power Added Efficiency defined as: PAE = (Power delivered to load Power delivered to DUT ) / (DC power); and the Gain measured becomes Power Gain Gp = Pout-del / Pin-del But one has to be careful: If the DUT is tuned at the input so that the reflected power to the source (measured via the 4rth port of the input coupler or the third port of a circulator) becomes zero, this does not mean the DUT is "input matched", it means that the setup is matched at the intersection between tuner and circulator, not tuner and DUT

37 Illustration : Measurements on a f=4ghz Microwave Source Power Amplifier Input Coupler Γin-tuner Γin-DUT DUT Power Meter Input Tuner Output Tuner P meter S11 S22

38 Illustration : Measurements on a f=4ghz Microwave Source Power Amplifier Input Coupler Zin-tuner Zin-DUT DUT Power Meter Input Tuner Output Tuner Power Meter Φ(S22)=Φ(Γin*)

39 Illustration : Measurements on a f=4ghz Microwave Source Power Amplifier Input Coupler Zin-tuner Zin-DUT DUT Power Meter Input Tuner Output Tuner Power Meter The source tuner is matched (not the DUT) Φ(S22)=Φ(Γin*)

40 Illustration : Measurements on a f=4ghz Microwave Source Power Amplifier Input Coupler Zin-tuner Zin-DUT DUT Power Meter Input Tuner Z_Source Output Tuner Power Meter The DUT is matched (not the source tuner) Φ(S22)=Φ(Γin*)

41 Can a PA Load Pull System measure Power Added Efficiency? : The answer is: NO. The assumption that the Efficiency measured equals the Power Added Efficiency only when the DUT is input matched and only then, means that this assumption is valid only when the source pull optimization (iso-pout or Gain circles) is done for a constant amount of input power injected into the DUT. As a consequence, because the transistor s input impedance is related to the amount of power injected in the DUT, this optimization must be done for each power level.

42 Conclusion : Each time the power injected in the DUT is varied, the transistor input impedance is varied as well, and then the assumption of the perfect matching at the input could not be done any more. If the transistor s intrinsic PAE needs to be measured, then the source impedance should be optimized for each power step : cumbersome and time consuming Ordinary load pull architecture are useful for PA designers but raw data such as gain and Efficiency measurements are not accurate enough to be used for model validation.

43 Conclusion : In addition, measurements made with power meters are mean power measurements. When in the bandwidth of the power sensor, the power measured corresponds to the power generated at the fundamental and harmonic frequencies,. For model validation, the wanted power (at the fundamental frequency) and the power generated at harmonic frequencies, should be measured independently.

44 Some LPPDs setups have been updated in order to measure the transistor s input reflection coefficient: Microwave Source Power Amplifier Input Coupler Zin-tuner Zin-DUT DUT Power Meter Input Tuner Z_Source Output Tuner Power Meter A1 B1 B2 A2 VNA

45 Some LPPDs setups have been updated in order to measure the transistor s input reflection coefficient: Zin-DUT Coupler DUT Power Meter Input Tuner Power Meter A1 B1 B2 A2 VNA The lower Zin-DUT The Higher src tuner losses The lower the input deembedding accuracy Problem : The transistor power gain is really sensitive to the Γin meas accuracy.

46 Illustration : Gin measurements / LPPD setups Source pull : for each source impedance, the Gin measurement is de-embedded through a new input tuner s set of S2P bloc file. While the measurement accuracy if data such as Pout or Transducer Power gain versus Zsource are convenient for PA design..

47 Illustration : Gin measurements / LPPD setups Source pull : for each source impedance, the Gin measurement is de-embedded through a new input tuner s set of S2P bloc file. Some of them such as Γin or power gain are not accurate enough for Model validation

48 Load Pull used for PA Design : LPPD The needs Existing architectures Load Pull used for Model Validation : LPMV Specific needs Measurement definition Specific Architecture News trends Time domain measurements for model validation

49 Load Pull used for Model Validation Specific needs Measurement of the transistor input impedance, whatever the operating conditions (Zload, Power level ect.) Narrow band measurements at f, 2f, 3f ect. True calculus of Γin, PAE, Gain... Transistor model validation

50 Load Pull used for model validation Measurement definition P_in: Power delivered to the DUT by the source P_source: Power delivered by the source P_out: Power delivered to the load impedance

51 Load Pull used for model validation Measurement definition Used for model validation Power gain is the ratio of the power delivered to the load (P out ) to the power delivered to the transistor by the source (P in ). Used for PA design Transducer Power gain is the ratio of the power delivered to the load (Pout) to the power available from the source (Psource).

52 Load Pull used for model validation Measurement definition Used for model validation Power added Efficiency is the ratio of the power added by the transistor to the power consumed. Used for PA design Transducer Efficiency is the ratio of the power added by the source + transistor to the power consumed.

53 Load Pull used for model validation Measurement definition Used for model validation Power added Efficiency is the ratio of the power added by the transistor to the power consumed. Used for PA design Transducer Efficiency is the ratio of the power added by the source + transistor to the power consumed.

54 Illustration : Measurements on a f=4ghz Used for model validation Power gain Used for PA design Transducer Power gain Measurements done on the same transistor

55 Illustration : Measurements on a f=4ghz Used for PA design Transducer Power gain

56 Illustration : Measurements on a f=4ghz Used for model validation PAE Used for PA design Transducer Efficiency

57 Load Pull used for model validation Specific Architecture

58 Specific Architecture DC or pulse DC supplies + meas Units PA Gat te T Low loss directional couplers DUT Drain T 5ΩΩ Tuner f VNA Tuner f, 2f, 3f CW or pulse RF signal f or f1+f2

59 Specific Architecture AMCAD Load Pull system used for modellng activities

60 Conclusion Model validation using load pull measurements : VNA use instead of power meters Measurement in narrow band mode = F meas. + 2F meas. Instead of mean power meas. PA Gat te Better dynamic range = better meas. Accuracy T DUT Vector measurement s instead of scalar measurements = useful data for model validation Drain T

61 News trends Time domain measurements for model validation Time domain measurements for MMIC validation

62 Characteristics of transistor used: V BK >1V Rdson~ 2 ohm Cds=.9 pf Cgs= 8 pf Rg=.5 ohm Device used : 15 W GaN HEMT from CREE CGH615D Device size 2mm

63 Test Jig and packaged transistor fundamental frequency generator Harmonic tuner Focus MPT a1 b1 Time domain wave forms a2 b2 LSNA 5Ω Pout (dbm) Simulation Measurement PAE (%) Simulation Measurement Pe (dbm) Pe (dbm)

64 Ids(t) quasi-intrinsic (A) 1.5 Measure Simulation time, nsec Vds(t) quasi-intrinsic (V) 12 Class E time, nsec Intrinsic Impedance Extrinsic 2f Reference plan intrinsic de-embedding ref. Plan S4P f a1 b1 Test fixture Input package measure Plan (input) output package a2 Test fixture b2 measure Plan (output)

65 News trends Time domain measurements for model validation Time domain measurements for MMIC validation

66 Objective Time domain Measurement Setup HIP HIPHIP HIP Time domain measurement system RF sampling scope Long acquisition time Time base distorsions MTA (Microwave Transition Analyser) Obsolete 2 channels LSNA (Large Signal Network Analyser) Advanced technology (calibrated) 4 channels Commercialy available GSG GSG MMIC

67 Configuration HIP calibration assumption Vref. plane( f ) = ( f ).Vraw ( f ) K ~ Measurement Setup DOWN-CONVERTER BOX {r1 ; r2} 1 3 {r3 ; r4} 2 4 v 1 β HIP i 1 γ 1 δ 1 = v 2 i 2 LSNA HIP HIP α r 1 1 β1 HIP α γ CAL 2 CAL 2 β δ CAL 2 CAL 2 r 2 r 3 r 4 LSNA A1 5Ω B1 5Ω TEST-SET 1 2 HIP1 HIP2 A2 B2 GSG GSG {v1 ; i1} {v2 ; i2}

68 IN Applications OUT V be = 1V 1, Frequency 1,5, GHz 4 2 -,5 V ce = 9V LSNA -1 Analysis Grid -2-1,5 Fundamental harmonics -, ,5-8 Measurement -1, setup Pin (dbm) DC BLOCK GSG 93 ps HIP GSG -8

69 XLIM C2S2 123 Avenue Albert Thomas 876 Limoges Cedex FRANCE AMCAD Engineering Ester Technopole BP n Limoges Cedex FRANCE