Keysight Technologies

Transcription

1 DynaFET: A time-domain simulation model for GaN power transistors from measured large-signal waveforms and artificial neural networks David E. Root, Jianjun Xu, Masaya Iwamoto, Troels Nielsen, Samuel Mertens, Brian Chen, and Zhun Lin Keysight Technologies Slide 1

2 Acknowledgement Chad Gillease Jan Verspecht Jason Horn Radek Biernacki Mihai Marcu R. Jones S. A. Harris S. Halder F. Kharabi J. McMacken J. Gering C. Campbell M. Kalinski D. Sardin Z. Popovic Affiliations Keysight Raytheon RFMD TriQuint University of CO, Boulder DARPA MPC program (Dr. Dan Greene), through ONR (Dr. Paul Maki) Slide 2

3 NVNA DynaFET Modeling Flow Interoperable nonlinear measurement, modeling, & design IC-CAP ADS I V, V, T,,, V, V ) D( gs ds j 1 2 gs ds Vgs Vds Tj 2 1 V gs V ds NVNA-based device characterization system Model extraction and ANN training SW module Native implementation In Keysight ADS Slide 3

4 Outline Introduction DynaFET Model Capabilities and Features DynaFET Measurements on the NVNA DynaFET Model Identification (extraction) in IC-CAP Results: Model Validation Summary / Conclusions Slide 4

5 GaN Transistors Properties High power (e.g. 7W/mm) at microwave frequencies High speed - Circuit & MMIC design at mm-wave freqs soon Applications: High-efficiency power amplifiers - Doherty; Envelope Tracking, Radar High survivability low-noise amplifiers First-pass design success requires accurate, robust, and general nonlinear models well-implemented in commercial tools Slide 5

6 Challenges of GaN Modeling Characterization Wide operating range (100V or more) Excitation design: stimulus/responses for identification of the several independent mechanisms of relevance. Strong hysteresis; DC not even well-defined! Phenomena (nonlinearity and memory effects) Dynamic Self-Heating Nonlinear Charge Storage (multi-terminal) Gate Lag Drain Lag (current collapse, knee walk-out ) Slide 6

7 Drain Lag Pulsed IV measurements Id (ma) knee walkout [-0.2, 4] Vds (V) [-0.8, 6] But: Which I V curves to use? How to relate PIV curves to model coupling terms (trapping model)? Quiescent Bias Point Slide 7

8 DynaFET: Overall Objectives One global nonlinear simulation model in time-domain Valid over broad frequency range, multiple bias-points, over all load conditions, for CW and digitally modulated signals, Don t want a model that has to be tuned (re-extracted) for different applications Systematic characterization based on large-signal NVNA waveform data Automated identification (extraction) methods to separate mechanisms Automated, accurate, constitutive relations (I-V, Q-V) for a wide variety of devices (general) that simulate quickly and are robust for convergence Slide 8

9 D gs gs ds ds j j 1 gs ds gs ds DynaFET Model and Capabilities Same use model as conventional time-domain compact model Well-implemented as native nonlinear component I ( V, V, T,, 2, V, V ) V V T 1 2 V V NVNA-based device characterization Advanced compact model constructed from NVNA data Valid for all modes of simulation (e.g. TA, HB, SP, etc.) Natively implemented nonlinear component in Keysight ADS Slide 9

10 Equivalent Circuit (dynamics, physics ) VGS VDS I ( Vgs,Vds,Tj, 1, 2 D ) I G Q G Q D I D T j I( t) V ( t) C th R th Self-heating R 1_emit T 0 R 2_emit V GS 1 V DS 2 Trapping R 1_capt C 1_emit R 2_capt C 2_emit [3] O. Jardel et al, IEEE Transactions on MTT., vol. 55, Dec., [2] J. Xu, M. Iwamoto, J. Horn, D. E. Root, IEEE MTT-S International Microwave Symposium Digest, May, See also MOS-AK 2010 [10] Slide 10

11 Model Capabilities Features dynamic self-heating and ambient temperature-dependence gate-lag and drain-lag independently modeled (knee walk-out, power slump) artificial neural networks (ANNs) for very general, smooth I-V / Q-V relations NVNA data for model generation and independent nonlinear validation geometrical scaling Benefits accuracy versus temperature; thermal memory modeled power slump, bias current versus Pin, and PAE well modeled detailed nonlinear coupling of trap states to current accurately & smoothly modeled data covers entire operating range while maintaining device safety; NVNA data closer to actual use condition Same as standard expectations for a compact time-domain transistor model Slide 11

12 DynaFET Measurement Synchronized Bias Supplies Agilent E5270B or 4142B Controlled by an automated SW app. on PNA-X NVNA PA Bias T Bias T PA A 11 power bias Measurements performed at various: (1) DC biases (2) A11 power (3) A21 power (4) A21 phase (5) Ambient temperatures 4V Ambient temperatures bias Time, nsec Time, nsec Time, nsec Time, nsec A 21 power A 21 phase [6] J. Xu, R. Jones, S. A. Harris, T. Nielsen, and D. E. Root, 2014 IEEE International Microwave Symposium. [9] T. S. Nielsen, M. Dieudonne, C. Gillease, and D. E. Root, IEEE CSICS Digest La Jolla, CA, Oct 2012 [2] J. Xu, M. Iwamoto, J. Horn, D. E. Root, IEEE MTT-S International Microwave Symposium Digest, May, ma 70V 600 ma Slide 12

13 NVNA Data A 1k A 2 k B1k V 2Z ( A B ) p, k 0 p, k p, k 2 I A B pk, pk, pk, Z0 vp() t Re Vp, ke jk 0t B2 k A pk k V1 2 time B pk Harmonic Index Port Index I ip() t Re Ip, ke k jk 0t time Superset of DC & S-parmeter data S-parameters Waveforms Intermodulation X-parameters (see [1],[10]) Slide 13

14 Benefits of NVNA Data Large-signal RF measurements More realistic stimulus for DUT (than pulsed I-V) Closer to most design applications for device model Timescales 2 to 3 orders of magnitude faster than typical pulsed I-V! (0.1 to 10 GHz vs 1-10 MHz) Less stress to device when probing limiting mechanisms Fast enough to probe charge storage elements Nonlinear validation nearly for free Same instrument; AM-AM, AM-PM, compression, load-lines, intermodulation and harmonic distortion with phase, Slide 14

15 Detour: Modeling Flows Enabled by NVNA NVNA Conventional parameter extraction to NVNA data ADS NVNA-based device characterization DynaFET compact model constructed from NVNA data IC design X-parameters for transistor behavioral modeling [10] D.E. Root J. Horn, J. Xu, M. Iwamoto, F. Sischka, and Y. Yanagimoto MOS-AK Workshop, Dec.2010 San Francisco Slide 15

16 Active NVNA System for DynaFET Experiment Design: Active source injection Adaptive compliance mechanisms Synchronized Bias Supplies Agilent E5270B or 4142B Automated DUT coverage Pin, A 2,1, bias Slide 16

17 Sample Waveform Data Idrain (A) Idrain (A) GaAs GaN m Vd (V) GaAs Idrain (A) Vd (V) GaN Vd (V) Slide 17

18 Active Source Injection Measurements System avoids dangerous waveforms 2,1 Built-in device compliance mechanism for safety (e.g. avoid breakdown regions) No need to achieve gridded load impedances or A 2,1 ; just cover range of operation Slide 18

19 DynaFET Model Identification (Extraction) I D ( V gs, Vds, T j,, 2, V, V 1 gs ds ) V gs V ds T j 1 2 Self-heating V gs V ds NVNA-based device characterization Trapping Compiled model for use in Keysight ADS Average DynaFET compact model constructed from NVNA data [7] J. Xu, S. Halder, F. Kharabi, J. McMacken, J. Gering, D. E. Root,83rd IEEE ARFTG Conference, June 2014 Slide 19

20 I I gate drain (t) (t) I G I (V D (V gs gs (t), V (t), V Model Generation ds ds (t), T (t)) j (t), T j(t), 1 (t), 2 (t), V (t) I gate d dt Q G (V gs (t), V gs ds (t), V (t), T (t)) ds j (t)) d dt Q D (V gs (t), V ds I drain (t) (t), T (t)) j T (t), 1 (t), (t), V j 2 gs (t), V Auxiliary Variables ds (t) Self-heating Trapping Average Slide 20

21 Auxiliary Variable Identification (1) I (t) I (V (t), V (t), T (t), 1 (t), (t), V drain D gs ds j 2 gs (t), V ds (t)) Neglecting displacement current at low RF freqs. 1 emit f RF 1 capture (t) 1 Min(V gs (t)) 2 (t) Max(V ds (t)) 4 40 V gs (t) ts(vgsint_q[0,::]) ts(vgsint_q[2,::]) ts(vgsint_q[1,::]) ts(vgsint[0,::]-vsint[0,::]) ts(vgsint[2,::]-vsint[2,::]) ts(vgsint[1,::]-vsint[1,::]) 1 (t) (t) ts(vdsint_q[0,::]) ts(vdsint_q[2,::]) ts(vdsint_q[1,::]) ts(vdsint[0,::]-vsint[0,::]) ts(vdsint[2,::]-vsint[2,::]) ts(vdsint[1,::]-vsint[1,::]) V ds (t) time, nsec time, nsec Slide 21

22 NVNA Waveforms Model Identification I I (V, V, T,,, V, V ) Terminal Voltages (V gs, V ds ) drain D gs ds j 1 2 gs ds Terminal Voltages Auxiliary Variables Constitutive Relation Identification / Train Artificial Neural Networks (ANNs) I I (V, V, T,,, V, V ) drain D gs ds j 1 2 gs ds Natively Compiled Model in ADS T j Auxiliary Variable Generation T I( t) V ( t) 0 R Min( V ( t)), Max( V ( t)) V 1 gs 2 gs Ave(V gs (t)), V ds th Ave(V ds ds (t)) Tj Auxiliary Variables V V 1 gs ds j gs ds For model identification Auxiliary variables fixed at their steady-state large-signal values In simulation Auxiliary variables vary in time according to the coupled equivalent circuits 2 gs ds I D ( Vgs, Vds, Tj,, 2, V V V T 1 2 V, V 1 gs ds V ) ANNs model detailed, general, multi-variate coupling - Accurate and general - No additional assumptions (e.g., backgating/virtual gate) Slide 22

23 Artificial Neural Networks y 1 = f 1 (x 1, x 2, x 3 ) y 1 y 2 y 2 = f 2 (x 1, x 2, x 3 ) Outputs V jk Hidden Z 1 Z 2 Z 3 Z Neuron 4 W ki Hidden Neuron Output Parameters w = [W ki, V jk ] y j = V jk Z k k x i Z k = tanh( W ki ) x 1 x 2 x 3 Inputs Universal Approx. Thm: Can fit any nonlinear function of many variables The model computation is very fast. Infinitely differentiable. Perfect for training on non-gridded data. Slide 23

24 Knee Walk-Out vs RF Power Slide 24

25 Results DC IV S-parameters versus bias and frequency One-tone Harmonic Distortion Two-tone Intermodulation Load pull contours Slide 25

26 Results (device 1) Raytheon 6x60 mm GaN HFET GaN HFET Transistor from Raytheon Integrated Defense Systems 0.15 um x 6 finger x 60 um GaN HFET Individual Source Vias Optimized for 1-40 GHz operation - Power amplifiers - Low noise amplifiers - Switch applications [6] J. Xu, R. Jones, S. A. Harris, T. Nielsen, and D. E. Root, 2014 IEEE International Microwave Symposium, Tampa, June. Slide 26

27 Measurement Space Raytheon 6x60 mm GaN HFET Experiment design covers entire operating range; Well beyond static data 1-Tone, 16GHz 50ohm load 20V, 54mA DC 1-Tone Measurements NVNA Measurements Slide 27

28 Raytheon 6x60 mm GaN HFET 0.5 Model Validation (25 deg) 0.05 Idrain_meas I_drain.i Id (A) Red: Measured Blue: DynaFET Igate_meas Ig I_gate.i (A) Red: Measured Blue: DynaFET Vd (V) Vdrain Zoom in E E Vd Vdrain (A) Zoom in I_drain.i Idrain_meas Id (A) I_gate.i Igate_meas Ig (A) 5.00E E E0-2.50E E E E Vd Vdrain (A) -1.25E Vdrain (A) Slide 28

29 Raytheon 6x60 mm GaN HFET 0.5 Model Validation (55 deg) 0.05 Idrain_meas I_drain.i Id (A) Red: Measured Blue: DynaFET Igate_meas Ig I_gate.i (A) Red: Measured Blue: DynaFET Vd (V) Vdrain Zoom in E E Vd Vdrain (A) Zoom in I_drain.i Idrain_meas Id (A) I_gate.i Igate_meas Ig (A) 5.00E E E0-2.50E E E E Vd Vdrain (A) -1.25E Vdrain (A) Slide 29

30 Raytheon 6x60 mm GaN HFET Model Validation S21 Vd=20V, Id=64mA S12x50 S22 S11 Red: Measured Blue: DynaFET Vd=8V, Id=40mA S21 S12x50 S22 S11 Slide 30

31 Raytheon 6x60 mm GaN HFET Gain Model Validation 1-Tone, Id=54mA Fundamental output phase Red: Measured Blue: DynaFET Harmonics Fund Bias Current PAE 2 nd 3 rd 4 th Slide 31

32 Raytheon 6x60 mm GaN HFET Gain Model Validation 1-Tone, Id=36mA Fundamental output phase Red: Measured Blue: DynaFET Harmonics Fund Bias Current PAE 2 nd 3 rd 4 th Slide 32

33 pin_1l dbm(10*$measdata..a1[0,0,0,0,::,0,4]) Model Validation Raytheon 6x60 mm GaN HFET 2-Tone, f1=10.0ghz, Id=54mA Lower Sideband Lower Sideband Upper Sideband pout_3l1 dbm(10*$measdata..b2[0,0,0,0,::,0,3]) dbm(10*$measdata..b2[0,0,0,0,::,0,4]) Pout pout_1l1 (dbm) pout_3u1 dbm(10*$measdata..b2[0,0,0,0,::,0,6]) dbm(10*$measdata..b2[0,0,0,0,::,0,5]) Pout pout_1u1 (dbm) Fund IM3 Pin (dbm) Red: Measured Blue: DynaFET -100 Upper Sideband Fund IM Pin (dbm) pin_1u dbm(10*$measdata..a1[0,0,0,0,::,0,4]) pout_5l1 dbm(10*$measdata..b2[0,0,0,0,::,0,2]) dbm(10*$measdata..b2[0,0,0,0,::,0,4]) Pout pout_1l1 (dbm) pin_1l dbm(10*$measdata..a1[0,0,0,0,::,0,4]) pout_5u1 dbm(10*$measdata..b2[0,0,0,0,::,0,7]) dbm(10*$measdata..b2[0,0,0,0,::,0,5]) Pout pout_1u1 (dbm) Fund IM5 Pin (dbm) -100 Fund IM Pin (dbm) pin_1u dbm(10*$measdata..a1[0,0,0,0,::,0,4]) Actual stimuli and mismatch presented to model Slide 33

34 DynaFET Validation Raytheon 6x60 mm GaN HFET Power Delivered (dbm) Bias 12V, 54 ma, 10GHz Red: Measured Blue: DynaFET PAE (%) Pdel_conts_forSmithCh1 Pdel_conts_forSmithCh PAE_conts_forSmithCh1 PAE_conts_forSmithCh Mag_rho (0.154 to 0.800) Mag_rho (0.026 to 0.800) Mag_rho (0.136 to 0.800) Mag_rho (0.023 to 0.800) Maximum Power Delivered, dbm Maximum Power-Added Efficiency, % Measured Modeled Measured Modeled Measured: Load-dependent X-Parameters Slide 34

35 Results (device 2) RFMD 6x75 mm GaN HEMT DC NVNA Measurements Experiment design covers entire operating range; 1-Tone, 3.5GHz 50ohm load 48V, 10mA Well beyond static data [7] J. Xu, S. Halder, F. Kharabi, J. McMacken, J. Gering, and D. E. Root, ARFTG Conf. June, 2014, Tampa Slide 35

36 RFMD 6x75 mm GaN HEMT DynaFET Validation Red: Measured Blue: DynaFET I_drain.i Idrain_meas Vdrain Slide 36

37 RFMD 6x75 mm GaN HEMT DynaFET Validation Freq=1GHz, V=48V, Id=20mA, Source & Load=50Ω Slide 37

38 DynaFET Validation (device 4) TriQuint 8x40 mm GaN HEMT Bias 5V, 3.2 ma, 10GHz PAE (%) Gain (db) Pout (dbm) Pout (dbm) Acknowledgement: Dr. Charles Campbell and Maureen Kalinski (TriQuint) Prof. Zoya Popovic s group (Univ. of Colorado, Boulder), in particular David Sardin. UCB validation work funded under the DARPA MPC program (Dr. Dan Greene), through ONR (Dr. Paul Maki) Slide 38

39 DynaFET: Summary General, accurate compact III-V FET nonlinear model - Dynamic Self-Heating - Multi-dimensional Charge Storage - Trapping Effects for Gate-lag and Drain-lag (memory) Enabled by NVNA data Accuracy & Generality enabled by ANN Technology Excellent results for linear and nonlinear simulation Validated on a wide range of GaN (and GaAs) FETs from several manufacturers Slide 39

40 Conclusions: DynaFET Flow DC supplies RF sources bias tees amps probe station thermal chuck model-file (ANN weights) Circuit simulation PNA-X NVNA DynaFET Module PNA-X - NVNA DynaFET SW module Meas. control SW GUI Active Source Injection X-parameters (validation) Harmonics (validation) Intermodulation (validation) DynaFET model extraction is available now from the Keysight Service Organization DynaFET Characterization DC I-V SP Parasitic Extraction ANN Training knee walkout DynaFET Model Slide 40

41 References J. Xu, M. M. Iwamoto, J. Horn, D. E. Root, Large-signal FET model with multiple time scale dynamics from nonlinear vector network analyzer data, IEEE MTT-S International Microwave Symposium Digest, May, O. Jardel et al, An electrothermal model for AlGaN/GaN power HEMTs including trapping effects to improve large-signal simulation results on high VSWR, IEEE Transactions Microwave Theory and Techniques., vol. 55, Dec., D. E. Root, Future Device Modeling Trends, IEEE Microwave Magazine, Nov./Dec. 2012, pp D. E. Root, J. Xu, F. Sischka, M. Marcu, J. Horn, R.M. Biernacki, M. Iwamoto, Compact and Behavioral Modeling of Transistors from NVNA Measurements: New Flows and Future Trends, IEEE Custom Integrated Circuits Conference Digest San Jose, Sept Slide 41

42 References (2) 6. J. Xu, R. Jones, S. A. Harris, T. Nielsen, and D. E. Root, Dynamic FET Model DynaFET - for GaN Transistors from NVNA Active Source Injection Measurements, 2014 IEEE International Microwave Symposium, Tampa, June 7. J. Xu, S. Halder, F. Kharabi, J. McMacken, J. Gering, and D. E. Root, Global Dynamic FET Model for GaN Transistors: DynaFET Model validation and comparison to locally tuned models 83 rd IEEE ARFTG Conference Digest, June J. Xu and D. E. Root NVNA Characterization Enables DynaFET: an Advanced Compact Time-Domain FET Model, Nonlinear Vector Network Analyzer Users Forum, Tampa, June, T. S. Nielsen, M. Dieudonne, C. Gillease, D. E. Root, Doherty Power Amplifier Design in Gallium Nitride Technology Using a Nonlinear Vector Network Analyzer and X-Parameters, IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), D.E. Root J. Horn, J. Xu, M. Iwamoto, F. Sischka, and Y. Yanagimoto MOS-AK Workshop, December, 2010 San Francisco Slide 42