Large-Signal Network Analysis Technology for HF analogue and fast switching components

Transcription

1 Large-Signal Network Analysis Technology for HF analogue and fast switching components Applications This slide set introduces the large-signal network analysis technology applied to high-frequency components. These components can be analogue or digital. Indeed, due to the increased speed of digital signals, it becomes important to treat the digital signals more and more as analogue signals. In a separate presentation, the theoretical aspects of large-signal network analysis is explained. In this presentation, some examples are shown to give a flavor of what can be done, once the key information of the nonlinear behavior is measured. 1

2 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High-Speed digital PA design using waveform engineering Conclusions 2 2

3 Gate-Drain Breakdown Current Time (ns) º TELEMIC / KUL º transistor provided by David Root, Agilent Technologies - MWTC 3 Investigating transistor reliability under realistic operating conditions is the first application we show. On the above figures we see the voltage and current time domain waveforms as they appear at the gate and drain of a FET transistor. These measurements were done applying an excitation signal of 1GHz at the gate. The signal amplitude is increased until we see a so-called breakdown current. It shows up as a negative peak (20mA) for the gate current, and as an equal amplitude positive peak at the drain. We actually witness a breakdown current which flows from the drain towards the gate. This kind of operating condition deteriorates the transistor and is a typical cause of transistor failure. To our knowledge, the above figures show the first measurements ever of breakdown current under large-signal RF excitation. 3

4 Forward Gate Conductance Time (ns) º TELEMIC / KUL º transistor provided by David Root, Agilent Technologies - MWTC 4 Another similar measurement is shown here. This time the FET is biased at a less negative gate voltage then the one used for the breakdown measurements. We now see that the gate junction is turned on (forward conductance) by the large 1GHz input signal. We see a clipping of the gate voltage (which is behaving like a rectifier), with a positive peak of 50mA in the gate current. The drain current is clipped to 0mA on the low end, and at a value of 150mA at the high end (this occurs during the forward gate conductance). 4

5 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning PA optimization using Waveform Engineering System level characterization Scattering functions Memory effect Dynamic bias High-Speed digital PA design using waveform engineering Conclusions 5 5

6 Model Verification in CAE tool ADS v g i g v d i d Model Measured Incident Waves i g 0.06 i d v g v d Multi-line TRL Measured and Simulated Voltages and Currents 6 It is possible to use the measured incident waves as input to a model that exists in a CAE tool. The scattered waves are then simulated and compared to the measured waves. This allows to identify possible problems with the model. Of course, one should use realistic test signals to check the model under realistic conditions. The picture shows voltage and current at the gate and the drain, both simulated and measured. Also the dynamic load line is visualized (current versus voltage at the drain) and something similar at the gate (current versus the voltage at the gate). When the model does not correspond to the measurements, one can consider to tune the model against the large signal measurements. 6

7 LSNA Measurements in ICCAP: verification, optimization and extraction sweep of Power Vgs Vds Freq ICCAP specific input ADS netlist. Used, a.o., to impose the measured impedance to the output of the transistor in simulation 7 LSNA measurements can be made available in ICCAP for model verification and tuning purposes. In this example, LSNA measurements were performed on a MOSFET at different DC bias levels (V gs as well as V ds ) and applying various RF input power levels to verify the accuracy of a compact MOSFET model. The fundamental frequency is 2.4 GHz, frequencies are included up to the 8 th harmonic (19.2 GHz). Four sweeps are performed: input power, frequency (HB), V ds,dc and V gs,dc. The DUT was measured in a 50 Ohm environment, although different impedances are possible. IMPORTANT: if we want to make a fair comparison between LSNA measurements and simulations, we need to place the transistor (its model) during simulations in exactly the same environment as the DUT was during the measurements. Although the measurements are performed in a 50 Ohm environment, the load impedance experienced by the DUT is not exactly 50 Ohm. It is not purely resistive and it is frequency dependent. However, this is not a problem, because the the load impedance seen by the DUT can be derived directly from the LSNA measurements at all frequencies and as such taken into account. Also, although we set a certain input power at the microwave source, the input power at the level of the DUT is lower due to losses. Thus, in practice, after de-embedding, we use (1) the measured impedance at the level of the DUT and (2) the measured input power. In ICCAP we link to these measurement results using ADS s Data Access Component (DAC) and CITIfiles. We also link to the measured DC bias levels, that are corrected for cable resistance losses in the LSNA software. 7

8 Transistor De-embedding Equivalent circuit of the RF teststructure, including the DUT and layout parasitics Gate current / ma before after de-embedding Time/period 8 The purpose of the de-embedding technique is to shift the calibration reference planes closer to the DUT, in the above case, from the probe tips to the transistor itself. As such, one has to calculate the values of the 6 unknown parasitic components (between probe tips and transistor) that influence the RF behaviour of the DUT (as shown in the slide) and correct the measurement results accordingly. The admittances G 1, G 2 and G 3 represent the coupling via the metal interconnections and the silicon substrate between the pads of gate (=port1) and source, drain (=port2) and source, and gate and drain, respectively. Z 1 and Z 2 originate from the metal interconnection series impedances between port 1 and port 2, respectively, on one hand and the actual device-under-test on the other. Z 3 represents the ground leads towards the DUT. Thus, the first step in the large-signal de-embedding is to measure the S- parameters (LSNA used in VNA mode), at the defined frequency grid, of the on-wafer de-embedding structures and convert them to Y-parameters using a conversion table. In our example, we measured the de-embedding structures at f=2.4 GHz, 4.8 GHz,, 8*2.4=19.2 GHz. Subsequently, the resulting Y-parameters are then used to calculate the parasitic components (G 1, G 2, G 3, Z 1, Z 2, and Z 3 as shown in the slide) at all harmonic frequencies. Knowing these values, the voltages and currents can be calculated at the transistor eliminating the parasitics. 8

9 Input capacitance behavior V ds,dc =0.3 V V gs,dc =0.9 V V ds,dc =1.8 V Input loci turn clockwise, conform i=c*dv/dt 9 Let us take a look now at some large-signal measurement and simulation results. The figures show the instantaneous gate current versus the instantaneous gate voltage at different DC bias settings. These, so called, input loci turn clockwise, conform i=c.dv/dt. If the gate capacitance does not depend on the gate voltage, the input locus will be shaped like an ellipse. A distorted ellipse indicates that the gate capacitance depends on the gate voltage, as is the case for a MOSFET. The input locus immediately reveals whether the gate capacitance model is accurate or not. The results presented here indicate that the modelled and measured input loci show similar trends. However, the absolute model accuracy can still be improved by optimizing gate capacitance model parameters towards these measurement results, as will be shown later in this presentation. 9

10 Dynamic load line & transfer characteristic V ds,dc =0.9 V V gs,dc =0.3 V 10 Other important large-signal characteristics of a DUT are the transfer locus and dynamic loadline. They show the instantaneous output current versus instantaneous input voltage and output voltage, respectively (arrows indicate time progress). Observe that, for this operating condition,, the drain current is negative for a short period of time, due to the direct coupling between gate and drain through the gate-drain capacitances (overlap and fringing). In fact, there is a small current that flows directly from the gate to the drain (i=c*dv/dt, with dv/dt positive) when the gate voltage starts to increase after it has obtained its lowest value. Because the drain current is defined as being positive when flowing into the transistor, during a small period of time a negative drain current can be observed. The dynamic loadline and transfer locus turn counterclockwise and show hysteresis. The transfer locus clearly shows that the drain current does not follow the gate voltage instantaneously, due to finite charging and discharging times (mainly RC contribution, no contribution of non-quasi static effects yet at these frequencies). The opening of the dynamic loadline largely stems from the complex value of the load impedance as seen by the transistor. 10

11 Identifying modeling problems: extrapolation example SiGe HBT... v1mts_de v1sts time, ps v2mts_de v2sts time, ps meas. simul. i1mts_de i1sts i2mts_de i2sts time, ps time, ps SiGe HBT (model parameters extracted using DC measurements up to 1V) V be = 0.9 V; V ce =1.5 V; P in = - 6 dbm; f 0 = 2.4 GHz 11 This slide shows the effect of not taking into account a sufficient range of DC bias levels during the extraction of the model parameters. This example is provided with courtesy of the Alcatel Microelectronics and the Alcatel SEL Stuttgart Research Center teams. In a first step, model parameters for a SiGe HBT technology were extracted using DC bias-levels up to 1 V. However, during LSNA measurements, the maximum instantaneous voltage at port 1 was 1.15 V. These LSNA measurements were performed using realistic operating conditions, i.e. operating conditions that are used by the circuit designers. One clearly sees that the agreement between measured and modeled currents and voltages is far from good. From the simulated data one could, for example, wrongly conclude that the output current clips at high current levels, while this is just due to the limited range of DC bias levels used during model parameter extraction. Of course, there is also a large disagreement in the DC behavior above 1 V, as shown in the next slide. As long as you do not measure the large-signal behavior of your transistor under realistic large-signal RF operating conditions, you will not be able detect these kind of modeling problems. This example also shows that, during model parameter extraction, it is of paramount importance to consider the area of applications (and the corresponding boundaries), where the transistor will be used. 11

12 Identifying modeling problems: extrapolation example SiGe HBT SiGe HBT - DC characteristics (different V ce ) DCmeas1..Ice VbDC Measurement i2.i VbDC Simulation Alcatel Microelectronics and the Alcatel SEL Stuttgart Research Center teams are acknowledged for providing these data. 12 The agreement between measured and modeled DC characteristics of the SiGe HBT is accurate up to 1 V, but becomes worse for voltages larger than 1 V. Of course, this also has significant effects on the large-signal behavior of the DUT, as was shown in the previous slide. It is by measuring the large-signal behavior of the DUT with the LSNA and looking at the agreement between measured and modeled large-signal characteristics that this modeling issue was triggered. Now that we know the range of voltages that can appear instantaneously at the input of the transistor, we can take this information into account during model parameter extraction and obtain much better agreement between measurements and simulations. 12

13 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High-Speed digital PA design using waveform engineering Conclusions 13 13

14 Empirical Model Tuning Parameter Boundaries GaAs pseudomorphic HEMT gate l=0.2 um w=100 um MODEL TO BE OPTIMIZED Chalmers Model generators apply LSNA measured waveforms Power swept measurements under mismatched conditions º Dominique Schreurs, IMEC & KUL-TELEMIC 14 The approach of optimizing existing empirical models is pretty straightforward. For our example we use a so-called Chalmer s model. First one performs a set of experiments which covers the desired application (and its boundaries) of the model. This data is imported into a simulator. During a simulation, the measured incident voltage waves are applied to the model in the simulator. This model is using the parameters provided by the optimizer. 14

15 Using the Built-in Optimizer During OPTIMIZATION Voltage - Current State Space voltage current gate Time domain waveforms drain gate drain Frequency domain 15 The model parameters are then found by tuning them such that the difference between the measured and modeled scattered voltage waves is minimized. Note that one can often use the optimizers of the CAE tool for this purpose. As with all nonlinear optimizations, it is necessary to have reasonable starting values. For this purpose, one can use the values provided by a simplified version of the classical approaches. The figures above represent one of the initially modeled and measured gate and drain voltages and currents, and this in the time domain, the frequency domain and in a current-versus-voltage representation. Note especially the large discrepancy between the measured gate current and the one which is calculated by the initial model. 15

16 Verification of the Optimized Model AFTER OPTIMIZATION Voltage - Current State Space voltage current gate drain Time domain waveforms gate drain Frequency domain 16 The above figures represent the same data after optimization. Note the very good correspondence that is achieved. This indicates that the model is accurately representing the large-signal behavior for the applied excitation signals. 16

17 Waveform Engineering Block Diagram Source f 0 Sampling Converter DUT Test Set Filter Filter Filter Filter Data-Acquisition PC L O f 0 2f 0 3f 0 IRCOM Setup 17 Waveform engineering corresponds to the synthesis of different source and load conditions to enforce a certain shape of (usually) output voltage and current as a function of time. For example, for an optimal power added efficiency (PAE), one will try to have a low current at a high output voltage and vice versa. This is realized by presenting proper load conditions to a transistor for the different harmonics. To apply waveform engineering, a large-signal network analyzer must be extended with tuners to control impedances at the different harmonics. In this case active tuners for each harmonic were selected because this allows independent control of the impedances at 3 harmonics. Each loop samples the transmitted wave, changes its amplitude (usually decreases it) and its phase and reinjects it towards the component. In this way, a reflection factor is synthesized which is independent of the transmitted wave. 17

18 Example - Measured Waveforms MesFET Class F f 0 =1.8 GHz I ds0 =7 ma V ds0 = 6 V PAE 50% Waveform Engineering Z(f 0 )=130+j73 Ω Z(2f 0 )=1-j2.8 Ω Z(3f 0 )=20-j97 Ω PAE=84% º IRCOM / Limoges 18 Here the different voltages and currents at the gate and the drain can be observed for different power levels, for a MesFET transistor operating in class F mode. By proper impedance tuning, 84% PAE can be achieved. 18

19 Example - Performance Improvement erived Information from the V/I waveforms (swept input power at different terminations) Z(f 0 )=123+j72 Ω Z(2f 0 )=50 Ω Z(3f 0 )=50 Ω PAE 74% Z(f 0 )=123+j72 Ω Z(2f 0 )=2 - j 4.0 Ω Z(3f PAE 74% 0 )=50 Ω Z(f 0 )=123+j72 Ω Z(2f 0 )=2 - j 4.0 Ω Z(3f 0 )=21-96 Ω PAE 84% º IRCOM / Limoges 19 Measuring the voltages and currents at the gate and the drain, allows to derive all other kinds of quantities like output power, PAE, DC power consumption, dissipated power as function of input power and this for different tuner settings. The plots correspond to 3 different load conditions. 19

20 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 20 20

21 RFIC Amplifier Characterization using periodic modulation Modulation Source E 1 a 1 f 0 = 1.9 GHz Evaluation Board A 1 shows spectral regrowth Spectral regrowth on b 1 combined with measurement system mismatch Nonlinear pulling on source a 1 5 db E 1 21 In this part of the presentation, a set of periodic modulation tones are used to characterize a RFIC amplifier on an evaluation board. The set of periodic modulation tones emulate the statistics of a CDMA signal. A major advantage of a large-signal network analyzer is that it can measure the actual incident wave to the component under test. In the graph, it is seen that some spectral regrowth is present in the incident wave which was not present when measuring the source separately (5 db difference) due to some nonlinear interaction between source and component. As such one much be very careful when first measuring the signal generated by the source without any DUT connected and then assume that this is the excitation signal seen by the DUT after connecting it. 21

22 Transmission Characteristics Carrier Modulation A 1 B 2 Carrier Modulation Harmonic Distortion Compression Carrier Modulation 3rd harmonic Modulation 22 The figures represent the incident and transmitted time domain signals as they were measured at the signal ports of a 1.9GHz RFIC amplifier. The incident signal has characteristics similar to a CDMA signal. The transmitted signal clearly suffers from compression and harmonic distortion for large instantaneous input amplitudes. Another way of visualizing this behavior is a so-called dynamic harmonic distortion plot. This is interpreted in exact the same way as a classical harmonic distortion plot, but now the input amplitude does not change step-by-step (using a CW input signal) but changes very fast within the modulation period. The latter may reveal memory effects, as will be explained later. Note the compression characteristic for the fundamental. 22

23 Reflection Characteristics Carrier Modulation A 1 B 1 Carrier Modulation Carrier Modulation Harmonic Distortion Expansion 2nd harmonic Modulation 3rd harmonic Modulation 23 The figures above represent the incident and reflected time domain voltage waves as they were measured at the input port of a 1.9GHz RFIC amplifier. The incident signal has characteristics similar to a CDMA signal. The reflected signal clearly demonstrates expansion and harmonic distortion whenever the input amplitude is high. Again, another way of visualizing this behavior is a so-called dynamic harmonic distortion plot. Note the expansion characteristic for the fundamental. 23

24 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 24 24

25 Scattering Functions Provide component understanding Enable coupling in CAE fundamental higher harmonics 25 For a device under test (DUT), which is excited with a single dominant tone at the input, scattering functions are an appropriate way to model the component behavior. The S-parameters are a special case of these scattering functions, i.e. they correspond for small input signals, resulting in linear behavior of the device. The above setup shows how the scattering functions can be extracted. This setup uses additional synthesizers to inject travelling voltage waves at both ports of the device under test, both at the fundamental frequency and at higher harmonics. This setup also allows to tune the input and output match at the fundamental frequency using two tuners, while using a different match for the higher harmonics. Measurements must be performed for different amplitudes and phases in order to extract the scattering functions. This can be accomplished for example by injecting higher harmonics at either port 1 or port 2 using a switch and a 2 nd synthesizer or by injecting at the fundamental frequency at port 2 using a 3 rd synthesizer. The phase of synthesizers Hsynth and Fsynth2 is then randomized with respect to the phase of synthesizer Fsynth1, meanwhile keeping their amplitude constant. In addition to a LSNA, this flexible setup requires tuners, diplexers, amplifiers, synthesizers and a switch. 25

26 Nonlinear behavior and Scattering Functions Functions of (and independent bias settings) = ( + ) = = Index of: Port & harmonic Note: a s and b s are phase normalized quantities!! As shown before: for small-signal levels (linear) this reduces to (fundamental at port 2) =

27 Scattering Functions variation versus input power

28 Time domain waveforms Measured and simulated b-waves 0.2 ( ) ( )

29 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 29 29

30 Time domain ( ) Memory effects! ( Κ Κ ) ( ) ( ) ( ) ( ) ( ) = 30 30

31 Memory effects DUT behavior under 2 - Tone excitation Modulation frequency = 20 khz Modulation frequency = 620 khz

32 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 32 32

33 What is Dynamic Bias Behavior? Input Voltage V1 I2 Output Current DC 1 Freq. (GHz) DC 1 2 Freq. (GHz) Dynamic Bias Behavior Frequency Domain: Generation of Low Frequency Intermodulation Products Time Domain: Beating of the Bias 33 33

34 Dynamic Bias: Measurement Principle Bias 1 Supply Computer Bias 2 Supply Current Probe Dynamic Bias Data Acquisition RF Data Acquisition Current Probe TUNER 34 34

35 RFIC Example in Time Domain MultiLine TRL (V) Input Voltage Waveform Normalized Time Output Current Waveform (without Dynamic Bias) (ma) Normalized Time 35 35

36 Adding Measured Dynamic Bias (ma) Dynamic Bias Current Waveform Normalized Time (ma) Output Current Waveform (including Dynamic Bias) Normalized Time 36 36

37 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 37 37

38 High-Speed Digital Measurements System rise time 7ps Compare 12ps for 50GHz scope Some Gibbs phenomenon No (random) jitter No slow tail cable response corrected DUT: 40 Gb Data Amp at 1.25 GB/s 38 38

39 Bit stream measurement Scope/LSNA comparison highlights difference 39 39

40 Eye diagram measurement at 10 GB/s 40 40

41 Applications Transistor reliability Transistor model verification (ICCAP / ADS) Transistor model tuning System level characterization Scattering functions Memory effect Dynamic bias High Speed Digital PA design using waveform engineering Conclusions 41 41

42 LSNA and ATS tuners (Maury) Practical solution based on passive tuners LSNA Broadband Receiver Source Tuner Fixture Load Tuner Termination or Second source to minimize losses 42 In practice, passive tuners need to be as close as possible to the device under test. This complicates the calibration process, because one needs to take the changing tuner characteristics into account. On top of that, the device under test can be a transistor in a fixture. Therefore one also needs to de-embed the fixture. 42

43 Calibration process in LSNA Broadband Receiver Raw 1 Raw 2 Source Tuner Fixture Load Tuner P 1 T 1 T 1 D 1 D 2 T 2 T 2 P 2 Termination or Second source Step 1: Absolute calibration in DUT i plane (tuner in Z 0 position) = D i Raw i (tuner at Z 0 ) Step 2: SOL calibration (no THRU required) in Tuner i plane (tuner in Z 0 position) = T i Raw i (tuner at Z 0 ) Step 3: Tuner characterization (S-parameters) for all positions of interest = T i P i ( tuner positions, incl. Z 0 ) Proper combination of the above 3 steps allows to obtain fully calibrated data for any tuner position: D i Raw i (at any tuner position of interest) 43 In the ATS-LSNA software, a calibration process is implemented that requires the proper (S-parameter) characterization of the tuners at the different tuner positions, for the frequencies of interest. Due to the stability of the Maury tuners, these files can be used for a long time. Additionally, one needs to perform an absolute calibration in the device plane and a simple SOL (not thru) at the planes of the tuners. 43

44 ATS - LSNA Use: Calibration Support SOLT LRRM 44 Here the ATS interface is shown in combination with some dialog boxes used during the calibration of the LSNA. Presently SOLT and LRRM are supported. Multiline TRL can be provided under consulting. The advantage of using multiline TRL, is to be able to calibrate up to the level of a packaged RFIC. 44

45 ATS-LSNA Use: Load-pull measurements on RFIC Amplifier 45 The ATS-LSNA combination allows to select a load tuner position and to show the dynamic load line on top of measured DC I-V curves. The actual dynamic load line shows little variation of the voltage for large variations of the current and therefore the load is close to a short, as can be verified on the Smith Chart. 45

46 ATS-LSNA Use: Measurement Representations 46 The accurate voltages and currents or incident and reflected waves, measured and calibrated up to the DUT plane, can be visualized in different ways. 46

47 Conclusions LSNA opens complete new horizons to improve the design and testing process in different ways when nonlinear behavior is involved Contact Marc Vanden Bossche