Nonlinear characterization and modeling of low. power transistors

Transcription

1 Workshop WMB Nonlinear characterization and modeling of low frequency dispersive effects in power transistors R. Quéré (1), O. Jardel (2), A. Xiong (1), M. Oualli (2), T. Reveyrand (1), J.P. Teyssier (1), R. Sommet (1), J.C Jacquet (2), S. Piotrowicz (2) (1) MITIC/XLIM University of Limoges (2) MITIC/Thales 3-5 Lab -1-

2 Outline Characterization methods Thermal Issues Trapping effects Impact Ionization effects Conclusion -2-19/12/28

3 Challenges for the design of HPA Design of High Power Amplifiers requires accurate Non linear models that take into account: Strong Thermal constraints Parasitics effects such as Traps in HEMTs Impact Ionization limits in GaAs PHEMts To cope with Reliability issues Degradation of Large signal characteristics ti Rely on specialized characterizations tools -3-19/12/28

4 Characterization Tools -4-

5 Characterization of microwave devices In the modelling process, the characterization phase is preeminent, as some effects can only be put into evidence using specialized measurements techniques. DC and Pulsed I-V measurements CW and pulsed S-parameters meaasurements CW and pulsed Load-Pull frequency measurements CW and pulsed Load-Pull time domain measurements (LSNA) Low Frequency Z and S parameters measurements Two tone IM measurements. -5-

6 Pulsed Measurements of power devices g µ On Wafer performances Max current 5A Min current 1µA Max Voltage 12V S-parameters 1-4 GHz Température -65 C / 2 C Pulse duration > 3ns duty cycle >.5 % Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V -6-6

7 Principle of pulsed measurements - short pulses 4ns : quasi isothermal state - period : 6µs - starting point of the pulses is the quiescent bias point (Vgs,Vds) that defines the thermal and trapping gsaeo state of the device - small-signal RF during the steady state of the pulses - I(V) and S-Parameters are taken during the pulses -7-

8 Harmonic Load Pull ( Frequency domain analysis) 5Ω RF coupler coupler Lin Amp DC bias D U T HN Tuner DC bias 1 Mhz Synch 4 channel test set LO frequency synthesis BP Detection Filter Mixer VNA receiver operation mode : Heterodyne Principle + narrow BP IF filter Sequential Measurements of Harmonic components Hn No phase relationship measurements between Hn and Hn+1 Absolute power and power wave ratios Hn -8-

9 Load pull Time Domain Waveform Measurements Reference Comb generator For phase cal procedure RF coupler coupler Lin Amp DC bias D U T HN Tuner DC bias 5Ω 1 Mhz Sy nch Time equivalent 1-2 Mhz Comb sampling 1 Mhz 2 Mhz Synthesizer Gen head LP filter ADC Harmonic Sub 2 MHz Frequency Translation and compression into a 1 Mhz IF Bandwidth -9-

10 Pulsed LSNA-organisation -1-

11 Pulsed LSNA- The stroboscopic approach -11-

12 Pulsed LSNA- The set-up -12-

13 Thermal issues -13-

14 Thermal Behaviour Impact on PA Gain Average current Degradation of performances for a 1W X band PA Outpout t Power & PAE Junction Temperature Junction tempe erature ( C) Pin (dbm) Optimization of PAE allows to reach the relialbility constraints for space applications -14-

15 Electrothermal modeling of HBTs Ic ( A ) TRANSISTOR TAB PACKAGE BACKSIDE AuSn GaAs DCu DCu Abelfilm525E I (,, ) B = f1 VBE VBC T +55 C Package I (,, ) C = f2 VBE VBC T P = VCE IC + VBE IB Réseau I(V) [S] T( jω) = ZTH ( jω) P S(2,2) 1 µm 25 µm 28 µm 25 µm 15 µm 125 µm Vce ( V ) freq (1.GHz to 1.GHz) 8 Full electrothermal model requires the knowledge of Pout (dbm m) ) Gain (db) PAE, Pout, Gain PAE (%) Z TH ( ω ) Pin (dbm) -15-

16 Thermal modeling of HBTs & Packaging Experimental set up SIMULATION Thermal Model Electrical measurement of the thermal impedance ,E-7 1,E-6 1,E-5 1,E-4 1,E-3 1,E-2 1,E-1 3D finite element simulation HP4194A k DC Offset=V BE V BE + ~ v be R 2 C=2mF R 1 Model Comparison Model Order Reduction. C. X T R R R T = E. X = K. X V A11.T11 DD2 A11.P1 1/λ11 V DD1 1 T11 R R R + F u R 1 P1 T1 A1m.P1 1/λ1m 1 T1m A1m.T1m -16-

17 Zth extraction from electrical measurements ~ V ~ I Principle of the measurement of the input impedance ~ BE B V f ( I, T) ) ~ ~ BE = B T = Z ( ω). P th = f I B T + f T I B T Z in = Z iniso + ϕ. ~ II B ~ T. ~ I ~ ~ ~ P = VCE. IC + VCE. IC B ~ P ~ ~ = h fe.( V CE R L. I C ) I B ~ Z in = Z iniso + ϕ. Z th ( ω). h fe.( V CE R L. IC ) -17-

18 Ib (ma) Extraction of φ Vbe (V) Vbe (V) T( C) φ (V/ C) V ϕ BE ( I B ) = TT I Bo Ib (ma) -18-

19 Input impedance variation 5 4 Re{Zin} R L > V ce /I c R L = V ce /I c R L < V ce /I c ~ Z in -1 Im{Zin} 1 1E1 1E2 1E3 1E4 1E5 Frequency (Hz) Z + ϕ ω = Z + ϕ. Z ( ω ). h.( V R. I ) iniso. th fe CE L C Zin purely real if the condition (V CE - R L.I C) ) = is verified -19-

20 3D FE Simulation Static & Dynamic Transient regime at the selected points ,E-7 1,E-6 1,E-5 1,E-4 1,E-3 1,E-2 1,E-1 Hot points, temperature profile Homogeneous repartition of the power Useful tool for the design of microwave power transistors But huge calculation time and heavy computing ressources -2-19/12/28

21 Model Order Reduction Representation FEM Linear conductivity Real system 3D Modeling Thermal subcircuit Numerical system. C. T + K. T = F 1 A11.P1 P1 A1m.P1 1/λ11 1/λ1m A11.T11 1 T11 A1m.T1m 1 T1m T1 Circuit it synthesis Reduced Order Model MOR -21-

22 Comparison ANSYS vs MOR (static) The Ritz method for MOR guarantees that steady state temperature is reached /12/28

23 Comparison ANSYS vs MOR (dynamic) Transient regime The number of Ritz vectors determine the precision of the transient regime Computing time (3 nodes) ANSYS : 1 minutes (3 V) Ritz : immediate MOR provides a significant gain of computing time without loss of precision and allows the integration of the model in CAD softwares -23-

24 Influence of the mounting of the transistor Zin Ritz MOR 5 Re{Zth Kovar} 5 % Re{Zth Cu} Mounting impact Im{Zth Cu} Time constants of the transistor -1 Im{Zth Kovar}

25 Low Frequency S-parameters for a HBT 1 Magnitude S11 (db) E1 db( S11) 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 1E8 12 (db) Magnitude S Measures -2 1E1 ET model Isothermal model db( S12) 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 1E8 5 2 Phase S ϕ ( S ) 12 ( ) Phase S ϕ( S12) -2 1E1 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 1E8-2 1E1 1E2 1E3 1E4 1E5 1E6 1E7 freq, Hz 1E /12/28

26 Trapping Effects -26-

27 GaN HEMTs Characterization Some issues of GaN HEMTs - Various electrical effects (traps, thermal) which cover a large frequency band from BF to RF - Serously impact the power behavior Useful characterization tools: - Pulsed I-V and S-parameters - Load Pull frequency domain measurements - Load Pull time domain measurements (LSNA) -27-

28 Trapping Effects (1/3) Origin: Chemical defects which induce electrical defects. Impact: Slow current transient Ids= f (Vgs, Vds) Ids= f(vgs, Vds, trapping state, t ) -28-

29 Trapping Effects (2/3) Origin: Chemical defects which induce electrical defects. Impact: Slow current transient Ids= f (Vgs, Vds) Ids= f(vgs, Vds, trapping state, t ) fast capture -29-

30 Trapping Effects (3/3) Origin: Chemical defects which induce electrical defects. Impact: Slow current transient Ids= f (Vgs, Vds) Ids= f(vgs, Vds, trapping state, t ) Fast t capture (~ ns) Slow emission (up to second) -3-

31 Evidence of trapping effects Gate-lag: decrease of drain current Drain-lag: increase of Vknee g µ Vgs=+1. V.8 Vgs= +.nv.8 Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V.6 Vgs=-6. V Vgs=-7. V Vgs=-8. V.6 Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V.4 Vgs=-5. V Vgs=-6. V Vgs=-7. V.4 Vgs=-8. V Vgs=-8V to +1V, Vgs=-8V, Vds=2V Vgs=-8V to +1V, Vgs=-8V, Vds=25V Vgs=-8V to +1V, Vgs=-8V, Vds=3V Vgs=-8V to +1V, Vgs=-8V, Vds=35V Gate-lag Vert (Vgs=V,Vds=V) rouge (Vgs=-8 V, Vds=V) Mise en évidence des pièges During the pulses capture takes place, emission i freezed Drain-lag Vgs=-8 V, Vds=15 15, 2, 25, 3V τcapture << t IMPULSION << τémission -31-

32 Nonlinear electrothermal model with trapping effects Ibk Igd(T ) Lg Rg Cgd Rgd Rd(T ) Ld Cpg Vgs Vds Cpd Igs(T ) Cgs Gate- & Drain-lag Vgs_int Ids (Vgs_int(t-τ), Vds(t), T ) Cds Ri Transistor intrinsèque Rs(T ) Ls -Nonlinear capacitances -Current sources -Thermal dependence -Trapping sub circuits -32-

33 d Mesure Modele x75 POLAR Vgs=-4.41 V, Vds= V, Id =+.163 A Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts Cgs_1D Vgs 6,E-13 5,E-13 4,E-13 3,E-13 2,E-13 1,E-13,E+ Mesure Modele Cgd_1D Vgd 1,4E-13 1,2E-13 1,E-13 8,E-14 6,E-14 4,E-14 2,E-14,E+ 1,6 1,55 1,5 1,45 1,4 1,35 1,3 1,25 1,2 y = -,24x + 1, ,5E-14 3,E-14 2,5E-14 2,E-14 1,5E-14 1,E-14 5,E-15,E+ y= 1,6E-16+1,4973E-16*EXP(T/26,3157) 16 1,4973E 16 EXP(T/26,3157) C²S² Steps of the modeling process Étapes de modélisation db (S(2,1)) db (S(1,2)) Modèle petit-signal Modèle I-V Capacités NL Modèle thermique Modèles de pièges S(1,1) ; S(2,2) freq, GHz Phase (S(1,2)) Pha se (S(2,1)) freq, GHz freq, GHz freq, GHz Ids (A) Vds (V) Id en Amperes Cgs (F) Cgd (F) Idss Is_gs 6.E-2 5.9E-2 5.8E E-2 5.6E-2 5.5E-2 5.4E-2.E+ 2.E-6 4.E-6 6.E-6 8.E-6 1.E- k Vds + k + Vgs_int Rfill Vgs Vds Rempty C Vds freq (2.GHz to 4.GHz) Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Dgs=f(Vgs) Dgd=f(Vgd) Ids=f(Vgs,Vds) Cgs=f(Vgs) Cgd=f(Vgd) Dgs=f(Vgs) Dgd=f(Vgd) g Ids=f(Vgs,Vds,T) Rs=f(T) Rd=f(T) Rgd=f(T) Ids=f(Vgs_pièges,Vds,T) Various parasitics effects are successively added -33-

34 Thermal effects modelled through 3D FE simulation Thermal simulations (3-5 lab) Zth [ C/W] Heating as a function of time HEMT 1t8x75_35µm - 7W/mm_3 C GaN1.2µm/SiC44µm/AuSn45µm/Al2mm ANSYS FIT RC 1.E-3 1.E-2 1.E-1 1.E+ 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 temps [µs] Mise en équation avec des formes exponentielles Thermal subcircuit R1 R2 R3 R4 R5 TEMP = 22,8.(1-e-t/τ1) +217(1e 21,7.(1-e-t/τ2) + 7.(1-e-t/τ3) + C1 C2 C3 C4 C5 I = P dissipée U=T chuck_ C T C -34-

35 Transistor parameters dependence on temperature various temperatures Thermal laws Id en Amperes Id en Am mperes x75 POLAR Vgs=+.163 V, Vds=+1.97mV, Id =-.55mA Vgs=+1. V Vgs= +.nv Vgs=-1. V Vgs=-2. V Vgs=-3. V Vgs=-4. V Vgs=-5. V Vgs=-6. V Vgs=-7. V Vgs=-8. V Vds en Volts. 25 C x75 POLAR Vgs=+.165 V, Vds=+9.79mV, Id =-.44mA Rs, Rd Idss Rd y =.49x Rs y =.29x T C. Equations Thermal parameters - Access resistances - Current sources - Diodes. Rs= Rs + α _Rs.T Rd= Rd + α_rd.t T Vgs=+1. V Vgs= +.nv Idss= Idss Vgs=-1. V Vgs=-2. V + Idss t.t y = -.8x Vgs=-3. V Vgs=-4. V P=P Vgs=-5. V Vgs=-6. V +P t.t Vgs=-7. V Vgs=-8. V Ngs=Ngs +Ngs t.t Vds en Volts 15 C T C. Ngd=Ngd +Ngd t.t Isgs=Isgs +Isgs t.e (T/Tsgs) Isgd=Isgd +Isgd t.e (T/Tsgd) -35-

36 Topology of the trapping effects model Trapping effects modify the gate command (back gating) transients on Vgs Transients of the drain current Charge of the capacitance= Ionized traps Charge through Rcapture, Emission through Rémission Diode= dissymetry of the capture and emission process Tuning of the magnitude of the trapping effects Fundamental assumption : dissymetry of the capture and emission process -36-

37 The model takes the knee walk out into account Measured Drain Lag Ids (A/m mm) Vgs=-7V, Vds=25V Vgs=-7V, Vds=V Ids (A/m mm) Simulations drain-lag ON/OFF Vds (V) Pulsed Measurements - Vgs=-7V, Vds=V V (bleu) - Vgs=-7V, Vds=25V (rouge) Vds (V) Simulated I-V Vgs=-7V, Vds=V Vgs=-7V, Vds=25V (rouge) Vgs=-7V, Vds=25V (bleu) -37-

38 Large signal impact of traps (1) Load pull measurements at various loads 3 4 1: Z 1 OPT 2 2 : Z 5 2_VSWR= : Z 3_VSWR=2.5 4 :Z 4_VSWR=1.6 5: Z 5_VSWR=2.5 6: Z 6 _ VSWR=2.5 Class AB, Vds=25 V, DC Bias, RF CW, 1 GHz -38-

39 Large signal impact of traps (2) Load tuned for optimum power Load.8 Pièges ON Pièges OFF Mesure Zload int.i reseau_iv_sdd..ids_ cycle (. to.) indep(cycle) X1.Vd_int PAE(%) 2 IDS (ma) Phase (Gamma a_in) Pin (dbm) 3 Pin (dbm).95 Pin (dbm) Gain(dB) Pin (dbm) Pout (W) Pin (W) in) Mag (Gamma_i Pin (dbm)

40 Explanantion of the decrease of the average current 22 ID DS (ma) Pin (dbm) 25-4-

41 Explanantion of the decrease of the average current 22 ID DS (ma) Pin (dbm)

42 Explanantion of the decrease of the average current 22 ID DS (ma) Pin (dbm)

43 Explanantion of the decrease of the average current 22 ID DS (ma) Pin (dbm)

44 Validation of the model with mismatched loads TOS=1,6 Load.8 Pièges ON Pièges OFF Mesure Zload s_int.i reseau_iv_sdd..id cycle (. to.) -16 indep(cycle) X1.Vd_int PAE(%) IDS (ma) Phase (Gamma in) Pin (dbm) 2.5 Pin (dbm).98 Pin (dbm) Gain(dB) 19 Pout (W) Pin (dbm) Pin (W) Mag (Gamma_in) Pin (dbm)

45 Validation of the model with mismatched loads TOS=2,5.8 Pièges ON Pièges OFF Mesure Zload Load reseau_iv_sdd d..ids_int.i cycle (. to.) indep(cycle) X1.Vd_int PAE(%) 2 1 ) IDS (ma) Phase (Gamma a_in) Pin (dbm) 2.5 Pin (dbm).85 Pin (dbm) Gain(dB) 1 8 Pout (W) Pin (dbm) Pin (W) -45- Mag (Gamma_in) Pin (dbm)

46 LSNA Measurements 5 GHz, 25V, dc/cw Igs Igs Ids (ma) Vgs Vds Vgs Vds Pe (dbm) -46- Vds Ids Ids Ids Pièges ON Pièges OFF Mesure TOS 4 5dB compression TOS 3,3 7dB compression TOS 2 8dB compression

47 Design of a 2 stages AlGaN/GaN MMIC HPA Output power, PAE & Gain at 9 GHz Drain Bias 32V ) Power (dbm m) & gain (db) 5 45 Pout gain PAE Input Power (dbm) PAE (%) Pout = 47.7 dbm ( 58 W) PAE = 38 % 6.5 W/mm Chip size : 16.5 mm² 43x38 µm² 1 st stage : 2.4 mm 2 nd stage : 8.96 mm Gain = 14.6 db =23A State-of-the-Art Output Power with Vds = 32V, Ids 2.3A AlGaN/GaN N MMIC HPA at X Band -47-

48 Impact Ionization -48-

49 Impact Ionization in GaAs HEMTs [ ] R Y 22.2A.15 4x75 POLAR Vgs= V, Vds=+6.7 V, Id =+41.25µA Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V Vgs=+.75 V.1 Id en Amperes ( 5.5 I DS ( V ) DS 5V Vds en Volts I Interaction between II and Traps [ Y ] Temperature dependence 22 Frequency dispersion of output conductance /12/28

50 PHEMT GaAs/GaInAs Model for Impact Ionization Impact ionization i is frequency dependent d Model with impact ionization source Model with impact ionization filtered around 2 GHz Lowpass filter with a cut-off frequency of 2 GHz -5-

51 Conclusions Dispersive effects have a strong impact on transistors performances Thermal Effects in all devices Trapping effects in HEMTs (GaN and GaAs) Impact ionization effects coupled with trapping effects Require specialized characterization tools Pulsed I-V and S-parameters measurements Load Pull Frequency and Time Domains Low Frequency Characterization Physical and thermal simulation Need further investigations for checking the consistency of different kinds of characterization and modeling. To provide usefull tools for the technology assessment and improvement as well as optimization of PA performances /12/28