8-Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC08

Transcription

1 a FEATURES Fast Settling Output Current: ns Full-Scale Current Prematched to LSB Direct Interface to TTL, CMOS, ECL, HTL, PMOS Nonlinearity to.% Maximum over Temperature Range High Output Impedance and Compliance: V to + V Complementary Current Outputs Wide Range Multiplying Capability: MHz Bandwidth Low FS Current Drift: ppm/ C Wide Power Supply Range:. V to V Low Power Consumption: V Low Cost Available in Die Form GENERAL DESCRIPTION The DAC series of -bit monolithic digital-to-analog converters provide very high-speed performance coupled with low cost and outstanding applications flexibility. Advanced circuit design achieves ns settling times with very low glitch energy and at low power consumption. Monotonic multiplying performance is attained over a wide -to- reference current range. Matching to within LSB between reference and -Bit, High-Speed, Multiplying D/A Converter (Universal Digital Logic Interface) DAC full-scale currents eliminates the need for full-scale trimming in most applications. Direct interface to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic input. High voltage compliance complementary current outputs are provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak output swing. In many applications, the outputs can be directly converted to voltage without the need for an external op amp. All DAC series models guarantee full -bit monotonicity, and nonlinearities as tight as ±.% over the entire operating temperature range are available. Device performance is essentially unchanged over the ±. V to ± V power supply range, with mw power consumption attainable at ± V supplies. The compact size and low power consumption make the DAC attractive for portable and military/aerospace applications; devices processed to MIL-STD-, Level B are available. DAC applications include -bit, µs A/D converters, servo motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high-speed modems and other applications where low cost, high speed and complete input/ output versatility are required. FUNCTIONAL BLOCK DIAGRAM MSB LSB V+ B B B B B B B7 B 7 DAC V REF (+) BIAS NETWORK CURRENT SWITCHES V REF ( ) REFERENCE AMPLIFIER COMP V Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box, Norwood, MA -, U.S.A. Tel: 7/-7 Fax: 7/-7 Analog Devices, Inc.,

2 DAC SPECIFICATIONS ELECTRICAL CHARACTERISTICS V S = V, I REF =. ma, C T A + C for DAC/A, C T A +7 C for DACE and DACH, C to + C for DACC, unless otherwise noted. Output characteristics refer to both and.) DACA/H DACE DACC Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Resolution Bits Monotonicity Bits Nonlinearity NL ±. ±. ±. % FS Settling Time t S To ± / LSB, ns All Bits Switched ON or OFF, T A = C Propagation Delay Each Bit t PLH T A = C ns All Bits Switched t PHL ns Full-Scale Tempco TCI FS ± ± ± ± ± ± ppm/ C DACE ± Output Voltage Compliance V OC Full-Scale Current (True Compliance) Change </ LSB, V R OUT > MΩ typ Full Range Current I FR V REF =. V ma R, R =. kω T A = C Full Range Symmetry I FRS I FR I FR ±. ± ± ± ± ± µa Zero-Scale Current I ZS... µa Output Current Range R R, R =. kω... ma R V REF = +. V, V = V V REF = +. V,... ma V = V Output Current Noise I REF = ma na Logic Input Levels Logic V IL = V... V Logic Input V IL V Logic Input Current = V Logic I IL V IN = V to +. V µa Logic Input I IH V IN =. V to V... µa Logic Input Swing V IS V = V V Logic Threshold Range V THR V S = ± V V Reference Bias Current I µa Reference Input di/dt R EQ = Ω ma/µs Slew Rate R L = Ω C C = pf See Fast Pulsed Ref. Info Following. Power Supply Sensitivity PSSI FS+ V+ =. V to V ±. ±. ±. ±. ±. ±. % /% V+ PSSI FS V =. V to V ±. ±. ±. ±. ±. ±. % /% V I REF =. ma Power Supply Current I+ V S = ± V, I REF =. ma ma I ma I+ V S = + V, V, ma I I REF =. ma ma I+ V S = ± V, ma I I REF =. ma ma Power Dissipation P D ± V, I REF =. ma mw + V, V, I REF =. ma mw ± V, I REF =. ma mw NOTES Guaranteed by design. Specifications subject to change without notice.

3 TYPICAL ELECTRICAL CHARACTERISTICS V S = V, and I REF =. ma, unless otherwise noted. Output characteristics apply to both and.) All Grades Parameter Symbol Conditions Typical Unit Reference Input Slew Rate di/dt ma/µs Propagation Delay t PLH, t PHL T A = C, Any Bit ns Settling Time t S To ± / LSB, All Bits Switched ON or OFF, ns T A = C Specifications subject to change without notice. DAC ABSOLUTE MAXIMUM RATINGS Operating Temperature DACAQ, Q C to + C DACHQ, EQ, CQ, HP, EP C to +7 C DACCP, CS C to + C Junction Temperature (T J ) C to + C Storage Temperature Q Package C to + C Storage Temperature P Package C to + C Lead Temperature (Soldering, sec) C V+ Supply to V Supply V Logic Inputs V to V plus V V to V+ Analog Current Outputs (at V S = V) ma Reference Input (V to V ) V to V+ Reference Input Differential Voltage (V to V ) ± V Reference Input Current (I ) ma Package Type JA JC Unit -Lead Cerdip (Q) C/W -Lead Plastic DIP (P) C/W -Terminal LCC (RC) 7 C/W -Lead SO (S) C/W NOTES Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. θ JA is specified for worst-case mounting conditions, i.e., θ JA is specified for device in socket for cerdip, Plastic DIP, and LCC packages; θ JA is specified for device soldered to printed circuit board for SO package. ORDERING GUIDE Temperature Package Package # Parts Per Model NL Range Description Option Container DACAQ ±.% C to + C Cerdip- Q- DACAQ /C ±.% C to + C Cerdip- Q- DACHP ±.% C to 7 C P-DIP- N- DACHQ ±.% C to 7 C Cerdip- Q- DACQ ±.% C to + C Cerdip- Q- DACQ /C ±.% C to + C Cerdip- Q- DACRC/C ±.% C to + C LCC- E- DACEP ±.% C to 7 C P-DIP- N- DACEQ ±.% C to 7 C Cerdip- Q- DACES ±.% C to 7 C SO- R-A (Narrow Body) 7 DACES-REEL ±.% C to 7 C SO- R-A (Narrow Body) DACCP ±.% C to + C P-DIP- N- DACCQ ±.% C to 7 C Cerdip- Q- DACCS ±.% C to + C SO- R-A (Narrow Body) 7 DACCS-REEL ±.% C to + C SO- R-A (Narrow Body) DACNBC ±.% C DICE DACGBC ±.% C DICE DACGRBC ±.% C DICE NOTES Devices processed in total compliance to MIL-STD-. Consult factory for data sheet. For availability and burn-in information on SO and PLCC packages, contact your local sales office. The DAC contains transistors. Die size mil x 7 mil =, square mils. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

4 DAC -Lead Dual-In-Line Package (Q and P Suffix) PIN CONNECTIONS -Lead SO (S Suffix) DACRC/ -Lead LCC (RC Suffix) V COMPENSATION V REF ( ) V REF (+) V+ V REF (+) V REF ( ) B LSB B7 B NC COMP V REF ( ) V+ COMP V V REF (+) MSB B B B 7 B LSB B7 B 7 7 B B B B NC B B B V 7 B B B NC MSB B B V+ NC B LSB B7 B MSB NC = NO CONNECT DICE CHARACTERISTICS ( C Tested Dice Available)... V.. BIT (MSB). BIT 7. BIT. BIT. BIT. BIT. BIT 7. BIT (LSB). V+. V REF (+). V REF ( ). COMP DIE SIZE.7. inch,,7 sq. mils (.. mm,. sq. mm)

5 WAFER TEST LIMITS V S = V, I REF =. ma; T A = C, unless otherwise noted. Output characteristics apply to both and.) DACN DACG DACGR Parameter Symbol Conditions Limit Limit Limit Unit DAC Resolution Bits min Monotonicity Bits min Nonlinearity NL ±. ±. ±. % FS max Output Voltage V OC Full-Scale Current V max Compliance Change < / LSB V min Full-Scale Current I FS or V REF =. V... ma max I FS R, R =. kω... ma min Full-Scale Symmetry I FSS ± ± ± µa max Zero-Scale Current I ZS µa max Output Current Range I FS or V = V, V REF = + V... ma min V = V, I FS V REF = + V... ma min R, R =. kω Logic Input V IL... V max Logic Input V IH V min Logic Input Current = V Logic I IL V IN = V to +. V ± ± ± µa max Logic I IH V IN = +. V to + V ± ± ± µa max Logic Input Swing V IS V = V V max V min Reference Bias Current I µa max Power Supply PSSI FS+ V+ = +. V to + V... % FS/% V max Sensitivity PSSI FS V =. V to V I REF =. ma Power Supply Current I+ V S = ± V... ma max I REF. ma µa max Power Dissipation P D V S = ± V mw max I REF. ma NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

6 DAC +V REF V R IN TYPICAL VALUES: R IN = k +V IN = V R EQ R P OPTIONAL RESISTOR FOR OFFSET INPUTS NO CAP R L R L ma.ma.ma ( ) I REF = ma ( ) Figure. Pulsed Reference Operation Figure. True and Complementary Output Operation C +V R = k C =. F C, C =. F C R mv V DAC 7.V.V V A C V MIN mv ns/division ns Figure. Burn-in Circuit Figure. LSB Switching ALL BITS SWITCHED ON.V V.V LOGIC INPUT V.V.V.mA OUTPUT /LSB SETTLING V +/LSB.mA mv ns mv ns R EQ R L = C C = ns/division SETTLING TIME FIXTURE I FS = ma, R L = k /LSB = A ns/division Figure. Fast Pulsed Reference Operation Figure. Full-Scale Settling Time

7 Typical Performance Characteristics DAC I FS, OUTPUT CURRENT ma T A = T MIN TO T MAX ALL BITS HIGH LIMIT FOR V = V LIMIT FOR V = V..... I REF, REFERENCE CURRENT ma PROPAGATION DELAY ns LSB = 7. A LSB = na I FS, OUTPUT FULL SCALE CURRENT ma RELATIVUTPUT db R = R = k R L ALL BITS ON V R = V. C C = pf, V IN =.V p p CENTERED AT +.V LARGE SIGNAL. C C = pf, V IN = mv p p CENTERED AT +mv SMALL SIGNAL FREQUENCY MHz TPC. Full-Scale Current vs. Reference Current TPC. LSB Propagation Delay vs. I FS TPC. Reference Input Frequency Response.. T A = T MIN TO T MAX ALL BITS ON.. OUTPUT CURRENT ma NOTE: POSITIVE COMMON-MODE RANGE IS ALWAYS (V+).V V = V V = V V+ = +V I REF = ma I REF = ma LOGIC INPUT A.... V TH V..... I REF =.ma. V, REFERENCE COMMON-MODE VOLTAGE V LOGIC INPUT VOLTAGE V TEMPERATURE C TPC. Reference Amp Common- Mode Range TPC. Logic Input Current vs. Input Voltage TPC. V TH vs. Temperature.. T A = T MIN TO T MAX ALL BITS ON.. OUTPUT CURRENT ma... V = V V = V I REF = ma... I REF = ma.. I REF =.ma. OUTPUT VOLTAGE V OUTPUT VOLTAGE V SHADED AREA INDICATES PERMISSIBLUTPUT VOLTAGE RANGE FOR V = V. I REF.mA. FOR OTHER V OR I REF. SEUTPUT CURRENT VS. OUTPUT VOLTAGE CURVE. TEMPERATURE C OUTPUT CURRENT ma..... I REF =.ma. V = V. V = V B B B B LOGIC INPUT VOLTAGE V B NOTE: B THROUGH B HAVE IDENTICAL TRANSFER CHARACTERISTICS. BITS ARE FULLY SWITCHED WITH LESS THAN / LSB ERROR, AT LESS THAN mv FROM ACTUAL THRESHOLD. THESE SWITCHING POINTS ARE GUARANTEED TO LIE BETWEEN.V AND.V OVER THE OPERATING TEMPERATURE RANGE (VLC =.V). TPC 7. Output Current vs. Output Voltage (Output Voltage Compliance) TPC. Output Voltage Compliance vs. Temperature TPC. Bit Transfer Characteristics 7

8 DAC POWER SUPPLY CURRENT ma 7 ALL BITS HIGH OR LOW I I+ POWER SUPPLY CURRENT ma 7 BITS MAY BE HIGH OR LOW I WITH I REF = ma I WITH I REF = ma I WITH I REF =.ma I+ POWER SUPPLY CURRENT ma 7 ALL BITS HIGH OR LOW V = V I REF =.ma V+ = +V I I+ V+, POSITIVE POWER SUPPLY V dc V, NEGATIVE POWER SUPPLY V dc TEMPERATURE C TPC. Power Supply Current vs. V+ TPC. Power Supply Current vs. V TPC. Power Supply Current vs. Temperature BASIC CONNECTIONS +V REF V IN V IN R +V REF I IN R IN R (OPTIONAL) I REF I REF PEAK NEGATIVE SWING OF I IN HIGH INPUT IMPEDANCE +V REF MUST BE ABOVE PEAK POSITIVE SWING OF V IN MSB LSB B B B B B B B7 B I REF V REF (+) +V REF 7 (R) R V REF ( ). F I FR = +V REF + = I FR FOR ALL LOGIC STATES V C C. F COMP V+ V V+ FOR FIXED REFERENCE, TTL OPERATION, TYPICAL VALUES ARE: V REF =.V =.k R = C C =. F = V (GROUND) Figure 7. Accommodating Bipolar References Figure. Basic Positive Reference Operation MSB LSB B B B B B B B7 B I REF =.ma.k.k FULL RANGE HALF-SCALE +LSB HALF-SCALE HALF-SCALE LSB ZERO-SCALE +LSB ZERO-SCALE B B B B B B B7 B ma ma Figure. Basic Unipolar Negative Operation

9 DAC.V MSB LSB B B B B B B B7 B.k I REF (+) =.ma.k POS. FULL RANGE POS. FULL RANGE LSB ZERO-SCALE +LSB ZERO-SCALE ZERO-SCALE LSB NEG. FULL-SCALE +LSB NEG. FULL-SCALE B B B B B B B7 B Figure. Basic Bipolar Output Operation V REF V k POT LOW T.C..k I REF (+) ma k V APPROX k V REF I FS R V REF NOTE SETS I FS ; R IS FOR BIAS CURRENT CANCELLATION. Figure. Recommended Full-Scale Adjustment Circuit Figure. Basic Negative Reference Operation k V V V O REF* MSB LSB B B B B B B B7 B.k.k V+ V C C I O.k +V OP7 POS. FULL RANGE ZERO-SCALE NEG. FULL-SCALE + LSB NEG. FULL-SCALE B B B B B B B7 B *OR ADR +V V V Figure. Offset Binary Operation R L OP7 TO +I FR R L I FR = I REF FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO (PIN ); CONNECT (PIN ) TO GROUND. Figure. Positive Low Impedance Output Operation OP7 TO I FR R L I FR = FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC), CONNECT NONINVERTING INPUT OF OP AMP TO (PIN ); CONNECT (PIN ) TO GROUND. Figure. Negative Low Impedance Output Operation R L I REF V TH =.V V CMOS V TH = 7.V V ECL CMOS, HTL, NMOS V+ TTL, DTL V TH =.V.k k k.k. F A k N k N TO PIN A k N k N TO PIN.k R A.V TEMPERATURE COMPENSATING CIRCUITS Figure. Interfacing with Various Logic Families

10 DAC APPLICATION INFORMATION REFERENCE AMPLIFIER SETUP The DAC is a multiplying D/A converter in which the output current is the product of a digital number and the input reference current. The reference current may be fixed or may vary from nearly zero to. ma. The full-scale output current is a linear function of the reference current and is given by: I FR = I REF, where I REF = I In positive reference applications, an external positive reference voltage forces current through R into the V REF(+) terminal (Pin ) of the reference amplifier. Alternatively, a negative reference may be applied to V REF( ) at Pin ; reference current flows from ground through R into V REF(+) as in the positive reference case. This negative reference connection has the advantage of a very high impedance presented at Pin. The voltage at Pin is equal to and tracks the voltage at Pin due to the high gain of the internal reference amplifier. R (nominally equal to R) is used to cancel bias current errors; R may be eliminated with only a minor increase in error. Bipolar references may be accommodated by offsetting V REF or Pin. The negative common-mode range of the reference amplifier is given by: V CM = V plus (I REF kω) plus. V. The positive common-mode range is V+ less. V. When a dc reference is used, a reference bypass capacitor is recommended. A. V TTL logic supply is not recommended as a reference. If a regulated power supply is used as a reference, R should be split into two resistors with the junction bypassed to ground with a. µf capacitor. For most applications the tight relationship between I REF and I FS will eliminate the need for trimming I REF. If required, full-scale trimming may be accomplished by adjusting the value of R, or by using a potentiometer for R. An improved method of full-scale trimming which eliminates potentiometer T.C. effects is shown in the recommended full-scale adjustment circuit. Using lower values of reference current reduces negative power supply current and increases reference amplifier negative common-mode range. The recommended range for operation with a dc reference current is. ma to. ma. REFERENCE AMPLIFIER COMPENSATION FOR MULTIPLYING APPLICATIONS AC reference applications will require the reference amplifier to be compensated using a capacitor from Pin to V. The value of this capacitor depends on the impedance presented to Pin : for R values of.,. and. kω, minimum values of C C are, 7 and 7 pf. Larger values of R require proportionately increased values of C C for proper phase margin, so the ratio of C C (pf) to R (kω) =. For fastest response to a pulse, low values of R enabling small C C values should be used. If Pin is driven by a high impedance such as a transistor current source, none of the above values will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. For R = kω and C C = pf, the reference amplifier slews at ma/µs enabling a transition from I REF = to I REF = ma in ns. Operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. This technique provides lowest full-scale transition times. An internal clamp allows quick recovery of the reference amplifier from a cutoff (I REF = ) condition. Full-scale transition ( ma to ma) occurs in ns when the equivalent impedance at Pin is Ω and C C =. This yields a reference slew rate of ma/µs, which is relatively independent of R IN and V IN values. LOGIC INPUTS The DAC design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. This feature is made possible by the large input swing capability, µa logic input current and completely adjustable logic threshold voltage. For V = V, the logic inputs may swing between V and + V. This enables direct interface with V CMOS logic, even when the DAC is powered from a V supply. Minimum input logic swing and minimum logic threshold voltage are given by: V plus (I REF kω) plus. V. The logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (Pin, ). The appropriate graph shows the relationship between and V TH over the temperature range, with V TH nominally. above. For TTL and DTL interface, simply ground pin. When interfacing ECL, an I REF = ma is recommended. For interfacing other logic families, see preceding page. For general set-up of the logic control circuit, it should be noted that Pin will source µa typical; external circuitry should be designed to accommodate this current. Fastest settling times are obtained when Pin sees a low impedance. If Pin is connected to a kω divider, for example, it should be bypassed to ground by a. µf capacitor. ANALOG OUTPUT CURRENTS Both true and complemented output sink currents are provided where + = I FS. Current appears at the true ( ) output when a (logic high) is applied to each logic input. As the binary count increases, the sink current at pin increases proportionally, in the fashion of a positive logic D/A converter. When a is applied to any input bit, that current is turned off at Pin and turned on at Pin. A decreasing logic count increases as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must be connected to ground or to a point capable of sourcing I FS ; do not leave an unused output pin open. Both outputs have an extremely wide voltage compliance enabling fast direct current-to-voltage conversion through a resistor tied to ground or other voltage source. Positive compliance is V above V and is independent of the positive supply. Negative compliance is given by V plus (I REF kω) plus. V. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers. POWER SUPPLIES The DAC operates over a wide range of power supply voltages from a total supply of V to V. When operating at supplies of ± V or less, I REF ma is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode

11 DAC range, negative logic input range and negative logic threshold range; consult the various figures for guidance. For example, operation at. V with I REF = ma is not recommended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible; however, at least V total must be applied to ensure turn-on of the internal bias network. Symmetrical supplies are not required, as the DAC is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required: however, an artificial ground may be used to ensure logic swings, etc., remain between acceptable limits. Power consumption may be calculated as follows: P D = (I+) (V+) + (I ) (V ) A useful feature of the DAC design is that supply current is constant and independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size of the power supply bypass capacitors. TEMPERATURE PERFORMANCE The nonlinearity and monotonicity specifications of the DAC are guaranteed to apply over the entire rated operating temperature range. Full-scale output current drift is low, typically ± ppm/ C, with zero-scale output current and drift essentially negligible compared to / LSB. The temperature coefficient of the reference resistor R should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC decrease approximately % at C; at + C an increase of about % is typical. The reference amplifier must be compensated by using a capacitor from pin to V. For fixed reference operation, a. µf capacitor is recommended. For variable reference applications, see Reference Amplifier Compensation for Multiplying Applications section. MULTIPLYING OPERATION The DAC provides excellent multiplying performance with an extremely linear relationship between I FS and I REF over a range of µa to ma. Monotonic operation is maintained over a typical range of I REF from µa to. ma. SETTLING TIME The DAC is capable of extremely fast settling times, typically ns at I REF =. ma. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only ns for each of the bits. Settling time to within / LSB of the LSB is therefore ns, with each progressively larger bit taking successively longer. The MSB settles in ns, thus determining the overall settling time of ns. Settling to -bit accuracy requires about ns to 7 ns. The output capacitance of the DAC including the package is approximately pf, therefore the output RC time constant dominates settling time if R L > Ω. Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for I REF values. The principal advantage of higher I REF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve ± µa, therefore a kω load is needed to provide adequate drive for most oscilloscopes. The settling time fixture shown in schematic labelled Settling Time Measurement uses a cascade design to permit driving a kω load with less than pf of parasitic capacitance at the measurement node. At I REF values of less than. ma, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from to provides an accurate indicator of settling time. This code change does not require the normal. time constants to settle to within ±.% of the final value, and thus settling times may be observed at lower values of I REF. DAC switching transients or glitches are very low and may be further reduced by small capacitive loads at the output at a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimizing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states;. µf capacitors at the supply pins provide full transient protection. FOR TURN-ON, V L =.7V FOR TURN-OFF, V L =.7V MINIMUM CAPACITANCE V L k F F +V Q V CL.7V. F V IN Q k F V OUT X PROBE +.V V V +V REF R 7 DAC. F k k V k.v. F. F. F +V V Figure 7. Settling Time Measurement

12 DAC OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead Plastic DIP (N-) -Lead Cerdip (Q-) PIN. (.) MAX. (.). (.). (.). (.). (.).7 (.)..7 (.77) (.). (.) BSC. (7.). (.). (.). (.). (.) MIN SEATING PLANE. (.). (7.). (.). (.). (.). (.). (.) MAX. (.) MIN. (.) MAX PIN. (.) MAX. (.). (.). (.)..7 (.7). (.) (.). (.7) BSC. (7.7). (.). (.). (.). (.) MIN SEATING PLANE. (.). (7.7). (.). (.) C /(B) -Lead SO (R-A) -Terminal Leadless Chip Carrier (E-).7 (.).7 (.) PIN. (.). (.).7 (.). (.). (.7) BSC. (.). (.). (.). (.). (.7). (.) SEATING PLANE. (.).7 (.). (.). (.). (.7). (.). (.). (.) SQ TOP VIEW. (.). (.). (.) MAX SQ. (.). (.7). (.).7 (.). (.).7 (.) R TYP.7 (.) REF. (.).7 BSC (.) REF. (.) BSC. (.). (.). (.) MIN. (.7). (.). (.7) BSC BOTTOM VIEW TYP. (.) BSC Revision History Location Page Data Sheet changed from REV. A to. Edits to SPECIFICATIONS Edits to ABSOLUTE MAXIMUM RATINGS Edits to ORDERING GUIDE Edits to WAFER TEST LIMITS Edit to Figure Edits to Figures and Replacement of SO- with R-A Package Outline PRINTED IN U.S.A.