A buck converter with adaptive on-time PFM control and adjustable output voltage

Transcription

1 Analog Integr Circ Sig Process (2012) 71: DOI /s MIXED SIGNAL LETTER A buck converter with adaptive on-time PFM control and adjustable output voltage Hyunseok Nam Youngkook Ahn Jeongjin Roh Received: 24 August 2010 / Revised: 5 September 2011 / Accepted: 11 October 2011 / Published online: 21 October 2011 Ó Springer Science+Business Media, LLC 2011 Abstract This letter proposes a new adaptive on-time pulse-frequency modulation (PFM) circuit that operates at a wide range of supply voltage levels and that can generate various output voltage levels compared to conventional circuits. The circuit s peak inductor current is well-controlled; the magnitude of the output ripple voltage is constant, even when the supply and output voltage levels are significantly different. Since the ripple voltage is a noise component, constant ripple voltage is important for predictable noise of a power management system. Keywords Buck converter Adaptive on-time (AOT) Constant on-time (COT) Pulse-frequency modulation (PFM) Inductor peak current 1 Introduction With an ever-increasing number of mobile devices in common use, the efficient use of power is an important issue [1 7]. In particular, many techniques have been studied to improve power efficiency when such devices are in stand-by mode, since they operate in this mode most of the time [8]. A simple way to increase power efficiency in stand-by mode is the constant on-time (i.e., fixed on-time) PFM method. This method does not require a sensing circuit, but the inductor peak current changes significantly in response to both the supply and output voltages [9]. This peak current variation affects the accuracy and ripple magnitude of H. Nam Y. Ahn J. Roh (&) Department of Electrical Engineering, Hanyang University, Ansan , Korea jroh@hanyang.ac.kr the output voltage. Since the ripple voltage is a noise component of the power supply, this variation makes filtering noise in a power-management system design difficult. Therefore, an adaptive on-time PFM control technique, rather than a constant one, is proposed. This technique produces little output ripple variation and improves power efficiency. Table 1 shows characteristics in relation to on-time control methods. Constant on-time (COT) can be implemented using a comparator and a simple on-time circuit to reduce the area and design complexity. However, due to the constant on-time, inductor peak-to-peak and output voltage ripples change significantly in relation to changes in supply voltage, output voltage, and load current. Adaptive on-time can be largely divided into fixed frequency and variable frequency methods. The AOT using the fixed frequency method can minimize voltage ripples against changes in supply voltage, output voltage, and load current. In addition, this method shows electromagnetic interference (EMI) problems can be minimized compared to other methods. However, the size of the entire system increases due to complicated sensing and control circuits. On the other hand, the AOT using the variable frequency method can reduce the system area as well as the complexity through the use of small-sized circuits. In addition, the magnitude of the output voltage ripples can be reduced against changes in supply voltage and output voltage [16]. However, the circuit in [16] was used under the assumption that the output voltage was fixed, which significantly limits the circuit s applications. This letter proposes a new type of adaptive on-time PFM circuit that does not need a complex current-sensing circuit and that can maintain a constant peak inductor current despite any variation in either supply or output voltage.

2 328 Analog Integr Circ Sig Process (2012) 71: Table 1 Comparison of the control methods Constant on-time Adaptive on-time [10 12] Fixed frequency method [13 15] Variable frequency method Fixed output voltage [16] Adjustable output voltage (proposed scheme) Area Small area due to simplicity Large area due to the sensing circuit Complexity Easy implementation Complexity increases due to the complex sensing circuit Output ripple voltage EMI Large ripple voltage due to changes in supply voltage, output voltage, and load current EMI problem is serious as f S changes are severe Small ripple voltage EMI problem is minimized due to constant f S Small area due to the simple sensing circuit Reduced complexity by using simple sensing circuit Ripple voltage is minimized only against changes in supply voltage EMI problem is slightly relieved compared to COT structures Ripple voltage is minimized against changes in both supply voltage and output voltage EMI problem is relieved by small changes in f S and small ripple voltage 2 Controller design Figure 1 shows a block diagram of the proposed PFM controller. If the output voltage (V O ) is lower than the reference voltage (V ref1 ), the comparator s output toggles to high, and this high signal turns the Qb of SR latch1 to low, which turns on the PMOS power transistor. Then, after an adaptively controlled delay time, the adaptive on-time circuit changes the RESET signal to high, which turns the Qb of SR latch1 to high and turns off the PMOS power transistor. At the same time, the Q of SR latch2 becomes high, which turns on the NMOS power transistor. The reverse current, which decreases overall efficiency, might occur if the NMOS power transistor stays on for too long. In order to prevent this, a reverse-current comparator (Comp2) is included in the controller [8, 16, 17]. Figure 2 presents the results of the HSPICE simulation of the control signals in Fig. 1. Figure 3 shows the proposed adaptive on-time circuit. The proposed circuit can adaptively control the on-time for various output and supply voltage levels, and, therefore, can generate different output voltages with very little change in the magnitude of the output voltage ripple. In order to generate a current (I adp ) that is proportional to the difference between the supply and output voltage, we designed a circuit that consists of MN1, R 1, C C, and an amplifier. The current is copied using a current mirror that consists of MN2, MP1, and MP2. This current can be expressed as follows: I adp ¼ V DD V O ð1þ R 1 which is converted to a saw-tooth waveform through C1: DV ramp ðtþ ¼ 1 Z I adp dt ð2þ C 1 Therefore, when the pdrive in Fig. 3 becomes low, the PMOS power transistor in Fig. 1 remains on until the Vramp is equal to V ref2. This on-time is defined as T ON, and is proportional to changes in both the supply and the output voltage. This can be expressed using (1) and (2) as follows: DT ON ¼ V ref2r 1 C 1 V DD V O ð3þ As shown in (3), T ON changes in response to the supply voltage (V DD ) and output voltage (V O ). Using T ON, we can adjust the peak inductor current: Fig. 1 Block diagram of the proposed PFM controller DI L ¼ V DD V O T ON ð4þ 2L When the supply voltage is high, the inductor current s slope increases and T ON decreases; the inductor s peak current is constant. Similar operations occur for different supply or output voltages, or both, by adaptively increasing

3 Analog Integr Circ Sig Process (2012) 71: Fig. 4 Voltage generator for output voltage of buck converter Table 2 Performance summary Technology Input voltage Output voltage Inductor/DCR Capacitor/ESR Quiescent current Load current Efficiency 0.35 lm V V 2 lh/200 mx 20 lf/50 mx la ma 50 V O = 1.8 V Fig. 2 Waveforms of control signals in the proposed PFM using only one external resistor in order to minimize the number of external passive components. The V ref1 is: R 1 V ref1 ¼ V ref þ 1 ð5þ R 2 þ R off 3 Simulation results Fig. 3 Proposed adaptive on-time circuit or decreasing T ON to maintain a constant peak current without requiring a current-sensing circuit. Figure 4 shows the voltage generator that regulates the output voltage level. In conventional buck or boost dc dc converters, the output voltage is regulated by two external resistors that compare the output voltage with the reference voltage. In this study, we adjusted the reference voltage The operation of the proposed circuit was verified by HSPICE simulations. Table 2 summarizes the design parameters and simulation results. The waveforms in Fig. 5 show the magnitude of the ripple voltage of the buck converter output and the inductor current peaks when the supply voltage is 3.6 and 2.5 V, respectively. The waveforms in Fig. 6 show the magnitude of the ripple voltage and the inductor current peaks were well-controlled, even when the output voltage levels were as different as 1.8 and 0.8 V, respectively. Figures 7, 8, 9, and 10 show the results of a comparison between the proposed PFM circuit and the constant on-time PFM circuit. Figures 7 and 8 show the ripple variation of the output voltage and peak inductor current, according to the supply voltage levels, when the output voltage is set to 1 V. Figures 9 and 10 show the

4 330 Analog Integr Circ Sig Process (2012) 71: Fig. 7 Output ripple variation according to changing supply voltage levels (V O =1V,L =2lH, C =20lF, load current = 100 ma) Fig. 5 HSPICE simulation: V O = 1V,L = 2 lh, C = 20 lf, load current = 100mA Fig. 8 Inductor current peak-to-peak according to changing supply voltage levels (V O =1V,L =2lH, C =20lF, load current = 100 ma) Fig. 6 HSPICE simulation: V DD = 2.5 V, L =2lH, C =20lF, load current = 100 ma ripple variation of the output voltage and peak inductor current, according to the output voltage levels, when the supply voltage is set to 3.6 V. As expected, the proposed circuit shows a significant improvement. Figure 11 shows the efficiency of the proposed buck converter. Fig. 9 Output ripple variation according to changing output voltage levels (V DD = 3.6 V, L =2lH, C =20lF, load current = 100 ma)

5 Analog Integr Circ Sig Process (2012) 71: References Fig. 10 Inductor current peak-to-peak according to changing output voltage levels (V DD = 3.6 V, L =2lH, C =20lF, load current = 100 ma) Fig. 11 Power conversion efficiency (L = 2 lh, C = 20 lf) 4 Conclusion We have proposed a new adaptive on-time PFM circuit and verified it using HSPICE simulations. The proposed circuit has a constant peak inductor current and has little ripple voltage variation in the output voltage, even when there are significant changes in the supply and output voltage levels. The proposed circuit was designed with standard 0.18-lm CMOS process parameters, and its performance was demonstrated by comparative simulations with a conventional circuit. Acknowledgments This research was supported in part by the Ministry of Knowledge Economy, Korea, under the University ITRC support program supervised by the National IT Industry Promotion Agency (NIPA-2011-C ), and supported in part by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education, Science and Technology ( ). 1. Nam, H., Kim, I., Ahn, Y., & Roh, J. (2010). DC-DC switching converter with positive and negative outputs for active-matrix LCD bias. IET Circuit, Devices & Systems, 4(2), Xu, W., Li, Y., Gong, X., Hong, Z., & Killat, D. (2010). A dualmode single-inductor dual-output switching converter with small ripple. IEEE Transactions on Power Electronics, 25(3), Barai, M., Sengupta, S., & Biswas, J. (2010). Digital controller for DVS-enabled DC DC converter. IEEE Transactions on Power Electronics, 25(3), Kwon, D., & Rincon-Mora, G. A. (2009). Single-inductormultiple-output switching DC DC converters. IEEE Transactions on Circuits and Systems II, 56(8), Lee, H., & Ryu, S.-R. (2010). An efficiency-enhanced DCM buck regulator with improved switching timing of power transistors. IEEE Transactions on Circuits and Systems II, 57(3), Hammes, M., Kranz, C., Seippel, D., Kissing, J., & Leyk, A. (2008). Evolution on SoC integration: GSM baseband-radio in 0.13 lm CMOS extended by fully integrated power management unit. IEEE Journal of Solid-State Circuits, 43(1), Lorentz, V. R. H., Berberich, S. E., Marz, M., Bauer,A. J., Ryssel, H., Poure, P., et al. (2009). Light-load efficiency increase in highfrequency integrated DC DC converters by parallel dynamic width controlling. Analog Integrated Circuits and Signal Processing, 62(1), Liou, W.-R., Yeh, M.-L., & Kuo, Y.L. (2008). A high efficiency dual-mode buck converter IC for portable applications. IEEE Transactions on Power Electronics, 23(2), Xiao, J., Peterchev, A. V., Zhang, J., & Sanders, S. R. (2004). A 4-lA quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications. IEEE Journal of Solid-State Circuits, 39(12), Craig, V. (2006). Controlling output ripple and achieving ESR independence in constant on-time (COT) regulator designs. application note Wong, L. K., & Man, T. K. (2008). Maximum frequency for hysteretic control COT buck converters. IEEE 2008 Power Electronics and Motion Control Conference, pp Liu, K. P. (2008). Control circuit and method for a constant ontime PWM switching converter. US Patent US 2008/ A Chuan, N., & Tateishi, T. (2007). Adaptive constant on-time (D-CAPTM) control study in notebook applications. TI application note SLVA281B. 14. Wong, L. K., & Man, T. K. (2010). Adaptive on-time converters. IEEE Industrial Electronics Magazine, 4(3), Sahu, B. (2008). Analysis and design of a fully-integrated current sharing scheme for multi-phase adaptive on-time modulated switching regulators. IEEE 2008 Power Electronics Specialists Conference, (pp ). Island of Rhodes 16. Sahu, B., & Rincon-Mora, G. A. (2007). An accurate, low-voltage, CMOS switching power supply with adaptive on-time pulsefrequency modulation (PFM) control. IEEE Transactions on Circuits and Systems I, 54(2), Ma, F.-F., Chen, W.-Z., & Wu, J.-C. (2007). A monolithic current-mode buck converter with advanced control and protection circuits. IEEE Transactions on Power Electronics, 22(5),

6 332 Analog Integr Circ Sig Process (2012) 71: Hyunseok Nam received the B.S. degree in electronic and electrical engineering science, Hallym University, Chuncheon, Korea, in He received the M.S degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in 2007, where is currently pursuing the Ph.D. degree. His research interests include power management circuits and mixed-signal integrated circuits. Youngkook Ahn received the B.S. degree in electronic and electrical engineering science, Kyeonsang University, Jinjoo, Korea, in He received the M.S degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in He is now working toward the Ph.D. degree in the same department. His research interests include power management circuits and mixed-signal integrated circuits. Jeongjin Roh received the B.S degree in electrical engineering from the Hanyang University, Seoul, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin in From 1990 to 1996, he was with the Samsung Electronics, Kiheung, Korea, as a senior circuit designer for several mixed-signal products. From 2000 to 2001, he was with the Intel Corporation, Austin, Texas, as a senior analog designer for delta-sigma data converters. In 2001, he joined the faculty of the Hanyang University, Ansan, Korea. His research interests include oversampled delta-sigma converters and power management circuits.