A 400-mA current-mode buck converter with a self-trimming current sensing scheme

Transcription

1 Analog Integr Circ Sig Process (2011) 66: DOI /s A 400-mA current-mode buck converter with a self-trimming current sensing scheme Youngkook Ahn Donghun Heo Hyunseok Nam Jeongjin Roh Received: 20 November 2008 / Revised: 16 August 2010 / Accepted: 23 August 2010 / Published online: 7 September 2010 Ó Springer Science+Business Media, LLC 2010 Abstract A current-programmed mode (CPM) controller is designed for improved DC DC converter control. The key building block of the CPM controller is an accurate current-sensing circuit. This paper proposes a lossless current-sensing technique to measure the inductor current by measuring the current through the power transistor. A self-trimming circuit is used to compensate for any inaccuracies caused by voltage and temperature variations. The measurement results validate the operation of the fabricated chip. Keywords DC DC converter Power management IC Buck converter Current-sensing Analog circuit 1 Introduction Power converters are becoming an essential building block in modern battery-operated electronic systems, and prolonging the life of the battery is one of the most important design goals. Inductor-based DC DC converters are very attractive due to their high power efficiency and consequently have become popular in recent years. Figure 1 shows a block diagram of a current-mode buck converter. The buck converter consists of a monolithic controller and several external passive components. In a current-mode converter, the measurement of the inductor current is very important since it is directly related to the duty control of the pulse-width modulation (PWM) power signal. In the most straightforward way, the on-resistance Y. Ahn D. Heo H. Nam J. Roh (&) Department of Electrical Engineering, Hanyang University, Ansan , Korea jroh@hanyang.ac.kr of the power transistor can be used as a sense resistor; the current is measured by evaluating the voltage across the transistor. This simple method is commonly used in industry even though it is known to be inaccurate [1]. We try to improve the accuracy of this scheme in this paper. Several current-sensing techniques have been developed [2, 3, 4, 5, 6]. In most cases, the sense transistor is inserted in parallel with the power transistor [2, 3, 4, 5]. The difficulty with the methods reported in the literature lies in matching the power and sense transistors, and this matching is crucial for an accurate measurement of the current; this matching is not easy. Accurate matching becomes even more difficult when the transistors have a very large ratio, such as 1:1000 or larger, as in the case of the sense transistor and the power transistor. This paper proposes a current-sensing circuit that compensates for the inaccuracy produced by the on-resistance sensing method. Section 2 describes the mechanism of the current-sensing circuit proposed in this paper. In Sect. 3, the proposed circuits are discussed in detail. The performance of the current-mode buck converter produced by using the proposed current-sensing circuit is evaluated in Sect. 4 based on the experimental results. Finally, the conclusion of the paper is presented in Sect Proposed current-sensing technique The variation in the on-resistance of the power transistor is analyzed, and a self-trimming technique is proposed in this section. When a transistor is turned on, the on-resistance is represented simply as 1 R on ¼ lc ox W L ð V GS V TH Þ ; ð1þ

2 164 Analog Integr Circ Sig Process (2011) 66: Fig. 1 Block diagram of a current-mode buck converter where l is the mobility, C ox is the oxide capacitance per unit area, W/L is the transistor width to length ratio, V GS is the gate source voltage, and V TH is the threshold voltage. As can be seen from the equation, process, voltage, and temperature (PVT) variations make current measurement by using the on-resistance method inaccurate. The unavoidable PVT variations necessitate the development of an improved current-sensing technique for modern highperformance power-management circuits. Among the three kinds of variations, the problem of voltage and temperature variations are resolved in the proposed current-sensing scheme. Figure 2 shows the variation in transistor on-resistance due to two variation parameters, voltage and temperature. On-resistance increases with an increase in temperature at the input voltages tested ( V), and varies by 30% or more in response to changes in temperature and voltage. The results shown in Fig. 2 are based on a total inputvoltage range of 0.8 V (from 2.5 to 3.3 V), while commercial DC DC converters have a much larger range. Therefore, actual variation in on-resistance in commercial devices is much higher than that shown in Fig. 2. High onresistance variation decreases the accuracy of the currentsensing circuit, impairing stable control of the DC DC converter. This paper presents a self-trimming technique to compensate for the voltage and temperature variations in order to reduce significantly the inaccuracies caused by variations in transistor on-resistance. The current-sensing technique using on-resistance from a current-mode DC DC buck converter, shown in Fig. 1, involves detecting the voltage drop V sd created by the inductor current between the source and the drain of the power transistor Q 1. By using V sd and the on-resistance R on, the current I L flowing through Q 1 can be expressed as resistance (Ω) On resistance variation of Power MOSFET temperature ( C) Fig. 2 Variations in the transistor on-resistance VDD:2.5V VDD:2.7V VDD:3.0V VDD:3.3V I L ¼ V sd : ð2þ R on It is important to maintain a small on-resistance value for the power transistor because on-resistance causes a reduction in the efficiency of the regulator. In commercial converters, the on-resistance is about 0.5 to 1 X, so the V sd has a very small value. For example, if 10 ma flows through the inductor, V sd is 10 mv or less. Therefore, a current-sensing technique based on voltage drop V sd requires amplifiers to increase the voltage swing, which can be done by using a single amplifier in the power transistor [7]. Two amplifiers are used in the proposed design, and the resistors in the second amplifier are trimmed to compensate for any on-resistance variation. Even though two amplifiers are used in our design, the

3 Analog Integr Circ Sig Process (2011) 66: same idea can be implemented by using a single amplifier if the hardware needs to be minimized. Figure 3 shows the proposed current-sensing circuit. When there is a change in the on-resistance due to variations in temperature or input voltage, the V sd also changes according to I L and the on-resistance. The key idea of the proposed circuit is to maintain the current-sensing ratio I L : V sense at a fixed level by adjusting the gain V sd :V sense adapted to V sd. The sensing circuit is composed of two stages, as shown in Fig. 3. The first stage involves a difference amplifier that senses the voltage drop of the on-resistance and the current through it. The amplified V difference can be written as V difference ¼ V dc þ V sd R 1 : ð3þ R 0 The second stage has trimming resistors that adaptively control for variations in temperature and voltage. The temperature and voltage sensors generate digital trimming signals that control the CMOS switches. The trimming mechanism compensates for variation in on-resistance by adjusting the gain of the output stage of amp2 as the onresistance varies. For example, since the on-resistance increases when the temperature rises, the resistance is reduced at the amplification stage in order to maintain the sensing ratio. Furthermore, when the on-resistance is reduced by an increase in the input supply voltage, the sensing ratio is maintained by increasing the resistance. Table 1 summarizes the resistance selection according to variations in temperature and input voltage. Consequently, V sense can be expressed as V sense ¼ V dc þ V sd R 1 ðr tm þ R v ÞþR m þ R s : ð4þ R 0 R s Here, V sense has an offset voltage of V dc to ensure that the amplifier s output transistors operate within the saturation Fig. 3 Proposed currentsensing circuit

4 166 Analog Integr Circ Sig Process (2011) 66: Table 1 Resistance variation of tuning circuit by input voltage and temperature conditions Temperature ( C) Rtm Input voltage (V) Rv Accuracy of proposed current sensing circuit \0 Rtm0? Rtm Rtm Rv28 [ Rv28? Rv31 region. The proposed current-sensing circuit was designed to create V dc by using the transistor s V GS for simplicity, as shown in Fig. 3. It is difficult to generate an accurate voltage by using V GS due to variations in parameters such as V TH, temperature, and process. However, what is important in controlling the current-mode DC DC converter is the variation and slope of the voltage that senses the inductor current. The effect of V dc on the sensing voltage is eliminated by the error amplifier and by the compensator s feedback loop in Fig. 1. Figures 4 and 5 compare sensing accuracies of a conventional circuit and the circuit proposed in this paper. Figure 4 indicates that the conventional circuit has about ±20% error due to variations in temperature and input voltage, where 3.0 V at room temperature the graph crossed the 100% accuracy point. On the other hand, the proposed circuit reduced the error to about ±7%, as shown in Fig. 5. This is an improvement of about 13%, which corresponds to an input-voltage variation of only 0.6 V. The difference in accuracy will become more significant for a converter with a greater input-voltage variation. Table 2 shows a comparison of the system stability between the conventional circuit and the proposed circuit. The control-to-output transfer function (A vc ) of the CPM buck converter is as follows: accuracy (%) Accuracy of conventional current sensing circuit temperature ( C) Fig. 4 Accuracy of conventional current-sensing circuit VDD:2.7V VDD:3.0V VDD:3.3V accuracy (%) A vc ðsþ ¼A cm ; ð5þ 1 þ x s p 1 þ x s c where A cm ¼ 1 x c L R f 1 D=nð1 DÞ ==R L : ð6þ In Eqs. 5 and 6, x p, x c, and n are expressed as the values that account for the effect of current-programmed control, D is the duty ratio, L is the power stage inductance, and R L is the load resistance [8]. The current sensing function is represented by R f, which is shown in Fig. 1. Because of the gain factor N, the effective value of R f is R f ¼ N R on ; ð7þ where R on is the on-resistance of the power transistor and N is the sensing gain of the current-sensing circuit proposed in Fig. 3, where N = 4 in the designed circuit. The transfer function (A c ) of the type-ii compensator used to compensate frequencies in Fig. 1 is as follows: A c ðsþ ¼ temperature ( C) Fig. 5 Accuracy of the proposed current-sensing circuit VDD:2.7V VDD:3.0V VDD:3.3V G m R out ðsr1c1 þ 1Þ s 2 R1R out C1C2 þ sðr1c1 þ R out C1 þ R out C2Þþ1 ; ð8þ where G m and R out represent the transconductance and the output resistance of the error amplifier, respectively, and C1, C2 and R1 represent the capacitors and the resistor used for the frequency compensation in Fig. 1. Based on Eqs. 5 and 8, the total transfer function of the CPM buck converter can be represented as follows: TðsÞ ¼A vc ðsþa c ðsþ; ð9þ where the phase of the entire loop at the crossover frequency (f c ) becomes \Tðf c Þ, and thus the phase margin of the entire system is defined as follows [9]:

5 Analog Integr Circ Sig Process (2011) 66: Table 2 Comparison of system stability VDD/V out (V/V) L/C (lh/lf) Temperature ( C) R on ðxþ R f ðxþ Phase margin (degrees) Conv. Prop. Conv. Prop. 3.3/ / / / / / / / / / / / / / / PM ¼ 180 ðj\tðf c jþ: ð10þ The effect of the variation in R on on the stability of the converter can be evaluated by using Eq. 9. As shown in Fig. 2 and Eq. 7, R f changes around a base value due to the influence of variations in the on-resistance; the base value used for this paper is R f = 2. In the case of the conventional circuit, R f changes linearly in relation to R on because the sensing gain N of the current-sensing circuit is fixed, while in the case of the proposed circuit shown in Fig. 3, the changes in R f can be minimized by using the sensing gain control. From Table 2, we can see that the conventional circuit and the proposed circuit have different R f values due to variations in the on-resistance, and the effect of R f on the phase margin increases as the input voltage decreases and the temperature and duty ratio increase. In Table 2, if we compare the two circuits when V DD = 2.5 V, V out = 2.2 V, L = 2.2 lh, and C = 4.7 lf, the stability of the converter using the conventional circuit can be greatly affected because they have a phase margin of less than a 40. The phase margin of the proposed converter, however, is improved by 7.5 by the self-trimming function. Thus the proposed converter is more stable. This improvement in the phase margin is seen when the input voltage difference is only 0.8 V. The advantage of the proposed circuit in terms of the stability will increase as the voltage difference increases. In the proposed current-sensing technique, the extra hardware overhead is insignificant, since the two amplifiers and resistors are essential to amplifying the low value of V sd. In general, since CMOS controllers might be damaged at high junction temperature under heavy load conditions or at the dropout operation, they must include a temperaturesensing and protection circuit. In our circuit design, one temperature-sensing circuit is implemented and is used as both the temperature-protection circuit and the currentsensing circuit. Moreover, existing resistors are divided into small resistors for trimming, so no extra resistors are required. In the proposed sensing circuit, newly added circuits are composed of four comparators and four CMOS switches. Simple comparator architecture is selected to minimize the size, as shown in next section, and the switches are insignificant in terms of chip area. As a result, the area overhead of the proposed sensing circuit is minimized. 3 Circuit implementation As illustrated in Fig. 3, two amplifiers are used in the current-sensing circuit implemented in this paper. The circuit architecture of the amplifier is a two-stage amplifier with Miller compensation. Amp1 and amp2 have almost identical operating characteristics, but amp1 uses a NMOS input pair and amp2 uses a PMOS input pair to handle different input-voltage levels. Figure 6 displays the voltage-sensing circuit of the input power supply, and is part of the current-sensing circuit proposed in this paper. A reference voltage is needed in order to detect the input voltage by using a comparator. However, since the reference voltage inside the entire converter is created by the bandgap reference circuit, a reference voltage higher than the input voltage cannot be generated. In order to sense the input voltage, the input voltage has to be scaled down according to a specific ratio by using R0, R1, and R2, as indicated in Fig. 6. Then V vsense28 and V vsense31 become V vsense28 ¼ V DD R 0 þ R 1 R 0 þ R 1 þ R 2 R 0 ð11þ V vsense31 ¼ V DD : ð12þ R 0 þ R 1 þ R 2 Both are less than the input voltage. The input voltage can now be sensed by using V vsense28, V vsense31, and V vref.

6 168 Analog Integr Circ Sig Process (2011) 66: Fig. 6 Input power supply voltage-sensing circuit Figure 7 shows the temperature-sensing circuit of the current-sensing circuit. In general, temperature is sensed based on the fact that V BE of a BJT varies according to temperature. The proportional to absolute temperature (PTAT) current, which is denoted as I PTAT, and V tmsense can be written as I PTAT ¼ V T lnðn mþ ð13þ R1 V tmsense ¼ R0 R1 V T lnðn mþ; ð14þ where the thermal voltage V T equals kt/q, k is the Boltzmann s constant, T is the absolute temperature, and q is the magnitude of the electronic charge. As can be seen from Eq. 14, V tmsense is temperature dependent. The accuracy of temperature sensing can be increased by a large variation of V tmsense over the temperature variation. For a conventional circuit, the slope of V tmsense is ov tmsense ¼ R0 ot R1 k lnðn mþ: q ð15þ If R0, n or m are modified to increase the slope, V tmsense escapes out of the operating voltage range, which results in clipping. To resolve this problem, a current source was added to the V tmsense node. The current source allows V tmsense to become V tmsense ¼ R0 R1 V T lnðn mþ R0I REF : ð16þ The slope of V tmsense can be expressed as ov tmsense ot ¼ R0 R1 k q lnðn mþ R0 oi REF ot R0 R1 k lnðn mþ: q ð17þ Now the slope can be increased while maintaining a low voltage level and the variation range of V tmsense can be extended without clipping. The ideal current source I REF and the reference voltages are generated from the bandgap reference, which is assumed not to vary in response to supply voltage and temperature. Since the real circuit would still have a slight dependence on variation in these values, there might be insignificant changes in the accuracy curve in Fig. 5. A hysteresis comparator is used in the sensing circuits to prevent comparator errors that can be caused by noise [10]. Figure 8 shows the hysteresis comparator used in Fig. 6. The hysteresis comparator used in Fig. 7 has an identical architecture as the one in Fig. 8, but an NMOS was used as the input stage. 4 Experimental results The current-mode DC DC buck converter proposed in this study was fabricated by using the standard 0.18-lm CMOS process. Threshold voltage V TH of the NMOS and PMOS transistors were V THN & 0.75 V and V THP & V, respectively. Figure 9 is a photograph of the fabricated chip. The overall chip size is mm 2 ( mm 2 ). Fig. 7 Temperature-sensing circuit

7 Analog Integr Circ Sig Process (2011) 66: Fig. 8 Hysteresis comparator Fig. 9 Chip photograph of the current-mode DC DC buck converter Fig. 11 Measured load regulation waveform (ch1. output voltage, ch2. load current) Table 3 Performance of the fabricated DC-DC buck converter Fig. 10 Measured output voltage and SW signal (ch1. output voltage (ac), ch2. SW signal) Figure 10 represents the waveforms at the output V out and the SW node, which are shown in Fig. 1. An input supply voltage of 3.3 V was applied to the converter and the output voltage was set to 1.2 V. The switching frequency was set at 1.25 MHz. The values of the inductor and capacitor were 4.7 lh and 4.7 lf, respectively. Theoretical calculation yielded an output ripple voltage of Die size mm 2 Technology Standard 0.18 lm CMOS Switching frequency MHz Efficiency Max 91.8% Input voltage range V Output voltage range 0.5 V-Input voltage Load current range Maximum 400 ma Quiescent current 440 la Line regulation 8.63 mv/v (at load 50 ma) Load regulation 0.13 mv/ma (at V DD 3.3 V) Inductor 4.7 lh Capacitor 4.7 lf about 15 mv, and the measured waveform displayed a similar value. Figure 11 displays the output-voltage waveform according to variation in the load current. The step response of the output voltage was measured as the load current was varied from 400 to 100 and then back to 400 ma. As the waveform indicates, the output voltage

8 170 Analog Integr Circ Sig Process (2011) 66: reacted to step changes of the load current but quickly returns to the original value, maintaining a stable output voltage. Table 3 summarizes the performance of the current-mode DC DC buck converter. 5 Conclusion This paper proposed a circuit to overcome the drawbacks of the conventional current-sensing method by using onresistance, the sensing accuracy of which is improved by sensing the temperature and input voltage. By including a circuit that compensates for the error caused by variations in temperature and input voltage, a sensing accuracy of over 93%, a 13% improvement over a conventional circuit with an input-voltage variation range of V. The accuracy is expected to improve by an even greater degree with a wider input-voltage variation. Acknowledgment This work was supported by Mid-career Researcher Program through NRF grant funded bythe MEST (No ). Youngkook Ahn received the B.S. degree in electronic and electrical engineering science, Kyeonsang University, Jinjoo, Korea, in He received the M.S. degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in He is now working toward the Ph.D. degree in the same department. His research interests include power management circuits and mixed-signal integrated circuits. Donghun Heo received the B.S. and M.S. degree in electrical engineering and computer science from Hanyang University, Ansan, Korea, in 2006 and 2008, respectively. He subsequently joined Samsung Electronics Corporation, Giheung, Korea. Since then, he has been engaged in the research and development of system LSI products. References 1. Lenk, R. (1999). Application bulletin AB-20 optimum currentsensing techniques in CPU converters, Fairchild Semiconductor, Application Notes. 2. Smith, T. A., Dimitrijev, S., & Harrison, H. B. (2000). Controlling a DC-DC converter by using the power MOSFET as a voltage controlled resistor. IEEE Transactions on Circuits and Systems-I, 47, Lee, C. F., & Mok, P. K. T. (2004). A Monolithic current-mode CMOS DC DC converter with on-chip current-sensing technique. IEEE Journal of Solid-State Circuits, 39(1), Leung, C. Y., Mok, P. K. T., Leung, K. N., & Chan, M. (2005). An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator. IEEE Transactions on Circuits and Systems-II, 52, Chen, J.-J., Su, J.-H., Lin, H.-Y., Chang, C.-C., Lee, Y., Chen, T.-C., Wang, H.-C., Chang, K.-S., & Lin, P.-S. (2004). Integrated current sensing circuits suitable for step-down DC DC converters. IEE Electronics Letters, 40, Forghani-zadeh, H. P., & Rincon-Mora, G. A. (2007). An accurate, continuous, and lossless self-learning CMOS current-sensing scheme for inductor based DC DC converters. IEEE Journal of Solid-State Circuits, 42, Zhang, Y., Zane, R., Maksimovic, D., & Prodic, A. (2004). On-line calibration of lossless current sensing. In Rec. IEEE applied power electronics conference exposition (APEC), pp Middlebrook, R. D. (1989). Modeling current-programmed buck and boost regulators. IEEE Transactions on Power Electronics, 4(1), Erickson, R. W., & Maksimovic, D. (2001). Fundamentals of power electronics (2nd ed.). Norwell: KAP Publishers. 10. Allen, P. E., & Holberg, D. R. (1987). CMOS analog circuit design. New York: Holt Rinehart and Winston. Hyunseok Nam received the B.S. degree in electronic and electrical engineering science, Hallym University, Chuncheon, Korea, in He received the M.S degrees in electrical engineering and computer science, Hanyang University, Ansan, Korea, in 2007, where is currently pursuing the Ph.D. degree. His research interests include power management circuits and mixed-signal integrated circuits. Jeongjin Roh received the B.S degree in electrical engineering from the Hanyang University, Seoul, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin in From 1990 to 1996, he was with the Samsung Electronics, Kiheung, Korea, as a senior circuit designer for several mixed-signal products. From 2000 to 2001, he was with the Intel Corporation, Austin, Texas, as a senior analog designer for deltasigma data converters. In 2001, he joined the faculty of the Hanyang University, Ansan, Korea. His research interests include oversampled delta-sigma converters and power management circuits.