Integrated Upconverter Design For WCDMA Transmitter Implemented In 90nm CMOS. Anosh B. Davierwalla

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1 ABSTRACT DAVIERWALLA, ANOSH BOMI: Integrated Upconverter Design For WCDMA Transmitter Implemented In 90 nm CMOS. (Under the direction of Dr. Kevin Gard). Motivated by the overwhelming technology imperative to integrate radio frequency (RF) circuits along with digital baseband circuits on the same die, the fundamental objective of this research is to assess the potential of 90 nm CMOS technology for use in the RF transmit section of Wideband Code Division Multiple Access (WCDMA) cellular handsets while still meeting the exacting performance standards for the same. This thesis addresses the specific challenges associated with designing an upconverter for an integrated WCDMA transmitter implemented in 90 nm CMOS. The upconverter simultaneously performs quadrature modulation and direct upconversion of the baseband signal to the WCDMA transmit band located at ( ) MHz. A double balanced mixer topology is used to perform frequency translation, with differential to single-ended conversion of the upconverted signal being effected by a current mirror at RF. To mitigate the crunch for voltage headroom, the upconverter design implements the baseband transconductor as a folded differential pair. This MOS differential pair transconductor is linearized based on ideas borrowed from the multi-tanh concept. At a rated RF output voltage of 60 mv (rms), the upconverter achieves an Adjacent Channel Leakage power Ratio (ACLR at ±5 MHz offset) of dbc and an Alternate Channel Leakage power Ratio (ACLR at ±10 MHz offset) of dbc. The conversion gain of each I and Q mixer is 0 db, and the noise level in the WCDMA receive band at a +190 MHz offset is measured to be dbc. While delivering this performance, the entire quadrature upconverter consumes a mere 1.7 ma from its nominal 1.2 V supply, thus proving to be an efficient and low-power design.

2 Integrated Upconverter Design For WCDMA Transmitter Implemented In 90nm CMOS by Anosh B. Davierwalla A thesis submitted to the Graduate Faculty of North Carolina State University in partial satisfaction of the requirements for the Degree of Master of Science in Electrical Engineering Department of Electrical And Computer Engineering Raleigh 2005 Approved By: Dr. Maysam Ghovanloo Dr. W. Rhett Davis Dr. Kevin G. Gard Chair of Advisory Committee

3 ii Dedication I dedicate this thesis to those who make it all worthwhile... My beloved mum & dad Freny & Bomi, and My dear, dear sister Anaheet.

4 iii Biography Anosh Bomi Davierwalla was born on 4 th November 1979 in Bombay, India, and calls the hill-station town of Panchgani home, where he spent the best years of his life. He received his high school education in Panchgani itself at Billimoria High School and then at New Era Junior College. In May 2001, Anosh graduated from Pune Institute of Computer Technology (University of Pune) with a Bachelor s degree in the field of Electronics & Telecommunications Engineering. Following this, from August 2001 to July 2003, he worked as an ASIC design engineer at Paxonet Communications in Pune. Since the Fall of 2003, Anosh has been a graduate student in the Electrical and Computer Engineering department at North Carolina State University, Raleigh. It was here, at N.C. State, that he developed a strong interest in Analog and RF circuit design. He joined the research group of Dr. Kevin Gard in August 2004, and has since been involved in the Advanced WCDMA Transmitter design project implemented using the latest 90 nm CMOS technology.

5 iv Acknowledgements I would like to extend a sincere thank you to my academic advisor, Dr. Kevin Gard, not just for giving me a strong footing in RF circuit design, but also for sharing with me his invaluable experiences & insights that enabled me to grasp the bigger picture. Thank you, Dr. Gard! It s been a pleasure and a privilege working for you.

6 v Contents List of Tables List of Figures viii ix 1 Introduction Motivation Project Overview WCDMA Transmit Chain: From Baseband To RF TXIC Overview Overview of 90 nm CMOS (CMOS090) Technology Scope of this Thesis Thesis Organization Design Specifications WCDMA User Equipment Specifications Upconverter Specifications Input/Output Interfaces RF Output Signal Level Conversion Gain Linearity Noise Out-of-Band Noise In-Band Noise Upconverter Architecture Mixer Core Topology Active Vs. Passive Mixers Single Balanced Vs. Double Balanced Mixers Quadrature Modulation Differential to Single-Ended Conversion Balun Mixer Output Taken From One Leg

7 vi Current Mirror Transconductor Topology Differential Pair Common Source Transconductor Folded Differential Pair Transconductor Upconverter Architecture Summary Achieving Linearity Performance Intermodulation in the Upconverter Sources of Non-Linearity Transconductor Mixer Switch Current Mirror Tank Load Transconductor Linearization Linearizing the Common Source Transconductor Source Degeneration Derivative Superposition Linearizing the Folded Differential Pair Transconductor Borrowing the Multi-tanh Idea Summary Design Tradeoffs Expressions For RF Output and Conversion Gain Tank Inductor Transconductor Mixer Core Current Source (Located at the Folding Node) Current Mirror Results Simulation Setups Simulation Setup For IM 3 Measurement Simulation Setup For Conversion Gain Measurement Simulation Setup For Noise Measurement Compliance Table Linearity Performance With Process and Supply Variations Simulation Plots and Results Comparing Performance With Published Upconverter Circuits Conclusion 86 A Schematics 88

8 vii B Layout 96 Bibliography 102

9 viii List of Tables 2.1 WCDMA User Equipment Transmit Specifications Upconverter Interface Specifications Upconverter Performance Specifications Compliance Table for the CMOS090 WCDMA Upconverter Design Upconverter Linearity Performance With Process Variations Upconverter Linearity Performance With Supply Variations CMOS Upconverter Circuit Comparisons

10 ix List of Figures 1.1 3G WCDMA Transmit Architecture: Going From Baseband To RF WCDMA Transmit Chain Relating ACLR to Intermodulation Performance Impact of upconverter ACLR on the cascaded ACLR performance of upconverter & driver amplifier Single Balanced Mixer Double Balanced Mixer Quadrature Modulator and its Implementation Current Mirror for Differential to Single-Ended Conversion Double Balanced Mixer with Common Source Transconductor Double Balanced Mixer with Folded Differential Pair Transconductor Basic Upconverter Architecture showing I and Q Mixers Intermodulation in the context of the Upconverter Voltage and Current Spectra of a Transconductor Upconversion of the 3 rd harmonic component Inductor R P Source Degeneration Plot of g 1, g 2, g 3 for an NMOS transistor Composite transconductor structure for suppression of 3 rd harmonic using Derivative Superposition technique Plot showing derivative superposition for g Composite transconductor structure for suppression of 2 nd harmonic using Derivative Superposition technique Transconductance Function of a Differential Pair G m components of a MOS Triplet MOS Doublet MOS Triplet G m of a MOS Triplet plotted for different values of m G m of a MOS Triplet (m=10) plotted for different values of W

11 x 4.16 Harmonic Signature of a MOS Triplet (m=10) Complete Upconverter Architecture Single-Point PSS Plot for Upconverter RF Output Voltage Swept PSS Plot for Upconverter RF Output Voltage Swept PSS Plot Showing Baseband and RF Current Linearity in the Upconverter Swept PSS Plot Showing Linearity Performance of the Upconverter and the Driver Amplifier Output Noise Spectral Density For the Upconverter A.1 Cell: Upconverter - Quadrature Upconverter - Zoom Section A.2 Cell: Upconverter - Quadrature Upconverter - Zoom Section A.3 Cell: Transconductor - MOS Triplet Transconductor A.4 Cell: Tail CS - Transconductor Tail Current Sources A.5 Cell: DB Mixer Core - Double Balanced Mixer Core A.6 Cell: Mixer CS - PMOS Current Sources (Located at Folding Node) 94 A.7 Cell: TXIC Testbench - TXIC Testbench with Quadrature LO Divider, Upconverter and Driver Amplifier B.1 Cell: Upconverter - Quadrature Upconverter B.2 Cell: Transconductor - MOS Triplet Transconductor B.3 Cell: Tail CS - Transconductor Tail Current Sources B.4 Cell: DB Mixer Core - Double Balanced Mixer Core B.5 Cell: Mixer CS - PMOS Current Sources (Located at Folding Node) 101

12 1 Chapter 1 Introduction This thesis details the design of a quadrature upconverter for Wideband Code Division Multiple Access (WCDMA) cellular handset applications implemented in the latest 90 nm CMOS process technology. For the WCDMA upconverter, most demanding of all is the linearity specification at its rated output level. Not surprisingly then, the thrust of the work described by way of this thesis revolves around the investigation of linearity issues in the context of the upconverter with the intent of synthesizing a highly linear, low power upconverter design for WCDMA applications. 1.1 Motivation The last decade has been witness to a phenomenal growth in the cellular telecommunications industry, a growth that is unparalleled in the history of technology adoption, even when compared with the internet revolution. With well over a billion cellular subscribers worldwide [21], and counting, the cellular phone industry represents the single largest market segment for semiconductor manufacturers. The ubiquity of cell phones today attests to the consumer-driven and intensely competitive nature of the industry, where the push for higher performance is only superseded by the demand for lower & lower costs. This consumer demand provides the impetus for low cost, low power and small form-factor cellular handsets. All the contemporary cellular communication technologies are based on sophis-

13 2 ticated digital modulation schemes and rely heavily on digital signal processing at baseband in order to deliver the required performance. By virtue of its unrivalled cost advantage, CMOS is the number-one technology choice used to fabricate high performance digital circuits that implement the digital signal processing at baseband. Furthermore, CMOS digital circuits can successfully harness the benefits of increased circuit speed and higher density (resulting from a smaller foot-print) that are associated with scaling CMOS technology into the deep submicron regime. Complete system integration is increasingly becoming a technology imperative that renders further reductions in cost, power, component count, and form factor. This implies implementing the complete transceiver system on a single chip, having digital baseband circuits integrated with RF circuits on the same die. The two viable and competing process technologies for realizing this integration goal are SiGe BiCMOS and bulk CMOS. SiGe BiCMOS technology integrates high performance heterojunction bipolar transistors (HBTs) along with CMOS devices on the same wafer. On account of their superior high frequency performance, HBTs are better suited for RF circuit design as compared to standard CMOS devices. However, SiGe technology is typically one or two process nodes behind the state-of-the-art digital CMOS technology. Given that handsets are increasingly requiring more digital processing resources, SiGe doesn t keep the more significant digital portion (especially memory) of the die cost at a minimum [14]. SiGe BiCMOS also has a higher cost per unit area, which deals a further blow to the cost effectiveness of this process technology. On the other hand, with the scaling in bulk CMOS technology continuing at a faster pace than in the competing BiCMOS technology, the performance gap between devices in bulk CMOS and those in BiCMOS is steadily shrinking. Specifically, the cutoff frequency, f t, of NMOS devices in the deep submicron bulk CMOS technology is getting closer to the f t of NPN devices in the BiCMOS technology [24, 6]. As a result of the above factors, bulk CMOS technology is being seen as the prime choice for cost-driven integration of digital, analog and RF circuits on the same die. With over 692 million cell phones shipped in 2004 alone [22], and the annual sales of cell phones projected to reach a billion before the decade is out [5], the boom in

14 3 cellular handset sales presents the semiconductor manufacturers with a market opportunity of epic proportions. The Third Generation (3G) is the next phase in the evolution of cellular communications that began some 20 years ago. 3G technology represents an evolution in terms of capacity, data speeds and new service capabilities from the earlier second generation (2G) cellular networks. The deployment of 3G networks has already started in some countries and will be implemented on a worldwide basis over the next decade. The Third Generation Partnership Project (3GPP) is the standards body responsible for the technical specifications of 3G. Wideband Code Division Multiple Access, hereinafter referred to as WCDMA, has been standardized by 3GPP as the air interface or radio access technology for 3G systems. Given the fact that 3G is on the threshold of global deployment, a WCDMA transmitter is a classic example of a cost sensitive product that will transition to high volume production within the next five years. While high levels of integration have been achieved on the receiver in silicon, the same cannot be said for the transmitter. It is generally accepted that the power amplifier in the transmitter chain is not a candidate for high level integration due to technology limitations that would reduce its power added efficiency, and the inability to remove the thermal dissipation effectively [9]. Over and above this, the extremely challenging performance specifications of the radio transmitter have necessitated the use of process technologies like BiCMOS to simultaneously meet specifications and achieve some level of integration. Even after discounting the power amplifier, the present level of integration in the transmitter is far from optimal and it is based on the relatively expensive SiGe BiCMOS process technology, thus contributing directly to higher manufacturing costs. However, as scaling into the deep submicron dimensions accelerates, the potential of bulk CMOS as a replacement technology for BiCMOS gains momentum, with the economies of scale ultimately gravitating the design of radio transceivers towards advanced CMOS technologies. Besides, there are additional cost savings to be gained from successfully transitioning product lines to technologies with fewer processing steps and greater die output per wafer. It is with this motivation that a research project has been undertaken to design,

15 4 Figure 1.1: 3G WCDMA Transmit Architecture: Going From Baseband To RF fabricate and test a WCDMA transmitter RFIC, implemented in deep submicron CMOS, that achieves comparable performance and power consumption as existing SiGe based transmitter designs. 1.2 Project Overview This thesis is part of a larger research project that involves the design, fabrication and test of a 90 nm CMOS transmitter RFIC intended for 3G WCDMA handset applications. The primary intent of this research is to investigate the viability of 90 nm CMOS in the RF transmit section, and address the specifics of designing a WCDMA transmitter RFIC for operation at frequencies of around 1.95 GHz while still meeting the stringent cellular performance specifications. As shown in Figure 1.1, the WCDMA transmitter RFIC, referred to hereafter as TXIC, is located between the baseband section and the RF power amplifier. The TXIC is based on a homodyne or direct upconversion architecture wherein the quadrature baseband signal is directly upconverted to RF and is followed by linear amplification at RF. Before elaborating on the specifics of the TXIC, a brief overview of the 3G

16 5 WCDMA transmitter architecture and the corresponding signal path is presented in order to put things into perspective WCDMA Transmit Chain: From Baseband To RF A high level block diagram of the WCDMA transmit chain illustrating the signal path from baseband all the way up to the RF output at the antenna is shown in Figure 1.1. As specified by the 3GPP Technical Specification [1], the radio interface for the 3G mobile system employs Direct-Sequence Code Division Multiple Access (DS- CDMA) as the multiple access technique. Using orthogonal spreading codes with a modulating chip rate of 3.84 Mcps, the information data is spread over a bandwidth of 1.92 MHz at baseband. Hence the name Wideband CDMA (WCDMA). The WCDMA transmitter is intended to be operated in the Frequency Division Duplex (FDD) mode. FDD is a duplex method whereby the uplink (mobile to base station) and downlink (base station to mobile) transmissions are separated in the frequency domain. For Band I operation, the uplink frequency band is located at ( ) MHz while the downlink frequency band is located at ( ) MHz, thus resulting in a TX- RX frequency separation of 190 MHz. At RF, each channel occupies a bandwidth of approximately 5 MHz, and since there are no guard channels, the channel spacing is also set to 5 MHz. Referring to the WCDMA transmit chain shown in Figure 1.1, the baseband processor separates the transmit digital data into I and Q channels, and then performs a spreading operation. One of the primary purposes of spreading is to separate the users in the power domain by spreading the energy contained in the narrowband information signal over a much wider bandwidth, thus allowing multiple users to simultaneously share the same radio frequency channel. Orthogonality between the spreading codes is required to ensure no crosstalk occurs between different users. Hybrid Phase Shift Keying (HPSK) is specified as the spreading technique for the uplink of 3G systems like WCDMA. Since the multiplexed I and Q channels can have differing power levels, HPSK uses complex scrambling and selected orthogonal spread-

17 6 ing codes to distribute the power evenly between the I and Q axes, thus reducing the peak-to-average power ratio (PAR) of the transmit signal [18]. Consequently, in WCDMA, spreading consists of two operations channelisation and scrambling. With the channelisation operation, data symbols on the so-called I and Q branches are independently multiplied by orthogonal spreading codes, thus increasing the bandwidth of the signal. With the scrambling operation, the resultant data on the I and Q branches is further multiplied by a complex-valued spreading code [2]. The modulating chip rate (after channelisation and scrambling operations) is 3.84 Mcps. Therefore, the transmit data generated by the baseband processor is an HPSK modulated digital signal with a bandwidth of 1.92 MHz. This is the case for the I channel as well as the Q channel. In order to improve the spectral efficiency and limit the RF signal bandwidth resulting from quadrature modulation, the baseband processor performs pulse shaping on the I and Q binary data streams generated after the spreading operation. Each transmit pulse shaping filter (one for the I channel and another for the Q channel) is specified to be a root-raised cosine (RRC) filter [23] function with a frequency roll-off α = 0.22, and is implemented by the baseband processor in the digital domain. Subsequently, the bandwidth of each baseband I and Q channel is 1.92 (1+α) = 2.34 MHz. As a result of this transmit filtering, the baseband signal is no longer a binary data stream of 1s and 0s, but has an amplitude component present. Consequently, the RF signal generated after quadrature modulation, instead of being a constant-envelope signal, is now a variable envelope signal. The I and Q streams of digital word samples corresponding to the RRC filtered baseband data are then applied to Digital-to-Analog Converters (DACs). As shown, there is a separate DAC for the I channel and another for the Q channel. Each DAC samples the digital words and converts it to a corresponding analog signal. Baseband low-pass filters are placed after the DACs on each of the two channels. Each baseband filter functions as an analog anti-aliasing filter. The analog output of the DAC is comprised of the baseband spectrum, having a 2.34 MHz bandwidth, along with replicas of this baseband spectrum at every integer multiple of the DAC sampling frequency. The baseband low-pass filter removes all the replicas/images

18 7 thus preventing aliasing. Since the transmitter is based on a direct upconversion architecture, the frequency translation from baseband to RF takes place in one single step. Consequently, the LO frequency is made equal to the output RF carrier frequency, with quadrature modulation and upconversion occurring in the same upconverter circuit. Quadrature modulation necessitates the use of two LO signals that have a quadrature phase relationship, i.e., the two signals are at the same frequency but have a phase difference of 90. In the upconverter, the filtered I & Q baseband signals are applied to separate I & Q mixers which are driven by the quadrature LO signals. The upconverted signals at the outputs of the I & Q mixers are then summed in quadrature to give the desired RF output. In order to derive accurate quadrature LO signals, a divide-by-two circuit is used. The quadrature LO divider circuit operates at a clock frequency equal to twice the desired LO frequency. This clock is supplied by a voltage controlled oscillator (VCO) that has been locked to the desired frequency using a phase locked loop. Through a mechanism called injection pulling or injection locking, the transmit LO spectrum can be corrupted by the power amplifier (PA) output [19]. In direct conversion, this issue arises because the PA output is a modulated waveform with a high power spectrum centered about the LO frequency. The phenomenon of LO pulling can be alleviated if the VCO frequency that is used to generate the LO signal is sufficiently far away from the PA output spectrum. This is another reason why the VCO that generates the LO signal operates at twice the required LO frequency. On account of the filtering performed at baseband, the upconverted RF output signal is not characterized by a constant envelope, but contains information in both the amplitude and phase components. Consequently, to avoid spectral regrowth and to ensure error-free detection at the receiver, linear amplification in the RF signal path becomes imperative. The driver amplifier, stepped gain amplifier and power amplifier blocks provide such amplification to the upconverted RF signal. Adequate gain is built into these amplifier blocks so that, in the extreme case, the rated RF output power can be delivered to the antenna. WCDMA transmitters require a wide dynamic range of gain control in order to

19 8 combat the near-far problem and maximize cell capacity. Thus, when a mobile user is close to the base station its transmit signal power is backed off so that it does not overwhelm the weaker signal transmissions from other far away users. In order to meet the closed loop power control requirements, the required gain control functions are typically distributed between the baseband, stepped gain amplifier and driver amplifier blocks. Before being applied to the power amplifier, the output of the driver amplifier is passed through a filter. This is an off-chip surface acoustic wave (SAW) filter that is used to attenuate the noise generated by the TX in the RX band. This noise becomes critical when the handset is operating at the edge of a cell where the receiver sensitivity and transmitter output power are at maximum levels. The amplified RF signal available at the power amplifier output is fed to the antenna through an isolator and a duplexer. The main function of the RF isolator is to prevent any reflected power from returning to the power amplifier output. With WCDMA being a full duplex communication system wherein both transmitter and receiver operate simultaneously, the duplexer allows the transmitter and the receiver to share a common antenna. In doing so, the duplexer also provides a finite degree of isolation between the transmitter and the receiver TXIC Overview As shown in the WCDMA transmit chain of Figure 1.1 on page 4, the TXIC is located between the baseband section and the RF power amplifier. The two primary functions performed by the TXIC are quadrature upconversion of baseband to RF, and linear amplification at RF. The key functional blocks of the TXIC are outlined below: Upconverter The upconverter performs the combined functions of quadrature modulation and direct upconversion. The analog baseband I & Q inputs of the upconverter present a differential interface to the baseband filter. The upconverter also makes use of quadrature LO signals taken differentially from the on-chip quadrature LO divider circuit.

20 9 Stepped Gain Amplifier This block implements linear amplification at RF while providing the necessary gain control function required to perform the closed loop power control in WCDMA. Driver Amplifier The driver amplifier provides linear amplification at RF with sufficient gain to be able to deliver the rated 10 dbm output power to a 50 Ω load. Since both the SAW filter and the power amplifier are not amenable to integration, the RF signal at the driver amplifier output needs to be taken off-chip. Hence the requirement for driving a 50 Ω load. Quadrature LO Divider This is essentially a divide-by-two circuit that enables accurate generation of quadrature LO signals from a clock running at twice the LO frequency. In case of the TXIC, the LO signal is provided externally by a signal generator operating at twice the RF carrier frequency. Accounting for the power amplifier gain and fixed losses in the transmitter chain, the maximum output power specification for the TXIC is calculated to be 10 dbm, with the details illustrated in Figure 2.1 on page 17. The specified gain control dynamic range for the entire transmit chain is around 90 db to meet the WCDMA closed loop power control requirements. The transmitter gain controls are distributed between the baseband and RF sections, with the actual budgeting done so as to minimize power consumption and maximize performance over the entire dynamic operating range. Of the various specifications for the CMOS TXIC, discussed in-depth in Chapter 2, without a doubt, the most challenging of all is the linearity specification at the high output power levels. The total DC power consumption is another critical specification, especially for the power-hungry driver amplifier, as this figure determines the overall power efficiency for the CMOS TXIC. Since this is the first of three passes for the 90 nm CMOS TXIC project, the upconverter and driver amplifier blocks are designed with the sole purpose of meeting specifications at the high end of dynamic range where output power, linearity and RXband noise dominate the performance specifications. This design does not incorporate

21 10 any form of gain control, and this task is earmarked for the second pass of the TXIC project Overview of 90 nm CMOS (CMOS090) Technology With the ultimate goal of achieving higher levels of integration, the WCDMA TXIC is designed using the latest 90 nm CMOS technology, CMOS090. Apart from the novelty of designing in 90 nm CMOS, part of the research aspect of this project lies in evaluating the feasibility of 90 nm CMOS for use in stringent and high performance RF applications such as WCDMA mobile transmitters. The following summary highlights some key features of the 90 nm CMOS technology, CMOS090, and its accompanying RF library. Alliance between Motorola SPS, ST-Microelectronics and Philips Semiconductors. Process development in ST-Microelectronics Crolles-2 Fab facility in France. Two standard bulk process options LP (Low Power) or GP(General Purpose). Only LP option available for RF library. Metallization option 6M1T (Total 6 metal layers, of which 1 is thick top metal). Dual gate oxide transistors Thin oxide (1.2V/22Å) or Thick oxide (2.5V/50Å). Gate Poly Contact Option available to contact the gate poly on one or both sides. Triple well process Isolated Pwell from substrate. isolated NMOS device. Can therefore build an Inductors Single-turn or multi-turn, 2-port or 3-port. Q = 5 to 10. Capacitors MIM (high density), fringe (medium density), poly gate (non-linear MOS) capacitors.

22 11 Resistors Silicided and unsilicided poly and active resistors. Layout pcells (parameterized cells) available for all devices. The 90 nm CMOS technology presents RF designers with opportunities as well as challenges. The improvement in the f t and f max of 90 nm CMOS devices, resulting primarily from scaling gate lengths, allows RF circuits operating in the 2 GHz frequency range to be designed with considerable ease. With performance relying strongly on minimization of parasitic elements, layout optimization calls for devices to be laid out in multiple fingers and the gate be contacted at both ends. mitigates the effects of parasitic gate capacitance and gate resistance. This The scaling of gate lengths is also accompanied by the scaling down of oxide thickness. This results in a higher transconductance coefficient, µc ox, and also higher parasitic ( ) capacitance, C ox. Furthermore, higher values of transconductance efficiency, gm, coupled with the lower supply voltages for deep submicron CMOS indicate I D the potential for reducing power consumption. A fallout of designing circuits using 90 nm CMOS devices is the restricted power supply voltage of 1.2 V. While on the one hand, this reduced supply voltage presents an opportunity of achieving a low power design, on the other it creates a crunch for voltage headroom, thereby limiting the total number of devices in a stack Scope of this Thesis The work detailed in this thesis is confined to the design of the upconverter section of the 90 nm CMOS TXIC for WCDMA applications. The focus of the upconverter design is on achieving the targeted linearity specifications at the high end of dynamic range while keeping the power consumption to a minimum. This thesis examines, in considerable detail, various linearization techniques and architectures that will enable the upconverter design to efficiently meet the WCDMA linearity requirements. The thesis also addresses some of the challenges associated with designing circuits in 90 nm CMOS, in particular, the reduced supply voltage. The anticipated result of this research is to demonstrate the viability of the 90 nm CMOS technology for

23 12 use in stringent and demanding RF/cellular applications without compromising on performance. While the upconverter design is complete in itself, it does rely on the driver amplifier and quadrature LO divider blocks to derive its specifications. The deliverables for the upconverter design include complete and verified schematics along with the corresponding layouts that are DRC and LVS clean. 1.3 Thesis Organization The thesis has the following organization: Chapter 2 arrives at the design specifications for the upconverter using the 3GPP WCDMA system specifications as a starting point. Chapter 3 evaluates the different topology choices for the upconverter design in order to come up with the overall upconverter architecture. Chapter 4 investigates the issues relating to upconverter linearity and discusses two solutions for mitigating the non-linearity predicament. Chapter 5 provides a summary of the trends and guidelines relating to the upconverter design with insights to aid a designer achieve the desired performance. Chapter 6 presents and comments on the results of schematic-level simulations for the upconverter design. Chapter 7 concludes the thesis with an overview of the work done, and the potential of 90 nm CMOS in the RF transmitter circuits.

24 13 Chapter 2 Design Specifications The technical standards body for 3G cellular systems, 3GPP, defines the WCDMA air-interface or radio specifications at the phone level, i.e., for the mobile handset (also known as WCDMA User Equipment) as a whole. The upconverter, being one of the constituent blocks in the WCDMA transmit chain, does not have its specifications standardized by 3GPP. In fact, the specifications for each of the constituent blocks in the WCDMA transmit chain are derived from the phone-level specifications such that their cascaded performance allows the complete WCDMA handset to meet the 3GPP specifications. This chapter details the specifications for the WCDMA upconverter, and how these are derived from the 3GPP WCDMA User Equipment specifications. 2.1 WCDMA User Equipment Specifications The 3GPP Technical Specification [1] establishes the minimum RF requirements for WCDMA User Equipment (i.e. mobile terminals) operating in the Frequency Division Duplex (FDD) mode. Based on this specification, the key RF performance requirements for 3G WCDMA transmitter terminals are outlined in Table 2.1. These requirements describe the system specifications for a 3G mobile transmitter, as specified at the antenna connector of the User Equipment.

25 14 Table 2.1: WCDMA User Equipment Transmit Specifications Performance Parameter 3GPP Specification Uplink Frequency (TX) MHz Downlink Frequency (RX) MHz Channel Spacing 5 MHz Chip Rate 3.84 Mcps Maximum Output Power 27 dbm +1/-3 db (Power Class 2) Minimum Output Power -50 dbm ACLR1 ( ±5 MHz ) -33 dbc ACLR2 ( ±10 MHz ) -43 dbc EVM 17.5% TX-RX Frequency Separation 190 MHz 2.2 Upconverter Specifications The specifications for the upconverter and the driver amplifier blocks are determined such that the cascaded performance of the upconverter, driver amplifier, power amplifier, and duplexer meets the 3G User Equipment transmit specifications outlined in Table 2.1. Tables 2.2 and 2.3 highlight the interface and performance specifications for the WCDMA upconverter, with the rationale behind these specifications explained in the following subsections. Table 2.2: Upconverter Interface Specifications Interface Parameter Specification Description I & Q differential inputs Relation between I & Q channels Independent Baseband Input Waveform Continuous wave Bandwidth 1.92 MHz Peak-to-Peak Amplitude - Description I & Q differential inputs Relation between I & Q channels Quadrature LO Input Waveform Square wave Frequency (nominal carrier) 1950 MHz Peak-to-Peak Amplitude mv RF Output Description Single-ended output

26 15 Table 2.3: Upconverter Performance Specifications Performance Parameter Specification Maximum RF output voltage 60 mv (rms) ACLR1 ( ±5 MHz ) -53 dbc ACLR2 ( ±10 MHz ) -63 dbc Conversion Gain 1 In-Band Noise -40 dbc Out-of-Band Noise (at 190 MHz offset) Without SAW Filter -164 dbc With SAW Filter -131 dbc Input/Output Interfaces Baseband Interface In the baseband section of the WCDMA transmit chain, the binary information stream is spread using a complex-valued PN sequence running at chip rate of 3.84 Mcps. Hybrid PSK (HPSK) modulation is used while spreading in order to reduce the peak-to-average power ratio (PAR) of the transmit signal. The resulting data on the I channel and the Q channel is independent, with each channel occupying a bandwidth of 1.92 MHz (corresponding to a channel bit rate of 3.84 Mbps). Before being applied to the upconverter, the data on the I and Q channels is passed through a root-raised cosine (RRC) filter. The primary purpose of this transmit pulse-shaping filter is to limit the spectrum of the RF signal after quadrature modulation, and thereby improve bandwidth efficiency. As a result of the filtering, the baseband input to the upconverter is no longer binary data, but now a continuous wave signal. Both, the I and the Q baseband channels are available as differential inputs to the upconverter. Local Oscillator (LO) Interface The upconverter block performs quadrature modulation as well as direct upconversion to RF. Consequently, the upconverter requires two LO signals having the same frequency and a quadrature phase relationship. These two quadrature LO signals are provided differentially from an on-chip LO divider circuit that is driven by

27 16 an external signal generator running at twice the operating (carrier) frequency. Carrier leakage is a cause for some concern, especially at the low output power levels. To highlight the scale of the problem, consider the RF output power to be at the low end of dynamic range, say -76 dbm. Across a 50 Ω load, this corresponds to an rms voltage level of µv. If the LO signal has a 400 mv p p swing, the rms value of the LO signal is mv. Clearly, with the LO and RF signals being at least three orders of magnitude apart, a high degree of isolation between the LO and RF paths is called for. One of the main mechanisms responsible for leakage of the RF carrier to the ouptut is substrate coupling. While using resistive loads instead of inductive loads for the on-chip quadrature LO divider circuit does not completely eliminate carrier leakage, it does help mitigate the problem to a considerable extent. It is with this motivation that resistive loads are used for the quadrature LO divider circuit, resulting in a square-like LO waveform. RF Interface The driver amplifier that connects to the upconverter has a single-ended input, thus requiring the upconverter RF output interface to be single-ended. Typically, on account of the large C GS of its input device, the driver amplifier input presents a significant capacitive load at the upconverter output interface. If not resonated, the capacitance starts to behave like a short at the operating frequency, thus lowering the impedance at the output node of the upconverter and killing the circuit gain. To counteract this capacitive loading at the upconverter RF output, an inductor is used such that, at the operating frequency, it resonates out all the capacitance present at the output node. Consequently, the RF output interface of the upconverter is a tuned circuit that is centered about the WCDMA transmit band at 1950 MHz.

28 17 Figure 2.1: WCDMA Transmit Chain RF Output Signal Level With the worst case values of gain/loss for the various blocks in the transmit chain shown in Figure 2.1, the driver amplifier needs to deliver a total power of around 8 dbm to a 50 Ω load in order to allow the transmitter to meet the 3G Power Class 2 specification. Allocating an additional 2 db margin for contingencies like process variations, finite model accuracies and any post-driver amplifier gain variations, the driver amplifier is targeted to deliver a total output power of 10 dbm. The WCDMA transmitter design is based on a direct upconversion architecture. As a result, the upconverted RF output is double sideband since the baseband information is translated to frequencies located on either side about the RF carrier. Both, the upper and lower sidebands together constitute the baseband information and each of them are equal in power. To put it differently, a single tone at baseband gets upconverted to a 2-tone RF signal, with each of the two tones having the same power level. Thus, for the driver amplifier to deliver a total output power of 10 dbm, each of the two RF tones must be at half-power, i.e., 7 dbm. The RF output level specification for the upconverter is tightly coupled with the

29 18 driver amplifier design and its gain. The driver amplifier is a 3-stage design comprising of a cascode followed by 2 common source stages. The primary reason for using a cascode as the first stage is to provide adequate isolation between the upconverter block and the common source stages of the driver amplifier. This ensures that the upconverter and the driver amplifier can be successfully hooked-up together with minimal impact on the driver amplifier performance. The maximum RF signal at the upconverter output needs to be high enough to allow the driver amplifier to hit the rated 10 dbm output power. Furthermore, since no power matching is done at the interface between the upconverter and the driver amplifier, the upconverter output is more meaningful when expressed as an rms voltage level rather than a power level. For a 2-tone signal, it is the individual power levels (or the mean square voltages) and NOT the rms voltages of the two tones that add algebraically. Consequently, the effective rms voltage of a 2-tone signal can be derived as follows: P 2 T one = P 1 + P 2 V 2 rms(2 T one) = V 2 rms1 + V 2 rms2 = 2V 2 rms1 V rms(2 T one) = 2V rms1 = V peak1 (2.1) With the cascode stage being part of the driver amplifier, the driver amplifier requires an effective RF voltage of 60 mv (rms) at its input in order to deliver the rated 10 dbm output power to a 50 Ω load. This, in turn, dictates the RF signal specification at the upconverter output Conversion Gain The sole function of an upconverter is to translate a signal from baseband all the way up to RF. Since the input and output signals of the upconverter are centered about different frequencies, the gain imparted to a signal in going from the input to the output of the upconverter is referred to as conversion gain. Consequently, the conversion gain relates the upconverted RF output voltage to

30 19 the input baseband voltage. In the case of this design, it is defined as: Conversion Gain = V out(rf )(rms)(single ended) V in(bb)(rms)(differential) (2.2) The WCDMA upconverter is based on a direct upconversion architecture. thus performs upconversion and quadrature modulation in the same circuit. In order to implement quadrature modulation, it uses two mixers, one for the I channel and another for the Q channel. While the baseband input signals for the I and Q mixers are independent, the LO signals for the two mixers are in quadrature. The upconverted RF outputs of the individual I and Q mixers are then summed together in order to generate the final RF output. phases of the I and Q baseband inputs. The exact summing result depends on the relative Since the I and the Q mixers are identical, their conversion gains are identical. The definition of conversion gain given by Equation (2.2) applies only to each individual I or Q mixer, and not to the entire quadrature modulator. There is no hard specification on the conversion gain of the upconverter. However, the conversion gain of each I and Q mixer should be adequate enough for a small to moderate baseband signal to generate an upconverted RF output signal that will enable the Driver Amplifier output to hit its rated 10 dbm output power. It Linearity Support for high data rates entails the use of spectrally efficient modulation schemes like Quadrature Phase Shift Keying (QPSK), Offset QPSK (OQPSK), etc. For the WCDMA uplink, Quadrature Phase Shift Keying (QPSK) is used as the modulation scheme. In order to limit the bandwidth of the modulated signal, the baseband data is further processed by passing it through a transmit pulse-shaping filter. This increased spectral efficiency comes at a cost though - the modulated signal now has a variable envelope, with information contained in both the amplitude and phase variations, thus necessitating the use of linear amplification to avoid spectral regrowth. Spectral regrowth is highly undesirable in the transmitter as it results in the energy from the signal spectrum spilling over into the adjacent channels.

31 20 The 3GPP linearity specification is critical for WCDMA transmitters and is characterized mainly by the Adjacent Channel Leakage power Ratio (ACLR). ACLR is defined as the ratio of the mean power centered on the assigned channel frequency to the mean power centered on an adjacent channel frequency. It is a measure of the low-order (3 rd & 5 th order) non-linearities in the transmitter chain. The ACLR specification for the entire transmit chain is defined as follows, and must be met over the entire range of transmitter output power. Adjacent Channel Leakage power Ratio (ACLR1) = -33 dbc, at ±5 MHz offset. Alternate Channel Leakage power Ratio (ACLR2) = -43 dbc, at ±10 MHz offset. Since the power amplifier is expected to dominate the transmitter linearity budget, the ACLR specification for the upconverter driver amplifier cascade is set to be 10 db backed-off from the above 3GPP transmit chain specification. Thus, the ACLR specification at the Driver Amplifier output is given as: ACLR1 = -43 dbc, at ±5 MHz offset. ACLR2 = -53 dbc, at ±10 MHz offset. By the same token, in order to ensure that the upconverter has a minimal impact on the ACLR at the driver amplifier output, the ACLR requirement at the upconverter output is backed-off by another 10 db. So, the ACLR specification at the upconverter output is set at: ACLR1 = -53 dbc, at ±5 MHz offset. ACLR2 = -63 dbc, at ±10 MHz offset. Spectral leakage into the adjacent channels, as mentioned earlier, is a direct fallout of intermodulation resulting from non-linearities in the transmitter. This idea is illustrated in the spectrum shown in Figure 2.2. Here, a 2-tone signal, with a tone spacing of 4 MHz, is used to represent the desired variable envelope modulation within the channel centered about 1950 MHz. As highlighted using different colors, each channel has an allocated bandwidth of 5 MHz, and there are no guard frequencies between channels. Also shown are the 3 rd order and 5 th order intermodulation products. Looking at the spectrum it is clear that the 3 rd order intermodulation products

32 21 Figure 2.2: Relating ACLR to Intermodulation Performance (IM 3 ) lie in the adjacent channels and the 5 th order intermodulation products (IM 5 ) in the alternate channels. Thus, Adjacent Channel Leakage power Ratio (ACLR1) is directly related to IM 3, while the Alternate Channel Leakage power Ratio (ACLR2) is directly related to IM 5. This observation establishes the link between system-level linearity specifications and circuit related non-linearities. Justifying the 10 db back-off in the ACLR specification The following section rationalizes the 10 db back-off in the upconverter ACLR specification from the ACLR specification at the driver amplifier output. The derivation of the driver amplifier ACLR specification from the overall transmitter ACLR specification is based on parallel lines. For a moment, consider the driver amplifier to be characterized by a non-linear transfer function of order 3, and have a stand-alone IM 3 performance of -43 dbc.

33 22 (a) No IM 3 components present at upconverter output (b) IM 3 components present at upconverter output Figure 2.3: Impact of upconverter ACLR on the cascaded ACLR performance of upconverter & driver amplifier

34 23 Figure 2.3(a) shows the output spectrum of the driver amplifier in response to a 2-tone stimulus provided by the upconverter. Note, in this case, the stimulus provided by the upconverter is an ideal 2-tone signal, with no intermodulation products. In addition to the amplified fundamental tones, the output spectrum of the driver amplifier contains the 3 rd order intermodulation products with an IM 3 of -43 dbc. Next, if the stimulus provided by the upconverter is also made to include its 3 rd order intermodulation products with an IM 3 of -53 dbc, then, as shown in Figure 2.3(b), the Driver Amplifier output at the 3 rd order intermodulation frequencies will have 2 components: 1. Component 1 Resulting from 3 rd order intermodulation in the driver amplifier. (P UP C + G DA 43)dB. 2. Component 2 The intermodulation products already present at the output of the upconverter, and amplified by the driver amplifier. (P UP C 53+G DA )db. Note here that the magnitude of Component 2 is 10 db lower than that of Component 1. In the worst case, both the 3 rd order components would have the same phase and hence the powers would add constructively. As indicated in the aside in Figure 2.3(b), the addition of two power levels differing by 10dB, i.e., (P ) db and (P 10) db, causes the total power level to increase by db. This result can be easily proved as follows: (P ) db + (P 10) db P + 0.1P = 1.1P (P ) db + 10log 10 (1.1) = (P ) db Thus, the worst case addition of Component 1 and Component 2 results in a net increase of db in the total 3 rd order power level seen at the driver amplifier output. Consequently, cascading the upconverter and the driver amplifier blocks entails an IM 3 degradation of just db at the driver amplifier output. A similar rationale applies to the cascaded IM 5 performance of the upconverter and driver amplifier.