ANNEX SR-TR-ATCA. Design Guidelines. 9 July (Ana Fernandes, Rita Pereira) REVISION 0.05

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1 NNEX S-- eign uideline 9 July 2009 (na Fenande, ita Peeia) EVISION 0.05 hi document decibe the egite ettled fo communication pupoe between digitize module (fimwae (FW)) and the hot (die). hee egite mut be pope defined by hot (ue) in ode to hae a coect opeation of the module. wo PIe adde pace ae aailable fo hot/module inteaction: - B 0 1Byte PIe memoy pace - cquied data fom module i only poible though packet, eading equet ae not poible though thi B. - B 1-128Byte memoy pace llow hot to configue the module behaio though configuation egite and to download file to the module. Section 1 decibe the module configuation egite. example, a imple inteaction between module (FW) and hot (die) i explained at ection 2. FW. Hot may change not ued egite, howee thee change do not influence the boad behaio until an upgade in 1. Boad egite able 1 how the module configuation memoy egite. he memoy tat at B1 adde ettled by the BIOS o the OS in the PIe configuation pace. eiion I Statu 0x0000 ommand Pot igge (Stat elay) 0x0004 0x0008 Byte Size Buffe Numbe 0x000c uent Buffe Intnt NPuleEent_H1 File with paamete dde 0 dde 1 dde 2 0x0010 0x0014 0x0018 0x001c 0x0020 0x0024 0x

2 dde 15 N_Sample emoy boad adde (E_INI_) ata Poceing Pule Paamete & hehold cquiition Byte Size (_BYE_SIZE) NPuleEent_H2 NPuleEent_H3 NPuleEent_H4 0x005c 0x0060 0x0064 0x0068 0x006c 0x0070 0x0074 0x0078 0x007c able 1: igitize module configuation memoy. he next ub-ection explain each of the function egite and intenal tuctue. ummaized iew of thi tuctue can be found at the end of thi ection. 1.1 eiion I egite NE: eiion I WIH: 8 bit hi egite, howed in able 2, infom the hot about function implemented in the module (like timing uppot, packet heade, debugging capability and othe). ll field ae ead only and contant duing boad opeation ei H B able 2: eiion I egite layout. ei - efine the eion counte of the module FW. Each new FW eion may hae a diffeent behaio, o thi egite allow the die oftwae adjuting itelf to pecific module eion. pe packet iing infomation - hi bit mut be et if the module implement timing infomation on a pe acquiition bae. iming infomation ouce can be of any type and can alo be ead fom the N heade, if peent. hi bit detemine if the timing infomation pe packet i enabled o not in the command egite; the alue mut be checked at tatup fom the deice die oftwae. Not ued. H pe packet N Heae - hi bit mut be et if the module can be teated a a N packet geneato. hi bit detemine if the N heade pe packet i enabled o not in the command egite. he alue mut be checked at tatup fom the deice die oftwae. Not ued. B Infom the hot if debugging pin ae peent on the module. If thi bit i et, debugging extenion i aailable. 1.2 Statu egite NE: Statu WIH: 24 bit hi egite infom the hot about the tatu of the module, to eet and to acknowledge inteupt equet. etected eo fom the module ae alo publihed hee. Following thee ule thi egite i not witable, the content of thi 61

3 egite i only changed by the FW duing opeation. egite layout i howed in able P F P P L P E F F F SLO L L L S I I S S NUBE L L F F H 2 1 L E 0 E F B N SLO NUBE efine module addee. able 3: Statu egite layout. PLL2 Block2 PLL tatu - hi bit field infom the hot if the PLL i locked (efeence clock ynchonize the PLL output if the PLL i locked). eading and witing thi field doe not change it condition. Not ued. PLL1 Block1 PLL tatu - hi bit field infom the hot if the PLL i locked (efeence clock ynchonize the PLL output if the PLL i locked). eading and witing thi field doe not change it condition. Not ued. PLLLB lobal PLL tatu - hi bit field infom the hot if the PLL i locked (efeence clock ynchonize the PLL output if the PLL i locked - fo example, all output ae ynchonized with JE clock if the PLL i locked). eading and witing thi field doe not change it condition. Not ued. SE/lae efine which module ae the mate and the lae: 1 the boad i ate; 0 the boad i Slae. ENION! he mate boad i alway placed at logical SLO 3 othewie i a lae boad. If no boad i placed at SLO 3 all boad ae een a lae and thee aen t any extenal clock and tigge. S Fimwae doe not hae thi poblem a the ytem opeate with only one of thi module and the module i ettled a mate, wheee it i placed. - efine the module a a ea anient odule. Not ued. FSH FluSH data on eet - Setting thi bit (in conjunction with S) the boad eet with data fluh befoe. he data fluh can only be done if an acquiition i in place. Not ued. S ese - Setting thi bit let the hot to eet the boad. When a eet i needed et thi bit and poll it until it change to zeo; the boad i then completely eet (etun to powe on condition). PIe ubytem mut be eetted without loing BIOS o OS alue. FP_N efine the two block FP of the module: 0 - BLOK 1FP; 1 - BLOK 2 FP. E0 Eo 0 - Eo condition zeo, may be ued to ignal to the hot that omething wa going wong. eading thi bit doe not affect it content; a wite acknowledge the eo epot. Not ued. FIFE FIFo Empty - Infom the hot about FIFO cuent tate, ettled when FIFO i completely empty. eading and witing thi field doe not change it condition. Not ued. FIFF FIFo Full - Infom the hot about FIFO cuent tate, ettled when FIFO i full. eading and witing thi field doe not change it condition. Not ued. omplete - hi bit goe high when a copy to hot memoy i finihed. eading the content of thi bit doe not change it tatu. Witing 1 i equied to acknowledge the inteupt and to clea the bit, acknowledge the bit e-enable ompletion inteupt fom the boad to the hot. In fat acknowledge mode thi bit i automatically cleaed. Futhe behaio of thi bit depend on the configuation elected by the ue in the command egite. uiition omplete - hi bit goe high when all data though the i toed in local boad memoy FIFO and i eady to be tanfeed to the hot memoy; i.e. when the acquiition poce i completed. Witing 1 i equied to acknowledge the inteupt and to clea the bit, acknowledge the bit e-enable cquiition ompletion inteupt fom the boad to the hot. In fat acknowledge mode thi bit i automatically cleaed. Futhe behaio of thi bit depend on the configuation elected by the ue in the command egite. 62

4 1.3 ommand egite NE: ommand WIH: 32 bit ommand egite let the hot etting all the acquiition paamete and enable o diable acquiition and tanfe. Such egite i theefoe eadable and witeable fom the hot. able 4 how the ommand egite layout O P L L O P H N I L V PLL F I N F I F I S K E S F E E ie ie ie able 4: ommand egite layout. OPL uiition ode - hi bit let the hot to chooe between IE input ignal ( 0 ) o input ignal OPLEEN (1). he default mode i 0. LO - uing data tanfe fom hot to PIe though egite 27 (ENEI) the hot mut enable thi bit. hi i only one example of how to ue thi bit egite. It i not cuently ued. uiition ode - hi bit let the hot to chooe between EOY UISIION ( 0 ) and EL IE UISIION ( 1 ). he default mode i 0. EL IE UISIION not implemented. P ata acuiition ype - hee bit let the hot elect between diffeent data acquiition type, table 5. P eciption Bit 5 Bit efault mode 0 - aw data mode Poceed data mode Segmented mode alibation mode (how fo example the tapezoid of one channel in ode to etimate the pole-zeo cancellation facto ) Poceed data coming fom PIe Not ued able 5: P egite layout. HN Hannel Numbe hi alue allow the boad to enable the numbe of input channel to acquie and to chooe between channel, table 6. HN HN Bit 9 HN Bit 8 HN B Bit 7 HN Bit 6 eciption efault - One channel acquiition (1_H_) hannel _H_ hannel wo channel acquiition (2_H_) H 1 & H _H_ hannel _H_ H 1 & H _H_ H 2 & H hee channel acquiition (3_H_) H 1 & H 2 & H _H_ H _H_ H 1 & H _H_ H 2 & H _H_ H 1 & H 2 & H _H_ H 3 & H _H_ H 1 & H 3 & H 4 63

5 _H_ H 2 & H 3 & H Fou channel acquiition H 1 & H 2 & H 3 & H 4 able 6: hannel numbe egite layout. ILV InteLeaVed ode - hee bit let the boad acquie in ingle mode o inteleaed mode between two o fou, table 7. Not ued. ILV Bit 11 Bit 12 ILV alue efault mode - Single mode wo inteleaed not ued Fou inteleaed eciption able 7: ILV egite layout. PLLF PLL onfiuation hee fou bit let the hot elect between diffeent data acquiition ate (depend on digitze block PLL VXO fequency 1Hz fo P-250 and 800 Hz fo P-400), table 8: Selection of the ata acquiition ate PLLF Bit 12 Bit 13 Bit 14 Bit 15 eciption: S VXO = 800 Hz eciption: N VXO = 1000 Hz efault - 400Hz Feq VXO 2 efault - 250Hz Feq VXO Hz Feq VXO 2 250Hz Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO Hz - Feq VXO 20 2,4,8,10,12,14 x x x x Keep the data acquiition ate alue of the lat acquiition able 8: PLLF egite layout efault mode 0000 If the LSB i 0 no configuation i allowed and PLL maintain the powe up alue defined a default in the table aboe. g_cc igge ccuacy - ethod of igge etection, table 9. Not ued in S. g_cc Bit 1 Bit 0 ethod of igge etection 0 0 ompae Pogammed hehold with ingle data ample EFUL VLUE 0 1 ompae Pogammed hehold with eage of WO data ample 1 0 ompae Pogammed hehold with eage of HEE data ample 1 1 ompae Pogammed hehold with eage of Fou data ample able 9: igge accuacy egite layout IN-FI Input FI - hi bit let the hot elect fom: (i) Haing a filteed output data by applying a finite impule filte on the input, o (ii) Haing the output data equal to the input data (default): (not implemented in S) 0 input data hough output data (default); 1 input data FI filteed output data; -FI igge FI - hi bit let the hot elect fom: (i) alculating the tigge fom a filteed input data, o (ii) alculating the igge uing the input data without filte (default): (not ued) 0 input data hough tigge calculation (default); 1 input data FI tigge calculation; 64

6 S uiition Souce - hi bit let the hot elect the clock acquiition ouce fo all the. 0 alue impoe the intenal clock ouce (which fequency i elected fom the cquiition Fequency egite) and a 1 alue elect the extenal clock ouce. Only intenal clock ouce i allowed fo the cuent fimwae. Not ued. uiition ype - hi bit let the hot elect the type of data acquiition. 0 alue configue the boad fo an one hot data acquiition while a 1 alue configue the boad fo a continuou data acquiition, in the lat type the acquiition boad automatically eam the clock line to the. In each type of acquiition the boad can geneate inteupt and tanfe. Only one hot data acquiition i allowed fo now (emoy acquiition mode). Not ued. _K ige Knowlegdment - hi bit let the hot to elect which clock edge of the tigge enable the tat acquiition. 0 elect tiggeing on falling edge and 1 on iing edge. Only iing edge i allowed fo the cuent fimwae. Not ued. E uiition Enable - hi bit tat data acquiition poce, the acquiition poce tongly depend on the peiou etting. S Statup igge - hi egite allow the hot to ettle a oftwae tigge to enable acquiition. he E bit mut be peiouly enabled. igge ode - hi egite allow the hot to chooe the tigge mode: 0 igge mode by leel; 1 igge mode by flank (diffeentiate). F Fat acknowledge - hi bit enable the fat acknowledge mode of the module. In thi mode a ead on the uent Buffe egite tigge the on boad acknowledge of the and bit in the Statu egite. hi woking mode i intoduced to educe the boad accee in a PI enionment (like in the VE5500 etup). Not ued. E Enable - hi bit enable tanfe afte a completed acquiition opeation. If thi bit i et, when an acquiition teminate the boad immediately tat a tanfe at addee pecified in the ddee aay. EiE Eo inteupt Enable - If thi bit i et, when an onboad eo i aied an inteupt i aeted. If thi bit i not et eo ae only aeted on the Statu egite with the E0, E1,... bit field. hee bit mut be acknowledged fo futhe ignaling of eo. Not ued. ie uiition complete inteupt Enable - If thi bit i et, when a data acquiition i completed the boad aet an inteupt. ie complete inteupt Enable - If thi bit i et (and the boad tanfe i enabled), afte an acquiition a tanfe to the hot memoy i tated and when i finihed an inteupt i aeted Heade featue he Heade featue that include the illutated timing and N pe packet heade i a ueful olution to maintain a timetamp on acquied data. he popoed olution i bette than haing a heade befoe and one afte becaue it doe not beak common memoy ule of the module. 1.4 Pot igge egite (Stat elay) NE: Pot igge (Stat elay) WIH: 32 bit hi field i eadable and witeable fom the hot; the content of thi field doe not affect immediately the boad behaio. t eet, thi field eet to default alue 0. Such egite detemine the delay time in econd that mut be ettled afte a ytem tat (ex: JE tigge), table 10. In fact, when the ue ettle 1 econd by witing 1, the die will end the alue 1x to the FW. hi i the coneion facto needed by the intenal counte to pefom 1 of delay. Pot igge (Stat elay) 65

7 able 10: Pot igge egite layout. 1.5 Byte Size NE: Byte Size WIH: 16 bit Byte Size Buffe Numbe able 11: Byte Size and Buffe Numbe and egite layout. he Byte Size field egite detemine the amount of byte copied duing a tanfe fom the module memoy to the hot memoy. It i deigned to let the hot pecify the allocated hot' memoy pace fo tanfe. Fo adding ome limitation to the alue ineted in thi egite ome eeed bit could be added at the ight ide (LSB) fo alignment pupoe (Byte to W coneion aleady done by fimwae) and to the left ide (SB) fo bounding pupoe (emembe the endianity). Fitly, a tanfe copie all data alue. Secondly, copie pecial heade until thee i enough pace left on the buffe baed on it Byte Size. If thee i exta pace left, the boad engine top afte copying the module memoy content; if thee i le pace than equied, the data copy poceed until Byte Size byte ae copied and then memoy i anyhow inalidate fo a new acquiition. he field i eadable and witeable fom the hot; the content of thi field doe not affect immediately the boad behaio; at eet thi field i cleaed. able 12 how the egite layout. NOE he peent fimwae eion allow a maximum _BYE_SIZE of 4096B. 1.6 Buffe Numbe NE: Buffe Numbe WIH: 16 bit When the module i mateing a tanfe, it mut know the hot buffe memoy addee (phyical addee). hoe addee fom the point of iew of the hot mut be -able chunk of memoy whee the module could acce fo copying the module memoy content. Such egite detemine the amount of entie ued in the ddee aay. uently the module limit thi egite fo 16 buffe. hi field i eadable and witeable fom the hot; the content of thi field doen't affect immediately the boad behaio. t eet, thi field i cleaed. able 12 how the egite layout. 1.7 uent Buffe NE: uent Buffe WIH: 32 bit Such egite detemine the index of cuently ued dde buffe. In fat acknowledge mode eading thi egite tigge an acknowledge on the and bit in the Statu egite. Some eeed bit could be ueful fo alignment and bounding pupoe. bette implementation of thi egite could hae thi egite and Buffe Numbe egite of the ame width. hi field i eadable and witeable fom the hot, but i alo witten fom the boad fimwae duing acquiition opeation. In fact i tongly ecommended to the deice die deelope not to wite on thi egite duing acquiition opeation. t eet thi field i cleaed. able 13 how the egite layout. uent Buffe 66

8 able 12: uent Buffe egite layout. 1.8 Inteupt count egite NE: Intnt WIH: 32 bit Fo debug pupoe, thi egite toe the numbe inteupt ent to the hot duing a memoy tanfe. hi numbe mut be equal to the total packet ent in that tanfe. hi field i eadable fom the hot. able 14 how the egite layout. Intnt able 13: Inteupt count egite layout. 1.9 Numbe of Pule Eent fom H1 NE: NPuleEent_H1 WIH: 32 bit Fo each new acquiition, the NPuleEent_H1 egite eet and incement eey time a pule in channel 1 i detected (egmented mode P 2 fom command egite). he counte top at the end of the acquiition. hi field i eadable fom the hot. able 15 how the egite layout. NPuleEent_H1 able 14: Numbe of pule eent fom channel 1 layout File with paamete NE: File with paamete WIH: 32 bit hi egite allow the loading of a file into the fimwae (32 bit binay file with a maximum ize of 4192 Byte). t eet, thi field eet to default alue 0, table 16. File with paamete able 15: File with paamete egite layout 1.11 ddee aay NE: ddee WIH: 16 dwod Each enty of thi aay i a phyical adde of -able hot memoy aea wide Byte Size. 16-enty aay wa pe-defined. t eet the aay i cleaed. able 17 how the aay tuctue. dde 0 67

9 dde 1 dde 2 dde 15 able 16: ddee aay layout Numbe of Sample to ead NE: N_Sample WIH: 32 bit hi egite define the total numbe of ample that hot want to eceie fom module, tough packet, in each eading acce. hee alue mut not exceed the half of maximum 2 capacity minu half of Buffe ize, table 18. N_Sample 1.13 emoy boad adde NE: E_INI_ WIH: 32 bit able 17: N Sample egite layout. efine the initial memoy adde (2 adde) whee the new eading acce equeted by hot hould tat, table 19. E INI able 18: emoy Init dde egite layout ata Poceing NE: ata Poceing WIH: 32 bit If the data poceing acquiition mode (P 1 fom command egite) i ettled, the hot mut peiouly define K, L, paamete, table 20. Such egite i theefoe eadable and witeable fom the hot K L able 19: ata Poceing egite layout. K - ie time of the tapezoidal hape gien in numbe of ample; only aailable at the data poceing acquiition mode (P 1); ange - 1 to 63 (2^8) (default 0); 68

10 L - he duation of the flat top of the tapezoidal hape gien in numbe ample; only aailable at the data poceing acquiition mode (P 1); ange - 1 to 63 (2^8) (default 0); - Pole zeo cancellation; only aailable at the data poceing acquiition mode (P 1); ange - 1 to (2^16) (default 0) Pule Paamete NE: Pule Paamete WIH: 32 bit Pule paamete egite i intended to let the hot define all pule paamete uch a the width of the pule, how many ample befoe pule tigge and the thehold alue fo pule detection, table 21. Such egite i theefoe eadable and witeable fom the hot P PWIH able 20: Pule paamete egite layout. P Peigata - t eet, thi field eet to the default alue. Such egite detemine how many ample befoe tigge the hot wite to memoy. ange - 1 to 63 (2^6) (default 0). PWIH PuleWidth - t eet, thi field eet to the default alue. Such egite define the numbe of ample pe pule and paamete US be a multiple numbe of 8. ange - 1 to 4095 (2^12) ( default 0). hehold - Pule detection thehold (default 0 ) - ailable at the data poceing acquiition mode (P 1)and egmented mode (P 2). ange - 1 to (2^14) ( default 0) ENION! hi alue i in bin not in olt!!! 1.16 cquiition Byte Size NE: _BYE_SIZE WIH: 32 bit he hot mut define the ize of acquiition to 2 in BYE befoe memoy acquiition tat. he default i 64B and the maximum alue allowed by the boad i 2B, table 22. _BYE_SIZE able 21: cquiition Byte Size egite layout Numbe of Pule Eent fom H2 NE: NPuleEent_H2 WIH: 32 bit Fo each new acquiition, the NPuleEent_H2 egite eet and incement eey time a pule in channel 2 i detected (egmented mode P 2 fom command egite). he counte top at the end of the acquiition. hi field i eadable fom the hot. able 23 how the egite layout. NPuleEent_H2 69

11 able 22: Numbe of pule eent fom channel 2 layout Numbe of Pule Eent fom H3 NE: NPuleEent_H3 WIH: 32 bit Fo each new acquiition, the NPuleEent_H3 egite eet and incement eey time a pule in channel 3 i detected (egmented mode P 2 fom command egite). he counte top at the end of the acquiition. hi field i eadable fom the hot. able 24 how the egite layout. NPuleEent_H3 able 23: Numbe of pule eent fom channel 3 layout Numbe of Pule Eent fom H4 NE: NPuleEent_H4 WIH: 32 bit Fo each new acquiition, the NPuleEent_H4 egite eet and incement eey time a pule in channel 4 i detected (egmented mode P 2 fom command egite). he counte top at the end of the acquiition. hi field i eadable fom the hot. able 25 how the egite layout. NPuleEent_H4 able 24: Numbe of pule eent fom channel 4 layout Boad egite efeence Next cheme may be ueful a efeence cad of the digitize configuation memoy. egite 0 (32bit) offet 0 (0x0000) P F P P L P E F F H F SLO L L L S I I ei B S S NUBE L L F F H 2 1 L E 0 E F B N egite 1 (32bit) offet 4 (0x0004) 70

12 O P L L O P H N I L V PLL F I N F I F I S K E S F E E ie ie ie egite 2 (32bit) offet 8 (0x0008) Pot igge (Stat elay) egite 3 (32bit) offet (0x000) Byte Size Buffe Numbe egite 4 (32bit) offet 10 (0x0010) uent Buffe egite 5 (32bit) offet 14 (0x0014) Intnt egite 6 (32bit) offet 18 (0x0018) NPuleEent_H1 egite 7 (32bit) offet 1c (0x001c) File with paamete egite 8-23 (32bit).. offet 20 - offet 5 (0x0020-0x005) dde 0 71

13 dde 1 dde 2 dde 15 egite 24 (32bit) offet 60 (0x0060) N_Sample egite 25 (32bit) offet 64 (0x0064) E INI egite 26 (32bit) offet 68 (0x0068) ata Poceing Paamete K L egite 27 (32bit) offet 6c (0x006c) Pule paamete P PWIH egite 28 (32bit) offet 70 (0x0070) _BYE_SIZE egite 29 (32bit) offet 74 (0x0074) NPuleEent_H2 egite 30 (32bit) offet 78 (0x0078) 72

14 NPuleEent_H3 egite 31 (32bit) offet 7c (0x007c) NPuleEent_H4 73

15 2. Boad (fimwae) / hot (die) inteaction cheme hi ection biefly decibe, a example, the inteaction between module (fimwae) and hot (die) and the module behaio. - emoy cquiiton ode (default mode) 1) ie tatup Hot wite: - _BYE_SIZE (offet c) ize of each in byte; - _BUFFE_NUBE (offet c) numbe of buffe to be ued (max of 16); - _ESS (offet 20-5c) buffe adde; - N_Sample (offet 60, eg. 0-31) numbe of ample that hot want to eceie (ead) fom 2; - E_INI_ (offet 64, eg. 0-31) initial 2 eading adde; - _BYE_SIZE (offet 70, eg. 0-31) ize of new acquiition in byte. he default i 64B; the maximum i 2B; - HN (offet 4, eg. 6-9) Select the channel to be ued; - ie (offet 4, eg. 31) enable to allow SI inteupt at end of acquiition; - ie (offet 4, eg. 30) enable to allow SI inteupt at end of each packet. If anothe opeation cheme, diffeent fom the default, i deiable, othe egite may alo need be defined at die tatup. Pleae ee the digitize module egite decibed at ection 1. 2) Stat boad acquiition Hot enable E (offet 4, eg. 23); he tat ignal i ent to the boad. hi ignal can be made by oftwae enable S (offet4, eg 24), o by hadwae (S_ BKPLNE); 2.3 delay can be pogammed. If the tat i by oftwae, no delay i needed he boad tat to acquie fom S() to 2. t the end of acquiition, the fimwae diable E; 2.5 If ie i enabled, the boad end one SI inteupt and enable (offet 0, eg. 31); he hot wite = 1 and then the boad diable. t thi point (if ie =1), o at the end of point 2.3 (if ie =0) the boad i capable to end packet to the hot (eading data). 3) eading data Hot enable E (offet 4, eg 27) If thi egite i aleady enabled the eading data immediately tat at point 2.5 (if ie = 1) o at point 2.3 (if ie = 0); 3.2 he boad end the packet to the adde elected by the _UEN_BUFFE; 74

16 3.3 t the end of cuent packet the boad end one SI inteupt and enable (offet0, eg 30) (if ie=1). 4) Inteupt handle and next packet 4.1 Hot wite =1 (indiect wite); he boad diable ; Hot ead UEN BUFFE (offet 10); thi eading allow the fimwae to inceae UEN BUFFE and to tat ending the new packet (etat fom point 3.2) ; 4.4 fte eceiing all the N_Sample equied the hot diable E. 4.5 If a new eading i deied: Hot may change, if needed, the egite lited at point 1.1 (only egite elated to packet eading data); etat fom point If a new acquiition i deied: Hot may change, if needed, the egite lited at point 1.1; etat fom point 2. 5) Boad/Fimwae eet Hot wite S=1 (offet 0, eg 19) (indiect wite); 5.2 he boad enable S; when all the default condition wee eplaced, the boad diable S. EKS 1 t note: he _BYE_SIZE i defined by hot in byte, but fimwae tanlate them to dwod (1W = 4 BYE). 75