International Journal of Advance Engineering and Research Development

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1 Scientific Jounal of Impact Facto SJIF:.7 Intenational Jounal of Advance Engineeing and eeach Development olume, Iue, Novembe -7 e-issn O: 8-7 p-issn P: 8-66 otalk Modeling and Analyi of oupled Inteconnect fo Signal Integity Bhattu.HaiPaad Naik, handa Sekha Paidimay,, Dept. of EE, UE, Omania Univeity, Hydeabad, Telangana, India. Abtact With the technology advancement in the field of chip fabication, the ignal clock ate and data-ate ae in eveal Giga-Hetz ange. Simultaneouly, ignal ie time edge ate ae in Pico-econd ange. On-chip inteconnect on a multilaye boad tack-up play a vital ole and contitute a majo ouce of cicuit delay than gate delay. Thi i becaue of deceae of tace width and vaiou device paaitic on the chip. Thee can caue eveal implication uch a electo-magnetic EMI iue in the deign. Thee poblem can poe eveal deign challenge to the deigne with the Signal Integity poblem uch a inging, double clocking, non-monotonicity and pefomance degadation of deign. Typically, thee ae numeou analytical and numeical appoache ued fo the analyi of high peed inteconnect. Each appoach i diffeent fom the othe in diffeent domain of evaluation. Hee, cotalk voltage modeling and analyi of coupled G model of inteconnect with tanient analyi in time domain i popoed. Tanient analyi of lumped, coupled and ditibuted model of inteconnect i pefomed and pefomance metic delay, aveage powe, PDP and cotalk voltage ae meaued. Hence, accuate modeling and validation of inteconnect model i eential fo the ucceful tanmiion of ignal without inging, cotalk and EMI poblem. Thee educe the popagation delay and inceae the oveall cicuit pefomance in-tem of peed. Index Tem Micotip, Inteconnect/tace,, EMI, otalk, Fa End otalkfext, Nea End otalknext, Signal IntegitySI, Delay, lumped, PDP, I. INTODUTION In the deep-ubmicon DSM egime, high peed deign have fate edge ate ignal and witching fat chaacteitic. Advancement in the chip fabication technology, peent high peed logic and deign ae opeating at much highe peed. The clock ate of the ignal in high peed >MHz deign have eached the GHz ange and edge ate of the ignal doped below pico-econd ange e.g. DD, DD and DD deign and ignal fequency content of digital ignal have extended to GHz. In addition, deign on I ae becoming moe complex, complicated with deceaed tace width and malle geometie. On a multilaye boad tack-up, the effect of inceae in fequency GHz, deceae of tace width and edge ate of the ignal ae alway poing challenge to the deigne with eveal citical ignal integity poblem. Thee poblem of SI ae diectly elated to d/dt o di/dt, fat ie time that ignificantly woe ome of the noie phenomena: powe/gound witching noie, cotalk, inging, eflection and ove/hoot. Many of poblem of SI ae electomagnetic in natue efeed a EMI/EM. Thee can degade the oveall pefomance of the ytem. So, it become eential to undetand, whee thee poblem of SI come fom, analyze them and olve the poblem at the ealy tage of deign ele the poce of olving i time taking and cot effective. The fundamental goal of SI i to enue high peed, eliable data tanmiion without inging, cotalk, double clocking, nonmonotonicity etc.si i the meaue of quality of ignal QoS, detemined by quality hape with thehold and aival time of the ignal. The ignal timing depend on delay which in-tun depend on the phyical length of inteconnect, that the ignal need to popagate though. The deigne mut enue the eliability of the deign by highlighting the poblem of SI and EMI. Hence, theeby inceae the quality of ignal tanmiion that ae high peed, eliable to obtain optimum pefomance fom the deign. Inteconnect contitute a dominant ouce of cicuit delay than gate delay []. Depending on the phyical length, often inteconnect on the I ae modeled a ditibuted model with eitance, capacitance and inductance paaitic. Inteconnect delay i playing a vital ole in cicuit deign and pefomance. In a complicated multi-layeed high peed inteconnect ytem deign, popagation delay and ignal coupling geatly affect cicuit pefomance and lowe the yield of I chip. A pope cae need to be taken egading citical inteconnect pacing, dimenion, layout, and device paaitic etc., pio to deign. On a multilaye boad tack-up, cotalk i efeed a the undeied voltage impated fom a aggeo line to a adjacent tace/inteconnect victim. Magnitude of cotalk voltage induced in to a victim line i a function of ie time, tace geomety and type of temination ued. Majo impact of co talk in high peed deign ae: a otalk induce timing delay that change the ignal popagation time, and in-tun lead to etup/hold time failue. b otalk induce glitche at the output, thi caue voltage pike on inteconnect, eult in fale logic. Hence, an accuate inteconnect modeling, etimate and chaacteization of the cotalk peak noie in inteconnect i theefoe vey cucial fo today high peed deign. Model chaacteization i pefomed uing tanient analyi in time domain. The pefomance metic of coupled lumped and ditibuted model ae evaluated. The objective of thi wok i to model and analyze the cotalk coupling noie between the aggeo and a victim line of a coupled All ight eeved 7

2 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 inteconnect. Delay modeling of lumped model of i peented in ection-. Subequently cotalk modeling of coupled inteconnect in ection-. otalk analyi of ditibuted inteconnect model i peented in ection- then followed by concluion in ection-5. II. DEAY MODEING OF UMPED INTEONNET Fo SI analyi, inteconnect/tace on a chip ae eithe modeled a lumped o ditibuted model of tanmiion line that eve a medium of ending ignal. The popagation delay along the tace depend on cicuit paaitic and on the phyical length of tace. Delay modeling of lumped model of inteconnect i hown in Figue.. Hee, voltage along both end of tace change intantaneouly with popagation timetp>>pd neglected. But in a ditibuted model, the ignal popagation timetp i conideed along with length of the tace. in out Fig.. Model of Inteconnect. Apply the K to the model of inteconnect hown in Fig.. Aume that it be the cuent flowing in the model which yield equation : i t d i t i i t i t dt dt d i t t t t dt Diffeentiate the equation w..t to t yield d d d i t t t t dt dt dt d d d t i t t t dt dt dt Since the obtained equation i in time domain, ue aplace Tanfom to covet fom time domain to fequency domain fo eay analyi. i / i / / The tanfe function of lumped model of inteconnect in fequency domain i given by econd ode equation : / H / / The tandad econd ode chaacteitic tanfe function i given by equation 5. n H n n 5 On compaing the econd ode tanfe function of model i.e. equation with the tandad fom of chaacteitic equation, we obtain the paamete uch a angula fequencyw n and damping factoξ. n n, Delay τ of a lumped model of inteconnect i defined by the,, and paaitic element and i given by 6: 6 Appoximate delay τ fo ditibuted model of inteconnect of n th tage i given by 7. n n.. All ight eeved 7

3 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 Figue. how the tanient analyi of the lumped model of inteconnect with the element paamete: =5Ω, =.5nH and =9.pF. Tanient analyi i pefomed with a pule a input with edgeateie, falltime equal 5p and peiod of pule i n. Hee, inteconnect/ tace i aumed a a micotip on a PB. The length of the tace/inteconnect i = inch, width W=8. mil, Dielectic height H=6. mil with a dielectic contant chaacteitic impedance of inteconnect i Z =5Ω and the delay though the tace i td=8p... The Fig.. Tanient analyi of Inteconnect. The tanient epone of inch inteconnect i hown in Fig.. epone how that inging i peent at the output and thi i due to the inductance effect at high fequencie. Fig.. Tanient epone of Inteconnect. III. OSSTAK MODEING OF OUPED INTEONNETS A PB tackup i a multilaye boad with many ignal tace, via and powe planedd, Gnd on it. At high fequencie inteconnect/tace on a PB ae often modeled a tanmiion line i.e. micotip, tipline, etc with vaiou dielectic mateial ued a ubtate. The ignal popagate though the tace at a peed of 6 /n which equal 65p/inch appoximately. A model of coupled tace i hown in Fig.. W S Tace c Tace c Tace H. Fig.. oupled model of tace/inteconnect on a ubtate. On a multilaye boad tack-up, cotalk coupling happen when two ignal tace/inteconnect ae unning ide by ide to each othe fo ome ignificant length i.e. data line. otalk i geneated between the tace due to coupling and enegy get coupled fom one taceaggeo to the adjacent tacevictim. otalk inceae with fat edgeate<p and inging theeby inceaing di/dt. otalk poblem can be olved by placing the ignal tace in cloe poximity to the dd, Gnd plane, ue of guad tace and inceae coppe pou on the boad to deceae cuent denity. A elationhip between tace widthw and impedancez of the tace/inteconnect i given a 8: Width W Z 8 High peed deign that ae opeating at high fequencie and fat edge-ate, cotalk effect between tace/inteconnect i an undeied effect that can caue eveal SI poblem. Theefoe, accuate cotalk modelling between coupled inteconnect and chaacteization i vey eential. otalk can affect the mutual inductance M a well a coupling capacitance c=.pf between All ight eeved 7

4 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: All ight eeved 7 c M Fig. 5. Model of oupled Inteconnect. Figue.5 i ued fo theoetical modeling and analyi of cotalk voltage in a coupled inteconnect. Analyi i pefomed with aumption = Gnd and the coupling coefficient between the inducto and i K=.. The cotalk voltage induced by aggeo line on to ictim line ae of two kind i.e. Fa End otalk FEXT at a output and Nea End otalk NEXT at ae etimated fo a coupled inteconnect model hown in Fig.5. Now applying the nodal analyi to coupled model of inteconnect hown in Fig.5. / / 9 * * / / * * The output voltage of the aggeo tace w..t input voltage i obtained by ubtitution of equation in. * * c * Theefoe, output voltage of the aggeo tace with victim tace gounded = i given by equation. * c The cotalk voltage, FEXT at the end of victim tace becaue of coupling of aggeo tace i calculated a follow. Hee equation can be i e-witten a: * Subtitute value of in equation to obtain the theoetical expeion fo cotalk voltage FEXT on the victim tace. On implifying the above equation, cotalk voltage FEXT i deived a in equation 5. * 5 Similaly, theoetical expeion fo cotalk voltage NEXT i deived a in equation 6. c 6

5 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 A. Tanient Analyi of oupled Inteconnect The tanient analyi objective i to evaluate the amount of cotalk voltage injected on to victim tace due to both capacitive and inductive coupling. Duing analyi, inteconnect/ tace i aumed a a micotip on a multilaye PB of length = inch, width W=8. mil, Dielectic height H=6. mil with a dielectic contant..the chaacteitic impedance of tace i Z =5Ω and the delay though the tace i t d=8p. The tace element paamete ae: =5Ω, =5Ω, = =9.pF, =.pf, = =.5nH, K=.. Theefoe with thee paamete the output voltage obtained on the aggeo line i given in equation 7..75e e e e e-9 +.e- + 7 otalk voltage FEXT, on ictim i given in equation 8..5e- + e e e e-9 +.e- + 8 otalk voltage NEXT, on ictim i given in equation 9. e -.6e e- +.e - 9 The tanient analyi of two inche coupled tace/inteconnect hown in Fig.6. i pefomed fo a iing, falling edge-ate of 5p epectively. A pule i applied on the aggeo tace with victim tace = a gounded. Fig. 6. Tanient Analyi of oupled Inteconnect. Fig. 7. FEXT and NEXT epone of oupled Inteconnect. Figue.7 how the cotalk voltage epone of a coupled epectively becaue of the affect of aggeo on to the victim tace. FEXT voltage i m peak-to-peak and NEXT voltage 5 m peak-to-peak. FEXT voltage > m could caue eveal ignal integity All ight eeved 7

6 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 Fig. 8. Tanient Analyi of oupled, and G Inteconnect. The tanient analyi of all coupled, and G tace/inteconnect i hown in Fig.8. otalk voltage FEXT epone of, and G tace i hown in Fig.9. Fig. 9. FEXT epone of oupled, and G Inteconnect. B. Effect of Mutual Inductance M on oupled Inducto At high fequencie, eactive component inductance ceate numeou ignal integity poblem i.e. inging due to inductive coupling. The inducto and ae coupled with coupling coefficient K < K < o a to obtain minimum cotalk. M K * An exta inductance get added becaue of the coupling between the inducto coil and and i called a mutual inductance M. M T M K * All ight eeved 75

7 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 Fig.. epone fo diffeent value of K and on oupled Inteconnect. Paametic imulation epone of inch coupled tace fo diffeent value of coupling coefficient K=.:.:.5 and coupling capacito =.5:.5:. i hown in Fig.. Thi help to find the optimal value of K and o that the cotalk voltage FEXT, on the victim tace i a low a poible. Fom the imulation eult it i evident that fo K=. and =.pf the cotalk voltage on the victim tace i low. In a inch coupled tace inducto and ae coupled though a mutual inductance M which add an exta inductance on to inteconnect. In ode to obeve the effect of M on and two tet cae have been conideed. The tep epone fo output voltage, FEXT and NEXT voltage epone epectively with elected optimum value of K=., =.pf and = =.5nH, M=.5nH ae hown in Fig., Fig. and Fig.. ae i: -M and -M =.5nH-.5nH =8nH.98e 9.65e.79e 8 6.e 9.e 9.e.79e 8.e 9 6.e 9.e 9.e.8e.9e 9.6e ae ii: +M and +M =.5nH+.5nH = 7nH.97e 9.65e 8.5e 8 9.8e 9 6.e 9.e 8.5e 8.8e.87e 9.6e.6.. Step epone.8e 9 9.8e 9 6.e 9 out@.5nh out@8nh out@7nh.e Amplitude Time ec x -8 Fig.. Analyi of out with =.5nh, 8nH and All ight eeved 76

8 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 Step epone Amplitude Time ec x -8 Fig.. FEXT oltage with =.5nh, 8nH and 7nH. Step epone.5 Next@.5nH Next@8nH. Next@7nH.5 Amplitude Time ec x -8 Fig.. NEXT oltage with =.5nh, 8nH and 7nH. A. Ditibuted model of inteconnect I. OSSTAK ANAYSIS OF DISTIBUTED MODE Fig.. Tanient Analyi of Ditibuted model of inteconnect. The tanient analyi of ditibuted model of tace/inteconnect i obtained by cacading of lumped i hown in Fig.. inteconnect/ tace i on a PB i aumed a a micotip of length =5* inch=5 inche, width W=8. mil, Dielectic height H=6. mil with a dielectic contant..simulation epone i hown in Fig.5, which how that the delay and time of flight have inceaed when compaed with eult in Fig.. A compaion of lumped and ditibuted model i lited in Table II. Fig. 5. Tanient Analyi of Ditibuted model of All ight eeved 77

9 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 B. Ditibuted oupled inteconnect model Fig. 6. Tanient Analyi of Ditibuted oupled model. Tanient Analyi of micotip tace of coupled length =5* inch=5 inche, width W=8. mil, Dielectic height H=6. mil with a dielectic contant. on a multilaye PB i hown in Fig.6. The two tace ae coupled though capacitive coupling c=.pf.the tanient epone fo output voltage and cotalk voltage FEXT and NEXT ae hown in Fig.7 and Fig.8. Fig. 7. Tanient epone of Ditibuted model of oupled. FEXT voltage i 68 m peak-to-peak and NEXT voltage 8 m peak-to-peak. Typically, FEXT voltage > m could caue eveal ignal integity poblem. Fig. 8. FEXT and NEXT epone of Ditibuted oupled Inteconnect. Figue.9 and Table-I how the cotalk voltage FEXT epone of all the ditibuted coupled model of, and G tace/inteconnect with micotip All ight eeved 78

10 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 Fig. 9. FEXT epone of Ditibuted oupled, and G Inteconnect. TABE I. OMPAISON OF OSSTAK OTAGES OF OUPED INTEONNETS. Type of Model umped oupled Model Ditibuted oupled Model NEXT m FEXT m NEXT m FEXT m G Table I lit the compaion of cotalk voltage FEXT and NEXT fo coupled model of tace/inteconnect in a tanient analyi. TABE II. OMPAISON OF DEAYS AND POWE IN INTEONNETS. umped Model Ditibuted Model G Delay p Avg Powe uw PDP Joule 8.69 e-.85 e-.55 e- Dela y n Avg Pow e mw PDP Joul e 5.56 e-. e-.5 e- TABE III. OMPAISON OF DEAYS AND POWE IN OUPED INTEONNETS. G oupled umped Model Delay p Avg Powe uw PDP Joul e. e-.58 e-.56 e- oupled Ditibuted Model Delay n Avg Powe mw PDP Joul e 8.85 e- 6.8 e- 6.8 All ight eeved 79

11 Intenational Jounal of Advance Engineeing and eeach Development IJAED olume, Iue, Novembe-7, e-issn: 8-7, pint-issn: 8-66 The length of the tace/inteconnect alo detemine the delay and timing of output ignal. The amount of delay fo a given length vaie fom laye to laye on a multilaye PB. Table II lit the compaion of delay, aveage powe and powe delay poduct PDP in lumped, ditibuted model. Table III lit the compaion of coupled lumped model and coupled ditibuted model of inteconnect with SPIE imulation.. ONUSION In thi pape, an appoach fo modeling and analyi of cotalk noie voltage in a coupled model of tace/ inteconnect i popoed. Thi i ued to detemine the cotalk coupling effect between the two on-chip tace viz: aggeo and a victim tace. The effect of inductive co-talk, capacitive cotalk, and coupling ae conideed fo vaiou combination coupling coefficient K and c on the aggeo and victim line. haacteization of all model of G tace in time domain ae pefomed with popetie of micotip a tace on a multilaye PB. In the tanient analyi cotalk voltage metic FEXT, NEXT ae meaued and compaed fo each coupled model of inteconnect. The modeling appoach can be ued fo fat etimation of cotalk voltage in coupled tace. A detailed SPIE analyi of all, and G tace model ae pefomed fo popagation delay, aveage powe and powe delay poduct PDP. A compaion of all model of inteconnect with metic ae lited in table. EFEENES [] Semiconducto Indutie Aociation SIA, Intenational Technology oadmap fo Semiconducto ITS, 7. [] hen Wei, Huang Qiu-yuan, Zhou Peng, "Signal Integity Analyi and Deign in High Speed icuit M" in PHEI, Beijing:, pp. 5-6, 9. [] JianQiang Mo, "High-peed Digital icuit Signal Integity Analyi", Electonic Tet, vol. 9, no. 9, pp. 5-9,. [] A.B.Khang, S.Muddu, An Analytical Delay Model fo Inteconnect, IEEE Tan. ompute Aided Deign , 997. [5] Y. I. Imail, E. G. Fiedman, and J.. Neve, Equivalent Elmoe delay fo tee, IEEE Tan. omput.- Aided Deign Integ. icuit Syt.,vol. 9, no., pp. 8 97, Jan.. [6] ika Mahehwai, Abhihek Shama,.Ka, Tanient and Delay Analyi fo On-hip High Speed SI G Global Inteconnect fo Unit Impule Input, IEEE, onfeence on eeach and Development,. [7] ajib Ka, A. K. Bhattachajee,ika Mahehwai Delay Model fo SI G Global Inteconnect, IEEE, PIMEASIA,. [8] Souajeet oy, Aneti Dounavi, Efficient Delay and otalk Modeling of Inteconnect Uing Delay Algebaic Equation, IEEE Tan. On SI Sytem, vol.9, no.,. [9] Muhammad Sanaullah and Maud H. howdhuy, Analyi of Inteconnect Delay Model uing Second Ode Appoximation IEEE, Sympoium icuit and Sytem,. [] Sunil Jadav, ajeevan handel Munih ahihath A Supeio Delay Etimation Model fo SI Inteconnect in uent Mode Signaling, Wold Academy of Science, Engineeing and Technology, 5. [] Mutafa elik, awence Pileggi, Altan Odabaioglu I Inteconnect All ight eeved 7