All-Digital DPWM/DPFM Controller for Low-Power DC-DC Converters

Transcription

1 All-Digital DPWM/DPFM Contolle fo Low-Powe DC-DC Convete Kun Wang, Nabeel Rahman, Zdavko Lukic, and Alekanda Podic Laboatoy fo Low Powe Management and Integated Switch-Mode Powe Supplie Depatment of Electical and Compute Engineeing, Univeity of Toonto Toonto, ON, CANADA Abtact A digital contolle fo dc-dc witching convete ued in battey-poweed handheld device i intoduced. The contolle can opeate in two mode and encompae novel deign of a digital pule-width modulato (DPWM) and an alldigital pule-feuency modulato (DPFM). The DPWM ha a high eolution and can opeate at vey-high contant witching feuency (ten of MHz). The DPFM featue veylow powe conumption, pogammable on-time and contol ove witching feuency ange. An expeimental FPGA pototype and an application-pecific IC that employ new contolle achitectue ae built aound 3.3 V, 3W, 6 MHz buck powe tage and ucceful opeation of the digital contolle in both mode i veified. The low powe conumption ha been alo veified on a chip implemented in a tandad CMOS 0.18um poce. I. INTRODUCTION Digital contol of low-powe witching convete allow numeou benefit including the ability to ue digital deign tool, flexibility in tanfeing to diffeent implementation technology, and low enitivity on extenal influence [1-6]. Howeve, in battey-poweed handheld device, uch a cell phone, digital till camea (DSC), and peonal data aitant (PDA), analog contolled dc-dc witching convete ae pedominantly ued. Among the main obtacle fo ucceful digital implementation ae lowe witching feuency, compaed to analog olution, and the abence of low-powe digital achitectue that can uppot pule-feuency modulation (PFM). The PFM eult in ignificant efficiency impovement when the output load of SMPS ae light. In handheld device, to extend the battey life, the PFM i uually ued when the upplied device pefom imple poceing tak o opeate in tand-by mode. In ecent publication eveal low-powe olution that eithe uppot only digital pule-width modulation contol o combine a digital-pule width modulato (DPWM) and an analog PFM have been peented [7-10]. With the exception of the DPWM demontated in [11] mot of the peented olution opeate at much lowe feuencie than the analog contolle. On the othe hand, digital pule-feuency modulato (DPWM) demontated in [12] have not been utilized in low powe witching convete. To ceate a pule-feuency modulated ignal, often chaacteized with hot on and long off time inteval, thee ealization ue high feuency clock and employ powe-inefficient counte, which make them unuitable fo low-powe application. In thi pape we intoduce a novel all-digital DPWM/DPFM contolle that can be ued in low-powe SMPS and eaily tanfeed fom one implementation technology to anothe. The contolle, hown in Fig 1, utilize novel achitectue of DPFM and DPWM. The DPWM opeate at witching feuencie compaable to the fatet analog olution today [13,14] and can be implemented with a low-powe digital hadwae. The DPFM i baed on a new acing ing achitectue that alo povide vey low powe conumption and opeation without an extenal clock. In addition, the DPFM utilize advantage of digital contol and offe new featue not commonly een in analog implementation. It offe digital contol of the ontime (maximum tanito cuent) and contol of the ange of witching feuency opeation, which can be ued to eliminate undeiable feuency component that can influence upplied device. Depending on the value of the extenal mode ignal m(t), the ytem of Fig.1 opeate eithe a a digital pule-width o pule-feuency modulato. In pule-width modulation mode it opeate in a imila manne a the ytem peented in [8]. V in m(t) SW1 c 1 (t) Dead-Time c(t) DPWM DPFM c 2 (t) SW2 d clk Digital Contolle L + _ C PI/PID Compenato Load e v out (t) H 1 A/D H 1 v out V ef Thi wok of Laboatoy fo Low-Powe Management and Integated SMPS i uppoted by Sipex Copoation and by Natual Science and Engineeing Reeach Council of Canada (NSERC). Fig. 1. Buck Convete egulated by all-digital DPWM/DPFM Contolle

2 Baed on the value of the eo ignal a look-up table baed PID compenato ceate a contol ignal fo DPWM. When opeating in pule-feuency mode a imple PI compenato law i ued. In thi cae the compenato ceate a contol ignal fo DPFM, which i popotional to the witching feuency. In the next ection, the achitectue and opeation of the DPWM ae explained. In Section III, we decibe the pogammable DPFM. Section IV peent the expeimental eult obtained with an FPGA -baed contolle that employ thi new contolle achitectue. In thi ection we alo how eult obtained fom an application pecific IC utilizing thi contol method. II. HIGH-FREQUENCY DIGITAL PULSE-WIDTH MODULATOR BASED ON SEGMENTED RING The new DPWM hown in Fig.2 i a modification of egmented DPWM achitectue [15] that doe not euie an extenal clock to opeate. The achitectue alo eemble the DPWM achitectue baed on a ing ocillato [16], with the diffeence hee being that the ize of thi tuctue, fo 8-bit implementation, i educed to 1/15 of the oiginal. The ing-baed egmented achitectue hown in Fig. 2 i an 8-bit DPWM. It conit of two 16:1multiplexe and two et of delay line connected a a ing. The fit delay line conit of 16 fat delay element in eie. Each intemediate node i paed onto a 16:1 multiplexe (MUX- A), whoe elect ignal ae the 4 leat ignificant bit (LSB) of the digital input d (ee Fig.2). MUX-A i eponible fo the fine eolution of the DPWM, a it i contolled by the 4 LSB of d. The econd delay line conit of 15 low delay element in eie. Thee delay ae 16 time lowe than the fat delay element. The output of low delay ae connected to a econd 16:1 multiplexe (MUX-B). The elect ignal fo the MUX-B ae the 4MSB of d connected in evee ode, uch that the MSB of d i tied to the LSB of MUX-B. In thi way, the 4MSB of d define the tat point of the pule-width modulated ignal, that et the SR latch. The 4LSB of d, connected to the elect input of MUX-A, ae not eveed and define the end point of the faction of witching peiod duing which the PWM ignal i high. Thi connection alway enue that the ignal top point i defined by 4LSB and hence an accuate duty atio adjutment i achieved. Fo example, when the input d i a high binay input, , which coepond to a duty atio value of , the PWM wavefom i ceated a follow. A the ignal i popagating though the delay cell, it et the SR latch at MUX-B I14. Then it goe though 14 low cell (becaue the MUX-B input i 1101), move though eight fat cell and eet the latch at MUX-A input I8 (becaue the MUX-A input i 1000). When the input value d i mall, , the ing ocillato ignal et the SR latch at MUX-B I1, move though jut one low and one fat cell and eet the latch afte that. A a eult, a mall duty atio value i obtained. It can be een that the DPWM can be implemented with vey mall hadwae. It take only 1/15 of the eouce needed fo the implementation of a conventional 8-bit ing-ocillato baed DPWM that employ a lage 256:1 multiplexe. A. DPWM Lineaization Poblem A decibed in [15] egmented DPWM tuctue uffe fom nonlineaity poblem. The mimatch between fat and low delay cell in ome cae can caue the chaacteitic of the DPWM to become nonmonotonic and caue intability of the ytem, due to effective poitive feedback. In mixed-ignal IC implementation both thi poblem and tabilization of the witching feuency can be olved uing imple DPWM lineaization block demontated in [16,17]. In that olution a eplica of fat delay line and cutom made pogammable delay cell ae ued. The delay of 16 fat delay cell i matched to be exactly the ame a the delay of a low cell. d 8-bit 4-bit 4-bit Fat Delay Line Slow Delay Line Enable d LSB d MSB MUX-A MUX-B c(t) S Q R Fig. 2. Ring-baed egmented DPWM

3 III. RACING RING BASED PROGRAMMABLE DIGITAL PULSE-FREQUENCY MODULATOR One of the main challenge in deigning a low-powe digital pule-feuency modulato (DPFM) i the ceation of long time inteval uing vey fat digital logic. Since the witching peiod of SMPS opeating in DPFM ae eveal ode of magnitude lage than the popagation time of moden digital cicuit, diect implementation of olution ued in DPWM achitectue i impactical. Conventional ing ocillato would euie thouand of delay cell and huge on-chip aea. On the othe hand, counte-baed DPFM achitectue [12] conume ignificant amount of powe and ilicon aea, epecially if a lage ange of feuencie ae euied. In potable application, thee method ae endeed uele due to thei high powe conumption. The novel ignal-ace baed DPFM achitectue i hown in Fig. 3. It allow ceation of vey long time inteval uing fat digital logic and can be implemented with low powe hadwae. The DPFM opeation i baed on the ace of two ignal aound a ing ocillato whee one ignal tat fit and the econd ignal, which popagate a little bit fate, tat a little bit late. Once the fate ignal catche the fit one the ace i ove. The peiod of the DPFM ignal i defined by the time diffeence between the tat of the fit ignal and the end of the ace. In thi cae the duation of the ace, i.e. witching peiod, i popotional to the time pacing between the two tat ignal and inveely popotional to the peed diffeence of the two ignal, i.e. time delay of digital logic. The achitectue of Fig.3 ha thee majo functional block, the DPWM decibed in the peviou ection, the End of Race detecto (EoR), and a ing ocillato that compie of SR latche and pogammable delay cell. In thi cae, the DPWM opeate with a boken ing and i tiggeed extenally, i.e. opeate in the ame manne a conventional egmented DPWM [15]. The DPWM ceate a hot pule, whoe iing and falling edge detemine the time-paced acing ignal (on-time of DPFM ignal). Initial tate of all the SR latche ae zeo. When the DPWM geneato poduce the poitive edge, the fit SR latch will be et to high. In tun, the output of the fit SR latch will et the econd SR latch. Thi i illutated in Fig. 3 a a poitive edge popagating on the uppe tack. When the DPWM geneato poduce the negative edge, the fit latch will be eet to zeo afte being peviouly et by the poitive edge. The output of the fit latch will eet the output of the econd latch. Thi i hown a a negative edge going down the eet line. Hence the poitive and negative edge will tat to chae each othe aound the SR latch ing, becaue the delay of the et delay block on the et line i made to be lightly bigge than the delay of the not gate. The delay of the DPFM i again contolled by the DPWM. Once thee pule catch up to each othe, all the output of the SR latch will become zeo, indicating that the ace ha ended. Each time the end of ace condition i detected by the EoR block, a new ignal fo the DPWM i ceated and the ace tat again. It hould be noted that thi contol cheme povide egulation of both the witching feuency and the on-time. IV. EXPERIMENTAL RESULTS Baed on the diagam hown in Figue 1 to 3, an expeimental ytem wa built aound an FPGA ytem. A a powe tage, a buck convete i ued and the contolle i ealized with a Xilinx Spatan-3 FPGA boad. A hown in Fig.1, in both mode, the witching convete i egulated with the ame contolle, coniting of a windowed analog-to-digital convete (ADC), digital compenato and the combined DPWM/DPFM decibed in peviou ection. No extenal clock i needed a in both cae the clock feuency of the ytem i the ame a the witching feuency, eulting in vey low powe conumption in DPFM and fat contol in DPWM. Mode election i pefomed with the extenal mode ignal. A. DPWM Opeation Figue 4 and 5 demontate DPWM opeation of the contolle. Figue 4 how teady-tate opeation. It can be een that the convete opeate at a vey-high contant witching feuency of 6.2 MHz, which i compaable to cutting edge analog integated olution. Figue 5 d DPWM with Boken Ring End of Race pfm-c[t] Fig. 3. All-digital DPFM

4 demontate that the contolle alo exhibit fat tanient epone. B. DPFM Opeation DPFM opeation i illutated with Fig. 6 and 7. Figue 6 demontate opeation of DPFM in open loop. It how how the digital contol ignal, d affect the pulefeuency modulated output. It can be een that the change of d immediately influence the feuency of the pulefeuency modulated ignal. Opeation of the DPFM in cloed loop i hown in Fig. 7. Fom the contol ignal d and output voltage v(t) it can be een that the contolle i able to povide good egulation of the output voltage by changing the feuency of opeation. ae hown in Fig. 8 and thei chaacteitic ae given in Table I. A it can be een the novel achitectue allow opeation at vey-high witching feuencie and ha vey mall powe conumption, compaable to tate of the at analog PFM olution. f w = 6.2 MHz Fig. 6. DPFM opeating in open loop. Ch.1: c(t) DPFM ignal. D0-D4: digital contol wod d Fig. 4: DPWM opeating at 6.2 MHz. Ch.1: egulated output voltage v(t); Ch.2: Gate dive ignal Fig. 7. Cloed loop DPFM opeation. Ch.1: v out(t); D0-D4: Digital contol wod d TABLE I- PARAMETERS OF ON-CHIP IMPLEMENTED DPWM AND DPFM Aea Feuency ange Cuent con. DPFM mm 2 20 khz to 250 khz 3 µa DPWM mm 2 1 MHz to 20 MHz 5 µa/mhz Fig. 5: DPWM load tanient epone. Ch.1: v(t); Ch.2: load tanient contol ignal. C. On-Chip Implementation In addition to the FPGA implementation, the DPWM and the DPFM have alo been implemented on a CMOS 0.18um, a a pat of moe complex low-powe management IC decibed in [16,17]. The layout of the DPWM and DPFM V. CONCLUSION Thi pape intoduce a novel digital achitectue of a DPWM/DPFM contolle fo low-powe dc-dc witching convete. The contolle i all-digital, and it deign can be eaily tanfeed fom one implementation technology to anothe. It alo meet the euiement of vey high feuency of opeation in DPWM mode and vey low powe conumption in the DPFM euied fo low-powe potable and handheld device. Expeimental FPGA pototype demontate opeation at a vey high contant witching

5 feuency of 6.2 MHz, a well a effective voltage egulation in DPFM opeation. Futhemoe, on-chip implementation of thi achitectue veifie ulta-low powe conumption, compaable to tate of the at analog olution. 0 um 1200um 0 um DPWM DPFM Fig. 8. Layout of DPWM and DPFM implemented in a tandad CMOS 0.18um poce REFERENCES [1] D. Monticelli, Sytem appoache to powe management in Poc. IEEE APEC Conf., 2002, Febuay 2002, pp [2] A.Podic and D. Makimovic, Digital PWM Contolle and Cuent Etimato fo a Low-Powe Switching Convete, in Poc. IEEE COMPEL Conf., 2000, pp [3] A.V. Petchev, S.R. Sande, "Digital Lo-Minimizing Multimode Synchonou Buck Convete" in Poc. IEEE PESC'04 Conf., 2004, pp um [4] J. Xiao, A. Petechev, J. Zhang, S.R. Sande, An Ulta Low-Powe Digitally-Contolled Buck Convete IC fo Cellula Phone Application, in Poc. IEEE APEC 04 Conf., 2004, pp [5] E. O'Malley, K. Rinne, A Pogammable Digital Pule Width Modulato Poviding Veatile Pule Patten and Suppoting Switching Feuencie Beyond 15 MHz, in Poc. IEEE APEC 04 Conf., 2004, pp [6] A. Podic, R.W. Eickon and D. Makimovic, Digital Contolle Chip Set Fo Iolated DC-DC Powe Supplie, in Poc. IEEE APEC Conf., 2003, Febuay 2003, pp [7] A.V. Petchev, J. Xiao, and S.R. Sande," Achitectue and IC Implementation of a Digital VRM Contolle," IEEE Tanaction on Powe Electonic, Special Iue on Digital Contol, vol. 18, pp , Januay [8] B. Patella, A. Podic, A. Zige, D. Makimoviæ, High-Feuency digital contolle PWM contolle IC fo DC-DC convete, IEEE Tanaction on Powe Electonic, Special Iue on Digital Contol, vol. 18, pp , Januay [9] A.P. Dancy, R. Amithaajah, and A.P. Chandakaan, High- Efficiency Multiple-Output DC-DC Conveion Fo Low-Voltage Sytem, IEEE Tanaction on VLSI Sytem, vol. 8, pp , June [10] Jinwen Xiao; Petechev, A.V.; Jianhui Zhang; Sande, S.R, A 4uA uiecent-cuent dual-mode digitally contolled buck convete IC fo cellula phone application IEEE Jounal of Solid-State Cicuit, Volume 39, Iue 12, Dec pp [11] Lukic, Z.; Kun Wang; Podic, A, High-feuency digital contolle fo dc-dc convete baed on multi-bit Sigma-Delta pule-width modulation in APEC pp Vol. 1 [12] Miibel-Catala, P.L., PuigVidal, M., Samitie Mati, J., Goyhenetche, P., Xuan-Quan Nguyen, An integated digital PFM DC-DC boot convete fo a powe management application:a RGB backlight LED ytem dive in IECON Nov Page():37-42 vol.1 [13] Data Sheet, TPS 62300, 500-mA, 3-MHz Step-Down Convete, Texa Intument Inc. [14] Data Sheet, MAX 85600, 4 MHz, 500 ma, Step-Down Dc Dc Convete, Maxim. [15] A. Syed, E. Ahmed, D. Makimovic, and E. Alacon, Digital Pule Width Modulato Achitectue, in Poc. IEEE PESC 04 Conf., 2004, pp [16] N. Rahman, K. Wang, A. Paayandeh, and A. Podic, Multimode Digital SMPS Contolle IC fo Low-Powe Management, in Poc. IEEE ISCAS 06, in pe [17] N. Rahman, Smat Digital Contolle IC fo ulta low-powe Switched Mode Powe Supplie,, M.S. thei, Univ. of Toonto, Toonto, ON, Mach 2006