Amplitude and Phase Stability of Analog Components for the LLRF System of the PEFP Accelerator

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1 Journal of the Korean Physical Society, Vol. 52, No. 3, March 2008, pp Amplitude and Phase Stability of Analog Components for the LLRF System of the PEFP Accelerator Kyung-Tae Seol, Hyeok-Jung Kwon, Han-Sung Kim, Dae-Il Kim and Yong-Sub Cho Proton Engineering Frontier Project, Korea Atomic Energy Research Institute, Daejeon (Received 21 September 2007) The Proton Engineering Frontier Project (PEFP) low-level radio frequency (LLRF) system for the 3-MeV radio frequency quadrupole accelerator (RFQ) and the 20-MeV drift tube linear accelerator (DTL) has been developed. A stability of 1 % in the amplitude and 1 degree in the phase is required. Therefore, the drift of the analog components should be low enough to satisfy these requirements. An analog chassis, as a prototype of the LLRF system, was congured and tested. RF components, including an IQ modulator, an RF switch, a mixer, RF splitters, RF lters, a circuit for measuring tank phase and a trip circuit for high voltage standing wave ratio (VSWR), have been installed in this chassis. The analog chassis performs an error compensation of the RF amplitude and phase from the IQ signal, a down-conversion to the 10 MHz IF signal, an interlock for the arc and the high VSWR and a distribution for the RF and the clock signals. The amplitude and the phase stability of each component were measured to check the eect on the whole system's performance. In the test with dummy cavities, a uctuation of 5 degrees was measured in the 340 MHz LO signal, but the relative phase between the two cavities was maintained within 0.2 degrees because of the eect being the same for the LO signals of the two cavities. PACS numbers: W Keywords: LLRF, Analog component, Phase, Stability, PEFP I. INTRODUCTION generators has an eect on the performance of the whole system. The 20-MeV proton linear accelerator for the Proton Engineering Frontier Project (PEFP) has been operated [1{3]. The RF source drives the radio frequency II. ANALOG COMPONENTS quadrupole accelerator (RFQ) and the drift tube linear accelerator (DTL) at a frequency of 350 MHz [4,5]. A The overall block diagram of the LLRF system for the low-level radio frequency (LLRF) system for operating 20-MeV accelerator is shown in Figure 1. As shown in the accelerator, which consists of the analog components Figure 1, a pulse delay generator (model 565, BNC) is and commercial digital control boards using a eld programmable gate array (FPGA) and PowerPC embedded generated in the rubidium oscillator (FS725, SRS) is used used for generating the trigger signal. A 10 MHz signal processor, has been developed and tested [6]. The LLRF as a reference clock and an RF signal of 350 MHz and an system provides eld control, resonance control and interlock for high power radio frequency (HPRF) system mercial signal generators synchronized with a 10 MHz LO signal of 340 MHz are generated by using two com- protection. In our system, an accelerating eld stability reference. RF components including an IQ modulator, of 1 % in amplitude and 1 degree in phase is required an RF switch, a mixer, phase comparators, RF lters, for the RF system [7{9]. The analog components generate and distribute an RF signal of 350 MHz, a LO sig- installed in the rack chassis as shown in Figure 2. power splitters and the circuits for the VSWR trip, were nal of 340 MHz and an IF signal of 10 MHz, which are This analog chassis performs an error compensation for synchronized with a 10 MHz reference. Thus, the drift the RF amplitude and phase due to the IQ signal from of the analog components should be low enough to satisfy these requirements. For the initial test of the LLRF signal, the interlock for the HPRF system protection, the the FPGA board, the down-conversion to the 10 MHz IF system, two commercial signal generators were used for RF and clock distribution and the phase measurement. generating an RF signal of 350 MHz and a LO signal The shift of the RF amplitude and phase was tested of 340 MHz respectively, so the stability of these signal by adjusting the IQ input signal of the IQ modulator (AD8345, Analog Devices, Inc.), as shown in Figure 3. ktseol@kaeri.re.kr; Fax: The input and the output frequency of the IQ modula

2 Amplitude and Phase Stability of Analog Components { Kyung-Tae Seol et al Fig. 1. Overall block diagram of the LLRF system for the 20-MeV accelerator. Fig. 2. Analog chassis conguration of the RF components for operating the 20-MeV accelerator. tor is 350 MHz and the IQ input signal is within DC 1 V. As shown in Figure 3, the adjustable phase range is 360 degrees and the adjustable S21 parameter in amplitude is about 2 with an input IQ signal of DC 1 V. In the feedback control, these results are used for error compensation of the RF amplitude and phase. An RF switch (ZASWA-2-500R, Mini-circuits) is used for the interlock for HPRF system protection. As shown in Figure 4, the switching time and isolation in the RF o status were tested with a security box manufactured by Thales Electron Devices, Inc. (TED). In the interlock test, the switching time of the RF switch is within 10 ns and the response time of the security box is about 2 us. It is possible to cut o the RF signal within about 3 us Fig. 3. RF amplitude and RF phase measured in the IQ modulator. (a) Phase range measured by adjusting the IQ signal of the IQ modulator. (b) Amplitude range measured by adjusting the IQ signal of the IQ modulator.

3 -768- Journal of the Korean Physical Society, Vol. 52, No. 3, March 2008 Fig. 4. Waveform measured in the interlock test. The blue trace and the green trace correspond to the TTL in the interlock event and the RF signal, respectively (left time axis: 200 ns/div, right time axis: 10 ns/div). high VSWR. The circuit for the VSWR trip consists of a divider IC and a switch for the pulse operation. A 350 MHz cavity RF signal is down-converted to a 10 MHz IF signal in the analog chassis and is transmitted to the FPGA board. A variable attenuator is used for matching the signal level between the down-converted 10 MHz IF signal and the ADC input of the digital control board. The 350 MHz output signal of the analog chassis is transmitted to a drive amplier to operate the klystron. A 350 MHz band pass lter (BPF) is used to eliminate the harmonic and spurious signals of the IQ modulator, as shown in Figure 5. As shown in Figure 5, the harmonic response for the operating frequency of 350 MHz shows 428 db@700 MHz and 412 db@1050 MHz without the BPF, but the harmonic and spurious signal is eliminated by using the BPF. This analog chassis includes an analog circuit for measuring the relative phase between DTL tanks, which consists of phase comparators, manual phase shifters and a divider IC. III. PHASE MEASUREMENT Fig. 5. (a) Frequency response in the output of the analog chassis without the 350 MHz BPF. (b) Frequency response in the output of the analog chassis with the 350 MHz BPF. in the case of an interlock event. The isolation is below {80 db in the RF o status. In the operation of the 20- MeV accelerator, the interlock signal is a circulator arc, a RF window arc, a klystron output window arc and a As shown in Figure 6, the cavity phase can be measured by using both the analog phase comparator and the digital feedback board in the feedback control. The digital board measures and controls the 10 MHz IF signal converted from the 350 MHz cavity signal and the 340 MHz LO signal by using the 10 MHz reference and the 40 MHz clock. In the feedback control test with a dummy cavity, the phase measured by using the analog phase comparator is not accordance with the phase measured by using the digital board in the open loop and the closed loop, as shown in Figure 7. This means that there is a possibility for an unstable 40 MHz clock or a 340 MHz LO signal. The phase stability of the commercial RF signal gen-

4 Amplitude and Phase Stability of Analog Components { Kyung-Tae Seol et al Fig. 6. Block diagram for measuring the cavity phase. Fig. 8. Phase stability for two commercial signal generators. 4438C is for the RF signal and 8648D is for the LO signal. Table 1. Phase stability statistics for the RF and the LO signal generators. Fig. 7. (a) Phase measured in the open loop with both the analog phase comparator and the digital board. (b) Phase measured in the closed loop with both the analog phase comparator and the digital board. erators (one is 4438C for 350 MHz RF and the other is 8648D for 340 MHz LO, both from Agilent Technologies) is measured and the measured result is shown in Figure 8. The phase is stable enough for the 4438C RF signal generator, but the 8648D RF signal generator shows a ripple of about 5 degrees. The phase stability statis- 4438C 8648D Average phase [degree] Standard deviation Maximum phase [degree] Minimum phase [degree] {1.463 {4.887 tics for two signal generators are summarized in Table 1. This means that the 8648D signal generator is sensitive to a temperature change in the control room. This ripple of the 340 MHz LO signal causes a uctuation in the 10 MHz IF signal and this brings the digital feedback control board to control of an incorrect cavity phase, although the cavity phase is not shifted in the feedback control. Although the cavity phase is not changed in the open loop, the cavity phase measured by using the

5 -770- Journal of the Korean Physical Society, Vol. 52, No. 3, March 2008 IV. CONCLUSION Fig. 9. Relative phase measured between two cavities. Table 2. Stability statistics for the relative phase. Analog Digital Average phase [degree] Standard deviation Maximum phase [degree] Minimum phase [degree] {0.245 {0.095 digital board is shifted due to the unstable 340 MHz LO signal, as shown in Figure 8. In the closed loop, although the cavity phase is not shifted, the incorrect cavity phase is controlled by the digital board. This is caused by a phase shift of the 10 MHz IF signal due to the unstable 340 MHz LO signal. In the feedback control for the PEFP 20-MeV accelerator, it is important that the relative phase between the RFQ cavity and the DTL tanks be maintained. In our case, the LO signal of 340 MHz is unstable, but the LO signal lines are very short and the unstable LO signal has an equal eect on the RFQ cavity and DTL tanks. Thus, the relative phase between the two cavities will be maintained. To check the relative phase, we used a cavity pickup signal for a reference signal in the analog phase comparators and we measured the relative phase between the two cavities by using analog phase comparators and a digital board simultaneously. In this relative phase measurement, the analog phase comparators measure the relative phase of the 350 MHz pickup signal and the digital feedback control board measures the relative phase of the 10 MHz IF signal aected by the 340 MHz LO signal. As shown in Figure 9, both the measured relative phase signals are maintained, which means that the eect of the unstable LO signal disappears. The stability statistics for the relative phase measured with an analog phase comparator and a digital board are summarized in Table 2. From the results, we nd that relative phase between the two cavities is maintained within 0.2 degrees because of the same eect of the LO signal. The analog components for the PEFP LLRF system were congured and tests for the performance of the whole system were conducted. The adjustable amplitude range and phase range for error compensation of the RF amplitude and phase were measured and an interlock test for protecting the HPRF system was performed. In the test with dummy cavities, we found that the relative phase between two cavities was maintained within 0.2 degrees under the same inuence of the LO signal, although the LO signal of 340 MHz had a uctuation of 5 degrees. From these results, we nd that the relative phase between the RFQ cavity and the DTL tanks is maintained for the operation of the 20-MeV accelerator because the LO signal lines are short and the line lengths are equal. For the signal and the clock distribution of the 100-MeV linear accelerator, the RF and the LO signal lines will be installed with equal lengths to maintain the relative phase between the adjacent cavities. These analog components are currently operating with digital control boards for the RF and the beam test of the 20-MeV accelerator and will be upgraded for the operation of the 100-MeV linear accelerator. ACKNOWLEDGMENTS This work was supported by the 21st Century Frontier R & D Program of the Ministry of Science and Technology, the Republic of Korea. REFERENCES [1] Y.-S. Cho, H.-M. Choi, S.-H. Han, I.-S. Hong, J.-H. Jang, H.-S. Kim, K.-Y. Kim, Y.-H. Kim, H.-J. Kwon, K.-T. Seol and Y.-G. Song, Proceedings of EPAC 2006 (Edinburgh, 2006), p [2] B. H. Choi, Proceedings of PAC 2005 (Knoxville, 2005), p [3] H.-J. Kwon, H.-S. Kim, J.-H. Jang and Y.-S. Cho, J. Korean Phys. Soc. 50, 1450 (2007). [4] Y. Y. Lee, Nucl. Eng. Tech. 37, 433 (2005). [5] M. Baba, Nucl. Eng. Tech. 38, 319 (2006). [6] H.-S. Kim, H.-J. Kwon, K.-T. Seol, I.-S. Hong, Y.-G. Song and Y.-S. Cho, J. Korean Phys. Soc. 50, 1431 (2007). [7] H.-S. Kim, H.-J. Kwon, Y.-S. Cho and Y.-S. Hwang, J. Korean Phys. Soc. 48, 732 (2006). [8] H.-J. Kwon, H.-S. Kim, K.-T. Seol and Y.-S. Cho, J. Korean Phys. Soc. 48, 726 (2006). [9] H.-S. Kim, H.-J. Kwon, K.-T. Seol and Y.-S. Cho, Proceedings of EPAC 2006 (Edinburgh, 2006), p