LOI progress report INTRODUCTION

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1 LOI-5 LOI progress report Summary of Experiments from August 4th through 22nd, 2008 November 10, 2008 INTRODUCTION Waveform distortions of the LOI system were investigated using a liquid resistor in place of the ferrite-loaded RF cavity (fig. 1). The liquid resistor (LR) can be modelled simply by a known shunt resistance with some stray capacitance across it, while the ferrite cavity shows more complicated structure. The new configuration also enabled high-power measurements of output impedance by changing the LR resistance. As for waveform distortions [1], we first suspected the coupling of the triode feedback coil and the triode anode choke, because these coils are placed closely in parallel. The feedback coil was then re-arranged at a right angle to the anode choke. However, the waveforms were almost the same as in the parallel arrangement. In the meantime, high frequency oscillations (50~65MHz) were also observed in the driver and the output stages. Measures such as a swamping resistor at the triode grid input, and increase of the grid bias resistance of the tetrode were tried. There were, however, no significant improvements or changes. The voltage gain, which is defined by the ratio of the LR voltage to the triode grid-input voltage, was measured for a right-angle arrangement. The result shows quite different features from the previous ones [2]. Output impedance was measured for five resistance values of LR between 4.8~1.17Kohms. Further measurements toward the lower values will be performed when more copper sulfate becomes available. In the following sections are reported, experimental setup in section 1, LR impedance measurements in section 2, RF waveforms under various conditions in section 3, voltage gain in a final stage in section 4, output impedance in section 5, faults and remedies in section 6, and discussions and conclusions in section 7. Table of the actual stage of this experiment is attached in the appendix. Figure 1: Liquid resistor in place of the ferrite-loaded RF cavity, which is seen at the left-hand side. 1

2 1. Experimental setup The LOI high power drive system (LOI HPD) is shown in Fig. 2, where the LR was installed in place of the ferrite cavity in this experiment. In order to keep the temperature rise of the LR as low as possible, the RF ON-period was limited by short grid-switching pulses of 1msec duration. These pulses are generated in the LOI timing system in Fig. 3, and are fed to the triode grid switcher and the tetrode G1 supply. The pulses are delayed from the Bend-field minimum by 0 ~ 8.8msec to scan a whole frequency range (Fig. 4). The plate voltages and grid bias voltages were the same as in ref. [1], while the current threshold of the Buck Regulator (BR) output was set to 30A-peak: potentiometer dial is 6.0 [3]. Fig. 5 shows the BR output voltage and current, and the tetrode output current in a switched mode. The experimental conditions were summarized in Table 1. Table 1 Experimental conditions load liquid resistor (solution of CuSO 4 ) repetition rate 50Hz class of operation grid switching class A for final triode and driver tetrode ON: 1msec duration at any delay time from the ISIS 50Hz clock OFF: other period than above duty factor 5% RF frequency 2.6 MHz (t = 0msec)~ 6.2 MHz (t = 10msec) ISIS Bend Field (50Hz) arbitrary units ISIS 50Hz delay 1 msec grid-switching pulse ISIS 50Hz sec Figure 4: Timing of grid-switching pulse for RF generation. Delay time is adjusted by the CP8865 digital delay module in fig. 3. Figure 5: Signals in a switching mode: from top, BR voltage (2kV/V), BR current (35A/V), and tetrode supply current (10A/10mV). 2

3 Figure 2: LOI HPD with Liquid Resistor STEP START COMMON EARTH PLATE August 23, 2008 YI DRIVER G1-300V,10A switching output DRIVER G2 1.4KV,10A DRIVER ANODE 5KV,40A CROWBAR BUCK REGULATOR 16KV, 25A T/R SET 13µ A 50mV 50A RF AMP 6x5M 10K V 5000p 3KV 5000p 3KV 4x4000p 15KV 2x1500p 20KV 300W Solid State Amp. 55dB Amplitude modulation RF-law 69p APN input voltage.54µ 1023p.54 µ 1K dB atten. (50ohm) (40x into 50ohms) 3.2µ 53µ 50 5A BURLE K 116µ 4V 1,650A HEATER TRANSFORMER 12n 1.3A 150n 1K 10 12n 12µ 220p EEV BW1643J2 38n 110 GRID -650V switching 5A output 9A 0.4µ 118µ 14V 555A HEATER TRANSFORMER 96n 55.4 µ 1.5K 0.2µ 0.4µ A grid voltage (120 x) 50mV 30A Pearson 310 Output CT (0.1v/2amps into 50ohms) Analog output (25mV/div into 50ohms) LR voltage P6015 (1000 x) 3 APN LIQUID RESISTOR (LR) Tektronics 465B CuSO4 solution

4 ISIS 50Hz (crate 48) Buffer Fanout TTL Buffer Fanout TTL for any trigger for any trigger CP8865 Digital Delay TTL Level Adapter NIM Fan IN/OUT NIM Dual Gate Generator delay, width ISIS 2nd Har HPRF System 4 Diag.->Hall 2, Channel 8 Carrier AM IN Amplitude Modulator Level Adapter TTL HP8012B Pulse Generator delay rise-, fall-time width amplitude 50Hz, 100Hz compensation 300W Solid-state Amp. Trigger Triode Grid Switcher BIAS -200V. INPUT A Tetrode G1 Supply INPUT B Figure 3: LOI timing system for grid switching and triggers 9/2/2008, YI

5 2. LR impedance measurements The resistive part of the LR was measured by two methods: one is to use the bridge impedance meter at 10kHz, and the other a resistive divider method at 1kHz. The latter method assumes the stray capacitance across the LR is negligible at 1KHz. Results agree well with each other as shown in Table 2 and Fig.6. However, the stray capacitance and the capacitance between the LOI chassis and the coupling bar of the LR and triode are important for experiments in the RF frequency range. These capacitances were measured by the Hewlett-Packard HP4195A network/impedance analyser, resulting in 9.5pF and 39.7pF, respectively. The impedance seen looking into the LR at the location of Pearson CT was also measured by the voltage and current monitors of the LR. With the solution conductance 4,437uS, the measurement shows 860ohms at 2.73MHz, while the calculation is 812±30ohms. The calculation error comes from the uncertainty of the LR resistance. The LR impedances by the two methods agree within 10% error. Table 2 LR resistance measurements conductance of LR [kω] Dummy LR*[kΩ] CuSO 4 solution [µs] divider method divider method bridge method , ~4.14 1, , ~1.54 3, , *) Dummy LR is located just outside the LOI area, which has the same structure with LR and is connected in series for the CuSO 4 flow. 6 5 resistance [Kohms] conductance [us] Figure 6: LR resistance measured by two methods. Square(divider method for dummy LR), triangle(bridge method for dummy LR) and red circle(divider method for LR). 5

6 delay = 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 6 msce 7 msec 8 msec 8.8 msec 0.2 msec/div delay = 0msec, 2.69MHz delay = 1msec, 2.94MHz delay = 2msec, 3.42MHz delay = 3msec, 4.03MHz delay = 4msec, 4.72MHz 0.2 usec/div 0.2 usec/div 0.2 usec/div 0.2 usec/div 0.1 usec/div delay = 5msec, 5.38MHz delay = 6msec, 5.43MHz delay = 7msec, 5.75MHz delay = 8msec, 6.10MHz delay = 8.8msec, 6.10MHz 0.1 usec/div 0.1 usec/div 0.1 usec/div 0.1 usec/div 0.1 usec/div Figure 7: RF envelopes and waveforms with LR resistance of 4.8kohms (August 18, 2008). Waveforms are taken at the beginning of each 1msec-duration. From top to bottom line in each screen, LR voltage (10kV/div), LR input current (10A/div), grid input voltage (240V/div) and grid input current (20A/div). APN 50ohm-output was kept 2volts-peak.

7 delay = 0 msec 1 msec 2 msec 3 msec 4 msec 5 msec 6 msce 7 msec 8 msec 8.8 msec 0.2 msec/div delay = 0msec, 2.72MHz delay = 1msec, 2.97MHz delay = 2msec, 3.44MHz delay = 3msec, 4.13MHz delay = 4msec, 4.82MHz 0.2 usec/div 0.2 usec/div 0.2 usec/div 0.2 usec/div 0.1 usec/div delay = 5msec, 5.20MHz delay = 6msec, 5.64MHz delay = 7msec, 5.86MHz delay = 8msec, 5.89MHz delay = 8.8msec, 6.13MHz 0.1 usec/div 0.1 usec/div 0.1 usec/div 0.1 usec/div 0.1 usec/div Figure 8: RF envelopes and waveforms with LR resistance of 1.17kohms (August 22, 2008). Waveforms are taken at the beginning of each 1msec-duration. From top to bottom line in each screen, LR voltage (10kV/div), LR input current (10A/div), grid input voltage (240V/div) and grid input current (20A/div). APN 50ohm-output was kept 1.6volts-peak.

8 3. RF waveforms High power experiments were carried out under various conditions to investigate the waveform distortions and the onset of high frequency components (50~65MHz). The conditions were, (1) different arrangements of the feedback coil and the anode choke, (2) installation of the swamping resistor (3.4ohms) at the triode grid input, (3) increase of the grid bias resistance of the tetrode from the present 2Kohms to 1Kohms, and (4) lowering the LR impedance. However, there were no significant changes/improvements in waveforms for cases (1)~(3). Typical RF envelopes and waveforms are shown in Fig.7, where the right-angle arrangement in (1) is applied and the LR resistance is 4.82Kohms. The 50ohm-output of an all-pass-network (APN) of the tetrode looks fine sinusoidal, and is kept as 2volts-peak through the experiments. In the figure, RF envelope indicates some resonance at delay = 2msec (between 3.4 and 4.0MHz). And, a large second-harmonic component appears at 4.72MHz (delay = 4msec), although there is no such component in the grid input voltage. High frequency deformations can clearly be seen in both the grid input and LR voltages at frequencies above 5.4MHz (delay = 5msec). For comparison, waveforms with lower LR resistance of 1.17Kohms are shown in Fig. 8. Slight changes between them are observed. Especially, a second-harmonic component almost disappeared at 4.815MHz (delay = 4msec) for the latter case. The reason(s) of these deformations are not clear yet. However, it may be probable that some parasitic resonances at the driver and/or final stage are excited by even a small amount of high frequency component at the APN input. 4. Voltage gain in a final stage Voltage gain in a final stage is defined by the ratio of the LR voltage to the grid input voltage. The data were sampled from the pictures in Fig. 7 to calculate the gain. The results are shown in Fig. 9 with the TopSpice calculations for the model LOI system [2]. Although they agree relatively well below 3MHz, they differ by a factor of more than 3 at higher frequencies. These discrepancies are, however, very surprising, because in February, 2003, Oki showed a good agreement for the experiments at KEK. His data is attached in the appendix. It is then reasonable to think the LOI parameters have changed since then. More speculations are given in section Triode anode output/grid inp frequency [MHz] Figure 9: Voltage gain of the final triode. Dots are for measurements and solid-line for calculations 8

9 5. Output impedance In the previous output impedance measurements, the HP4195A probe was directly connected to the output end of the final triode[2]. In this report, the voltage gain in section 4 was measured in high power conditions by changing the LR resistance, since the gain has strong dependence upon the output impedance. The LR voltage is 7kV-peak or higher, and the frequency is 2.7MHz. The results are shown in Fig. 10. The TopSpice calculations are also shown for the model LOI system and the cases where 250 and 2,500ohms resistors are artificially added at the output of the final triode. As seen in the figure, measured data are scattered around calculations. Measurements will be continued to a lower resistance value when more copper sulfate becomes available. Gain LOI design: Z0 Measurements Output Impedance: Z0 +250ohms Output Impedance: Z0 + 2Kohms LR resistance, Kohms Figure 10: Voltage gain variation with LR resistance. Measurements are at 2.7MHz for the resistance between 4.82 and 1.17Kohms. TopSpice calculations are also shown for comparison (see in the text). 6. Faults and remedies Faults and incomplete interlocks were found during the experiments. Remedies or temporary measures are summarized below. (1) Grid-switcher parts were found to be broken (August 6): IGBT(1RG4PH20K), trim pot at the emitter of Transistor(Q1) and zenor(d1). > All replaced. (2) No interlock available from the tetrode chiller. >New temperature sensor (60 C) attached to the water pipe flange at the water manifold (August 7). Chiller flow-interlock disabled at TB6(49,50) (August 5). (3) Grid-switcher fan was shorted (August 17). >Disconnected from the AC line. Need to replace with a new one. (4) AC lead of a triode heater supply was blown at the fuse box (August 21). >Should be replaced with a larger-size lead. (5) flow interlock of the LR at the cavity was disabled at the TB7(65,66) (August 21). 9

10 7. Discussions and conclusions In this experiment, reasons of the waveform deformation could not be found. Adversely, gain curve showed quite different features from the previous measurements in We think the reason is that circuit parameters have been changed since the final design and test experiments of the LOI in February, The circuit elements that have been changed are the anode chokes for both tubes. We purchased new anode chokes for use at ISIS, because the former chokes had poor current capacities. These new chokes are now installed in the present LOI HPD. So, it may be possible that the new chokes have brought undesired resonances into the driver and final stages and have produced the waveform distortions and gain change. Especially for the gain, parameter changes of triode such as amplification factor and/or plate resistance will also be another possibility. In the forthcoming LOI experiments, characteristic survey of each anode choke and examination of the triode gain without feedback loop should be performed. Further actions are highly required as soon as possible. Last but not least: as for output impedance measurements, it seems quicker to use low-impedance solid resistors for resistance below a few hundred ohms. (YI) References: [1] LOI status report LOI-2, September 24, [2] T Oki, et al., NIM A 565 (2006) [3] D Horan and M Middendorf, "Buck regulator upgrades", 12th collaboration meeting, January 18, 2008, 10

11 Appendix 1 Voltage gain of the final triode was measured and reported internally in February, 2003 by T Oki. The load was then the KEK PS ferrite-loaded cavity, the shunt impedance of which was assumed to be 2Kohms. The following figure is taken from ref.2. See text in section 4. Figure caption: voltage gain in the swept-frequency mode (box) and in the fixed-frequency mode (triangle). The dashed line shows the analytical calculations [2]. 11

12 under construction Appendix 2 will be completed in November, 2008 completed