Analog Circuit II Laboratory ( EC 409) EC 409 Analog Electronics Lab - II

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1 Analog Circuit II Laboratory ( EC 409) Subject Subject Title L T P Contact Credit Full Code Hours / Unit# Marks EC 409 Analog Electronics Lab - II Course Outcomes:- After successful completion of this course, a student will be - EC EC EC EC EC EC Able to apply the knowledge of opamp to construct an adder, subtractor and comparator circuit. Able to use opamp as Integrator, differentiator and Schmitt Trigger. Able to verify frequency response of RC coupled amplifier. Able to verify the output of Class A Power Amplifier (Transformer less), Class B Complementary Symmetry Amplifier. Able to use IC 555 timer to construct Monostable &Astable Multivibrator circuit. Able to design transistorized Phase shift, Wein-bridge, Hartley, Collpit oscillators List of Experiments: (i) Study of OP AMPs IC 741 functioning, parameters and Specifications. (ii) OP AMP Applications as Adder, Subtractor, Comparator Circuits. iii) Integrator and Differentiator Circuits using IC 741 (iv) Schmitt Trigger Circuits using IC 741. v) IC 741 Oscillator Circuits Phase Shift and Wien Bridge Oscillators. vi) Study of frequency response of RC coupled amplifier. vii) Study of Class A Power Amplifier (Transformer less). viii) Study of Class B Complementary Symmetry Amplifier. ix) IC 555 Timer Mono-stable Circuit. x) IC 555 Timer Astable Operation Circuit. Xi) Study of an RC Coupled amplifier circuit. xii) Study of Transistorized oscillators Phase shift 1

2 OBJECTIVE: - To measure the following parameters of OP-AMP IC Measurement of quiescent supply current of OP-AMP. 02 To null the offset voltage of an OP-AMP. 03 To measure open loop voltage gain under closed loop condition. 04 To measure output resistance. 05 To measure differential input resistance. 06 To measure unity gain bandwidth. 07 To measure the rated output. 08 To measure the slewing rate. 09 To measure the full power response. 10 To measure the input offset voltage. 11 To measure the input bias currents and offset current. 12 To measure the common mode rejection ratio (CMRR). 13 To measure the common mode input resistance. Apparatus required 01 Decade Audio Frequency Generator. 02 AC milli-voltmeter. 03 Cathode Ray Oscilloscope. Objective 01:-Measurement of quiescent supply current of op-amp Procedure: 01 Apply ± 12V supply to the OP-AMP IC 741 using patch cords and connect DC current meter in series with the supply as shown in Fig IC741 5 DPM 20mA Fig-01 Measurement of quiescent supply current of ic Note down the current indicated by the meter this will be around 1mA. This is the quiescent supply current and flows due to biasing of internal circuitry of the I.C V -12V 2

3 Objective 02:- To null the offset voltage of an op-amp Procedure: 01 Using patch cords assemble the circuit of Fig. 2. 1K 1K K IC K Fig-02 Method of offset nulling of op-amp ic Now monitor the output voltage at pin 6 with no input applied, the output voltage should be zero. 03 If the output voltage is not zero then adjust the 10K potentiometer for making the output as zero volt. The offset nulling is now done and the OP-AMP has no offset now. +12V V OUTPUT + DPM 20V Objective 03:- To measure open loop voltage gain under closed loop conditions. Procedure 01 Using patch cords assemble the circuit of Fig. 3. Keep the output of Audio Frequency around 30mV. Switch ON the supply to the training board. 47K Vj 47K 10Hz 470 Vs PF 0-20V SINE WAVE 1K DPM 20V 100K +12V IC V Vo Fig-03 Measurement of open loop gain under closed loop conditions 02 Measure Vi and Vo. If it is difficult to measure Vi, then measure Vj as indicated in Fig. 3 in this case Vj 100 Vi. 03 Now calculate the open loop gain of OP-AMP Objective 04:- To measure output resistance. Procedure: A O V V 01 Using patch cords assemble the circuit of Fig. 4. Keep the output of A.F. Generator around 30mV at 10Hz. Switch ON the supply to the training board. i O 3

4 47K Vj 100K 10Hz Vs SINE WAVE 1K DPM 20V 100K +12V IC V Vo RL 100E Fig-04 Measurement of output resistance 02 Measure Vo' and Vi'. 03 Calculate Where Ao is the open loop gain. A O Vo' ' V ' Thus output resis tance R i O (AO 1) R A ' O L Objective 05:- To measure differential input resistance. Procedure: 01 Using patch cords assemble the circuit of Fig. 5. Keep SW1 and SW2 both in ON position. Switch on the supply to the training Board. 47K Vj 47K Vs 100K 10Hz SINE WAVE 1K SW1 0.01uF 10K(RG) DPM 20V 10K(RG) 0.01uF 100K +12V IC V Vo Fig. 5 Measurement of differential input resistance 02 Set frequency to 10 Hz and adjust its output level to get voltage Vj = 50mV. Measure output voltage Vo Vj 50 Vi 0.5mV Calculate A O V V 03 Now keep SW1 and SW2 both in OFF position. Measure Vj' and Vo' SW2 O i 4

5 Again V i' Calculate A Rin A AO' 3 04 CalculateRin x10 x10 ohm A A O O' O A O' A Vj 100 Objective 06:- To measure unity gain bandwidth. Procedure: 01 Using patch cords assemble the circuit of Fig. 6 O' G' 10K 10K V V O' i' x 2RG Vs V 7 6 IC Vo Fig. 6-12V Measurement of unity gain band width 02 Switch ON the supply. Keep the output of signal source nearly 200mV, monitor the output of OP-AMP Vo on CRO. 03 Increase the frequency of Vs starting from 10Hz till Vo = Vin. Note down the frequency at which this happens. This is the unity gain bandwidth. Objective 07:- To measure the rated output. Procedure: 01 Using patch cords assemble the circuit of Fig. 7. 1K 10K Vs V 7 6 IC V Vo RL 10K Fig-7 Measurement of rated output 02 Switch on the supply to the training board. Set frequency to 1 KHz. 03 Monitor the output Vo on CRO and go an increasing the level of applied input signal VS 5

6 Objective 08:- To measure the slewing rate. Procedure: 01 Using patch cords assemble the circuit of Fig. 8. Set frequency 10 KHz. Vs 2 3 IC V V 10KHz SINE WAVE 6 Vo 100E Vo t SLEWRATE Vo sr = t Fig-8 Measurement of slewing rate 02 Monitor the output Vo on CRO and increase the level of input signal Vs till the peaks of output begin to flatten out. 03 Calculate Slewing rate S Objective 09:-To measure the full power response. Procedure: 01 Using patch cords assemble the circuit of Fig. 9. 1K r Vo volts / micro sec onds. t 10K Vs 10KHz SINE WAVE V 7 6 IC V 100E Vo Fig-9 Measurement of full power response 02 Switch on the supply to training board. Set frequency to 10 KHz 03 Monitor output Vo on CRO and go on increasing level of the input signal Vs till the output waveform begins to distort. This O/P level is the full power response at 10 KHz frequency. Objective 10:-To measure the input offset voltage. Procedure: 01 Using patch cords assemble the circuit of Fig

7 100E 100K DPM 20V V 7 6 IC Vo -12V Fig-10 Measurement of input offset voltage 02 Switch on the supply to the training board. Measure the input offset voltage Vos using A.C. millivoltmeter. NOTE: The offset voltage is dependent on temperature and supply voltage and also drifts with time. Objective 11:-To measure the input bias currents and offset current. Procedure: 01 Using patch cords assemble the circuit of Fig. 11. SW1 SW2 0.01uF 0.01uF 10K (RG) K (RG) + IC V V 6 Vo 02 Switch on the supply Fig-11 Measurement of input bias currents and offset current 03 Keep switch SW1 OFF and SW2 ON and measure Vo. calculate I B1 Vo R G 04 Keep switch SW2 OFF and SW1 ON and measure Vo. I B2 Vo R G 05 Now keep switches SW1 and SW2 both off and again measure Vo NOTE Vo Ios R 01 Where I B1 G & I B2 are input bias current and los is input offset current. 02 The voltmeter may have to be connected to suit the polarity of Vo voltage in each step. 7

8 Objective 12:-To measure the common mode rejection ratio (CMRR). Procedure: 01 Using patch cords assemble the circuit of Fig. 12. R2 100K Vs R1 100E R1' 100E 10Hz SINE WAVE R2' 100K IC V V 6 Vo Fig-12 Measurement of CMRR 02 Switch on the supply to the circuit. 03 Apply an input signal Vs at 10 Hz and measure Vs and Vo. 04 Calculate common mode rejection ratio as: R1 R2 Vs CMMR x(where R2 R1 Vo R) Objective 13:-To measure the common input resistance. Procedure: 01 Using patch cords assemble the circuit of Fig Hz SINE WAVE Vs SW1 1M (RG) 0.01uF V 7 6 IC V Vo Fig-13 Measurement of common mode input resistance 02 Switch on the supply to the training board. Keep switch SW1 OFF. 03 Set frequency to 10 Hz at 50 mv. Measure Vo' 04 Calculate common mode input resistance as Vo' Ri(cm)() R Ohms Vo' Vo g 8

9 INVERTING AMPLIFIER Aim: To design and setup an inverting amplifier circuit with OP AMP 741C for a gain of 10, plot the waveforms, observe the phase reversal, measure the gain. Objectives: After completion of this experiment, student will be able to design and setup an inverting amplifier using OP AMP. He/she will be able to design and implement OPAMP inverting amplifier circuit. Equipments/Components: Theory: It is a closed loop mode application of opamp and employs negative feedback. The R f and R i are the feedback and input resistance of the circuit respectively. The input terminals of the opamp draws no current because of the large differential input impedance. The potential difference across the input terminals of an opamp is zero because of the large open loop gain. Due to these two conditions, the inverting terminal is at virtual ground potential. So the current flowing through Ri and Rf are the same. I i = I f That is Vin/R i = - Vo /R f Therefore V o /V in = A v = - R f / R i, Here the Ve sign indicates that the output will be an amplified wave with phase shift (inverted output). By varying the R f or R i, the gain of the amplifier can be varied to any desired value. Procedure 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Give 1 Vpp / 1 KHz sine wave as input. 5. Observe input and output on the two channels of the oscilloscope simultaneously. 6. Note down and draw the input and output waveforms on the graph. 7. Verify the input and output waveforms are out of phase. 8. Verify the obtained gain is same as designed value of gain. 9

10 Circuit Diagram: Design: Gain of an inverting amplifier Av = V o /V in = - R f / R i The required gain = 10, That is Av = - Rf/ Ri = 10 Let Ri = 1KΩ, Rf Then = 10KΩ Observations: For DC signal ( at least for 5 different values of Rf) R f Theoretical A v V out Experimental A v % Deviation For AC signal ( at least for 5 different values of Rf) R f Theoretical A v V out Experimental A v % Deviation Graph: Conclusion: 10

11 NON- INVERTING AMPLIFIER Aim: To design and setup a non-inverting amplifier circuit with OPAMP IC 741C for a gain of 11, plot the waveform, observe the phase reversal, measure the gain. Objectives: After completion of this experiment, student will be able to design and setup a non-inverting amplifier using OP AMP. He/she will acquire skill to design and implement OPAMP non-inverting amplifier circuit. Equipments/Components: Theory: It is a linear closed loop mode application of op-amp and employs negative feedback. The R f and R i are the feedback and input resistance of the circuit respectively. There will be no phase difference between the output and input. Hence it is called noninverting amplifier. Av = V o / V in = 1+ R f / R i, Here the +Ve sign indicates that the output will be an amplified wave in phase with the input. By varying the R f or R i, the gain of the amplifier can be varied to any desired value. Procedure 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Give 1 Vpp / 1 KHz sine wave as input. 5. Observe input and output on the two channels of the CRO simultaneously. 6. Note down and draw the input and output waveforms on the graph. 7. Verify the input and output waveforms are in phase. 8. Verify the obtained gain is same as designed value. Circuit Diagram Design: 11

12 Gain of an inverting amplifier Av=V o /V in = 1+R f / R i, Let the required gain be 11, Therefore Av= 1+Rf/ Ri= 11 Rf/ Ri = 10 Take Ri= 1KΩ, Then Rf = 10KΩ Observations: For DC signal ( at least for 5 different values of Rf) R f Theoretical A v V out Experimental A v % Deviation For AC signal (at least for 5 different values of Rf) R f Theoretical A v V out Experimental A v % Deviation Graph: Conclusion: SUMMING AMPLIFIER Aim: To design and setup a summing amplifier circuit with OP AMP 741C for a gain of 2 and verify the output. Objectives: After completion of this experiment, student will be able to design and setup a summing amplifier using OP AMP. Equipments/Components: Theory: Op-amp can be used to design a circuit whose output is the sum of several input signals. Such a circuit is called a summing amplifier or an adder. Summing amplifier can be classified as inverting & non-inverting summer depending on the input applied to inverting & non-inverting terminals respectively. Circuit Diagram shows an inverting summing amplifier with 2 inputs. Here the output will be amplified version of the sum of the two input voltages with phase reversal. V o = - ( R f / R i )(V 1 +V 2 ) Procedure 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Give V 1 =V 2 = +1.5V DC with polarity as shown in fig.1. 12

13 5. Make sure that the CRO selector is in the D.C. coupling position. 6. Observe input and output on two channels of the oscilloscope simultaneously. 7. Note down and draw the input and output waveforms on the graph. 8. Verify that the output voltage is -6VDC 9. Repeat the procedure with V 1 =1Vpp / 1 KHz sine wave and V 2 = +1.5Vdc as shown in fig Verify the output. Circuit Diagram Design: The output voltage of an inverting summing amplifier is given by V o = -( R f / R i )(V 1 +V 2 ) Let R i = 1.1KΩ,Then R f = 2.2KΩ Then V o = -2(V 1 +V 2 ) Observations: For DC input I/P Voltage Input Resistance Rf(Feedback Output voltage(v) 13

14 resistance) Observations: For AC input I/P Voltage Input Resistance Rf(Feedback resistance) Output voltage(v) Graph: Conclusion: DIFFERENCE AMPLIFIER Aim: To design and setup a difference amplifier circuit with OPAMP IC 741C for a gain of 2 and verify the output. Objectives: After completion of this experiment, student will be able to design and setup a difference amplifier using OP AMP. Equipments/Components: Theory: A difference amplifier is a circuit that gives the amplified version of the difference of the two inputs, Vo =A(V1-V2), Where V1 and V2 are the inputs and A is the voltage gain. Here input voltage V1 is connected to non-inverting terminal and V2 to the inverting terminal. This is also called as differential amplifier. Output of a differential amplifier can be determined using super position theorem. When V 1 =0, the circuit becomes an inverting amplifier with input V 2 and the resulting output is V 02 = -Rf /Ri (V 2 ). When V 2 =0, the circuit become a non-inverting amplifier with input V 1 and the resulting output is V 01 = Rf/Ri(V 1 ). Therefore the resulting output according to super position theorem is Procedure Vo = V 01 + V 02 = Rf/Ri(V1-V2) 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Give V 1 = +1.5V DC with polarity as shown. 5. Give V 2 = 1Vpp/ 1 KHz sine wave. 6. Make sure that the oscilloscope coupling selector is in the D.C. position. 7. Observe input and output on oscilloscope simultaneously. 8. Note down and draw the input and output waveforms on the graph. 14

15 Circuit Diagram Design: Given the gain = 2 Vo = V 01 + V 02 = Rf/Ri(V1-V2) That is Rf / Ri = 2 Let Ri = 1.1KΩ Then Rf = 2.2KΩ Observations: Theoretical Differential Gain Table 1 Input V out Phase A v V inv V non Table 2 Circuit V out A v Common-mode Gain Differential Gain Experimental CMRR Table 3 Table 4 Graph: Conclusion: 15

16 INTEGRATOR Aim: To design and setup an integrator circuit using OP AMP 741C and plot its pulse response. Objectives: After completion of this experiment, student will be able to design and setup an integrator circuit using OP AMP. Equipments/Components: Theory: It is a closed loop op-amp circuit which performs the mathematical operation of integration. That is the output waveform is the integral of the input voltage and is given by Vo = ( -1/R f C) V in dt. The integrator circuit is constructed from basic inverting amplifier by replacing the feedback resistance R f with capacitor C. This circuit also works as low pass filter. Procedure: 1. Check the components. 2. Setup the circuit on the Trainer/ breadboard and check the connections. 3. Switch on the power supply. 4. Give V i = 2Vpp, 1KHz square wave. 5. Keep the oscilloscope in AC coupling mode. 6. Observe input and output on two channels of the oscilloscope simultaneously. 7. Draw the input and output waveforms on the graph. Circuit Diagram: 16

17 Design: Given f =1 KHz So T = 1/f = 1ms Design equation is T = 2ðR i C Let C = 0.01µF Then R i = 15KΩ Take R f = 10R i = 150KΩ Observation: Input Signal Output Signal 1 volt peak sine wave at 1 /2 f high 1 volt peak sine wave at 1 /10 f high 1 volt peak triangle wave at 1 /2 f high 1 volt peak triangle wave at 1 /10 f high Graph: Conclusion: DIFFERENTIATOR Aim: To design and setup a Differentiator circuit using OP AMP 741C and plot their pulse response. Objectives: After completion of this experiment, student will be able to design and setup a differentiator circuit using OP AMP. Equipments/Components: Theory: It is an opamp circuit which performs the mathematical operation of differentiation. That is the output waveform is the derivative or differentia l of the input voltage. That is Vo= - R f Cd(V in )/dt. The differentiator circuit is constructed from basic inverting amplifier by replacing the input resistance R i with capacitor C. This circuit also works as high pass filter. 17

18 Procedure: 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Keep the oscilloscope in AC coupling mode. 5. Give V i = 2Vpp, 1KHz square wave. 6. Observe input and output on two channels of the oscilloscope simultaneously. 7. Note down and draw the input and output waveforms on the graph. Circuit Diagram: Design: Given f = 1 KHz So T = 1/f = 1ms Design equation is T = 2ðR f C Let C = 0.01µF Then R f = 15KΩ Let Ri = Rf/10 = 1.5KΩ Observation: Input Signal Output Signal 1 volt peak sine wave at 1 /2 f high 1 volt peak sine wave at 1 /10 f high 1 volt peak triangle wave at 1 /2 f high 1 volt peak triangle wave at 1 /10 f high Graph: Conclusion: 18

19 SCHMITT TRIGGER Aim: To design and setup a Schmitt trigger, plot the input output waveforms and measure V UT and V LT. Objectives: After completion of this experiment, student will be able to design and setup a Schmitt trigger circuit using OP AMP. Equipments/Components: Theory: It is a regenerative comparator or it is a comparator with hysteresis. This circuit uses positive feedback and the op-amp is operated in saturation. The output can take two values +Vsat and Vsat. When output = +Vsat, the voltage appearing at the non-inverting terminal is VUT or UTP= +Vsat(R1/R1+R2) called the upper threshold point. Similarly when output= - Vsat, the threshold the voltage appearing at the non-inverting terminal is VUT or UTP= - Vsat(R1/R1+R2)called the lower threshold point. When Vin is greater than UTP, the output will switch from +Vsat to Vsat. Similarly When Vin is less than LTP; the output will switch from -Vsat to +Vsat which is shown in the graph. The difference between UTP-LTP is called hysteresis. Hysteresis avoids false triggering of the circuit by noise. Hysteresis curve is the plot of Vo versus Vin. Schmitt trigger circuit is used to convert any irregular wave into square wave. Procedure: 1. Check the components. 2. Setup the circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Give V i = 10 Vpp / 1KHz sine wave. 5. Observe input and output on two channels of oscilloscope simultaneously. 6. Note down and draw the input and output waveforms on the graph. Circuit Diagram 19

20 Design: UTP = +Vsat( R1/R1+R2) Let UTP = +3V and LTP = -3V, Vsat=+13V UTP, +3 = +13( R1/R1+R2) Let R1 = 1 KΩ Then R2 = 3.3KΩ Observations: UTP =? LTP =? Graph: Conclusion: RC PHASE SHIFT OSCILLATOR USING OP AMP Aim: To Design and setup a RC phase shift oscillator using Op-Amp 741 and (i) Plot the output waveform (ii) Measure the frequency of oscillation Objectives: After completion of this experiment the students are able to design and set up the RC phase shift oscillator for desired frequency. Equipments/Components: Theory: RC phase shift oscillator uses op-amp, in inverting amplifier mode and the circuit generates its own output signal. It consists of an op-amp as an amplifier and 3 RC cascaded network as the feedback circuit. Since the op-amp is used in the inverting mode, any signal that appears at the inverting terminal is shifted by at the output. An additional phase shift required for oscillation is provided by the cascaded RC network. Thus the total phase shift around the circuit is or 0 0. At some specific frequency, the phase shift of the cascaded RC network is exactly and feedback factor is 1/29. If the gain of the amplifier is 29, the total loop gain of the circuit becomes 1. The circuit will oscillate at this specific frequency and is given by Procedure: 1. Check the components. 2. Setup the RC phase shift oscillator circuit on the breadboard and check the connections. 20

21 3. Switch on the power supply. 4. Observe output voltage on oscilloscope. 5. Draw the waveforms on the graph. 6. Measure the frequency of oscillation. Circuit Diagram: Note: Instead of 100KÙ pot, use 47KÙ pot in series with 68KÙ resister for distortion less sine wave Design: Let f = 1 KHz, and C= 0.01µF R = 6.8KΩ Gain = 29 R f /R 1 = 29 If R1 = 3.3KΩ ; Rf = 95.7KΩ Use 100KÙ pot Observations: Theoretical Experimental % Deviation f out V out Graph: Conclusion: 21

22 WIEN BRIDGE OSCILLATOR USING OP AMP Aim: To design and construct a Wien bridge oscillator using Op-Amp 741 and (i) Plot the output waveform (ii) Measure the frequency of oscillation Objectives: After completion of this experiment the students are able to design and set up the Wien oscillator for desired frequency Equipments/Components: Theory: It is the commonly used audio frequency oscillator which employs both positive and negative feedback. The feedback signal is connected in the non-inverting input terminal so that the amplifier is working in non-inverting mode. The Wien bridge circuit is connected between amplifier input terminal and output terminal. The bridge has a series RC network in one arm and a parallel RC network in the adjoining arm. In the remaining two arms of the bridge, resistor R1 and Rf are connected. The phase angle criterion for oscillation is that the total phase shift around the circuit must be zero. This condition occurs when bridge is balanced. At resonance, the frequency of oscillation is exactly the resonance frequency of balanced Wien bridge and is given by f 0 = 1/ (2ðRC). At this frequency, the gain required for sustained oscillation is 3.It is provided by the non-inverting amplifier with Gain = 1+ (Rf/R1) = 3 Procedure: 1. Check the components. 2. Setup the Wien bridge oscillator circuit on the breadboard and check the connections. 3. Switch on the power supply. 4. Observe output voltage on oscilloscope. 5. Draw the waveforms on the graph. 6. Measure the frequency of oscillation. Circuit Diagram: 22

23 Note: Instead of 47KÙ pot, use 10KÙ pot in series with 22KÙ resister for distortion less sine wave Design: Let f = 1KHz, R=1.5KÙ and C= 0.1µF Gain=3 1+ (R f /R 1) =3 If R 1 = 10KÙ,R f = 20KÙ Use 47KÙ pot Observations: Theoretical Experimental % Deviation f out V out Graph: Conclusion: TO DESIGN, FABRICATE AND TEST AN ASTABLE MULTIVIBRATOR. Theory: If the circuit on the panel is connected as shown in Fig. 6 (a) it will trigger itself and free run as an astable multivibrator. The trigger socket (pin-2) is connected to the threshold terminal (pin-6) to ensure oscillations. F Vcc = 10V B' G,F' T,G' T' RA 10K RB 10K CT 0.1uF R RL 1K B Output C 0.01uF R' Fig. astable multivibrator with duty cycle more than 50% ra = 10k, rb = 10k, rl = 1k, ct = 0.1µf 23

24 When Vcc is first applied to the circuit (time t = 0), capacitor C T charges to 2/3 Vcc through RA & RB during time (t1 and then discharges to 1/3 Vcc through R B during time t2. The delay cycle can be controlled by selecting values for RA and RB as the voltage on CT swings between 2/3 Vcc and 1/3 Vcc as in Fig. 7. Therefore the frequency of oscillations depends only on the passive components RA RB and CT, and is independent of Vcc. Fig. 8 shows the actual wave form generated in this mode of operation. The charge time (output high) is given by: Fig. wave forms of pulse position modulator t1 = (RA + RB) CT... (1) and the discharge time (output low) by : t2 = RB CT Thus the total period is given by T = t1 + t2 = (RA + 2 RB) CT... (2) The frequency of oscillations is then: Fig.wave forms of schmitt trigger 1.46 f = 1/T = (RA + 2 RB) CT... (3) and may be easily found by Fig. 9. Output Voltage 0.67MS MS MS 0.2 MS MS MS Fig. Output wave form and capacitor voltage of astable with duty cycle less than 50% 24

25 by : Duty cycle is the Ratio of the ON duration to the total duration of a cycle and is given ON DURATION (RA + RB) CT D = = TOTAL DURATION (RA + 2 RB) CT RA + RB =... (4) RA + 2 RB It can be expressed in percentage also. Design considerations: Suppose we have to design an astable Multivibrator of Duty Cycle Then from eqn. (4) Hence RA = RB From eqn. (1) D = 2/3 with timing t1 = ms and t2 = ms RA + RB 2/3 = RA + 2 RB x 10-3 = (RA + RB) CT x 10-3 = RB CT or RB CT = 10-3 or CT = 10-3 Assume and RA = RB RB CT =.1 F = 10K Hence the calculated values of the components are RB = 10K ohms and CT = 0.1 mf Components can also be chosen from the graph shown in Fig. 4 Circuit connections: For Astable Multivibrator having duty cycle of more than 50% Connect the circuit components using patch cords as shown in Fig.10 25

26 F Vcc = 10V B' G,F' T,G' T' RA 10K RB 10K CT 0.1uF R RL 1K B Output C 0.01uF R' Fig. Astable multivibrator with duty cycle more than 50% Ra = 10k, rb = 10k, rl = 1k, ct = 0.1µf 01 Use IC1 for the purpose. 02 Observe the output between the terminals 3 and ground on C.R.O. The output should be as shown in Fig V Output Voltage 0V V5 MS MS MS MS MS 0V Capacitor Voltage Fig. Output wave form and capacitor voltage of astable multivibrator For Astable Multivibrator Having Duty Cycle of Less than 50%. 01 Connect the circuit components using patch cords as shown in Fig. 12. For this, utilize IC1 on the panel. F Vcc = 10V B' F,G M,G' M',T T' RA 10K RB 10K D2 CT 0.1uF D R RL 1K B Output C 0.01uF R' Fig. Astable multivibrator with duty cycle less than 50% Ra = 10k, rb = 10k, rl = 1k, ct = 0.1µf 26

27 02 Observe the output between the terminals 3 and ground on CRO. It should be as indicated in Fig.13. Output Voltage 0.67MS MS MS 0.2 MS MS MS Fig. Output wave form and capacitor voltage of astable with duty cycle less than 50% For Astable Multivibrator With Duty Cycle Variable From 0 to 100% and Frequency Constant. 01 Connect the circuit components using patch cords as shown in Fig. 14. W,C Rx 47K D,Y R2 2K7 M,D' M',S S' X L' R1 1K L D2 CT 0.047uF D1 Vcc = 10V C' R' R B' RL 1K B Output C 0.01uF Fig. Astable multivibrator with duty cycle variable from 0 to 100% and frequency constant Rx = 47k, r1 = 1k, r2 = 2k7, rl = 1k, ct = 0.047uf 02 Vary the duty cycle from 0 to 100% by potentiometer and observe the O/P on CRO. Observations: Connect the mains lead to the nearest mains socket and keep the power switch to ON position. Jewel light will glow indicating that instrument is ready for use. observe the output wave form between the pin-3 and ground on CRO. Waveform at the output should be as shown in Fig. 11 and 13. Remarks: The duty cycle depends on the values of RA and RB and is equal to : RA + RB D = RA + 2 RB 27

28 It can be set from slightly above 50% to nearly 100%. The maximum duty cycle is the ON time divided by the total time which is approximately 100% - is developed when RA is as small as possible while still sufficiently large to limit the current through the discharge transistor to a level that does not exceed the value specified for the specific device. For duty cycles less than 50%, a diode D1 in Fig. 12 is connected between the discharge and threshold terminals. Capacitor CT now charges only through RA (RB is shorted by diode conduction during the charge cycle) and discharges through RB so the duty cycle is now RA D = (RA + 2 RB) and can be varied from almost 0 to nearly 100% Fig. 9 shows the wave forms as the duty cycle is decreased below 50%. The voltage drop across D1 will prevent the timing cycle from being completely independent of RB. This can be prevented by installing D2 in series with RB as shown. In some applications, it is needed to vary the duty cycle from about 0 to 100% while holding the frequency constant. In this case, replace RA and RB with a single linear post as in Fig. 4 (c). Resistors R1 and R2 approximately 1K ohms each are connected in series with the pot of 47K ohms. R1 limits the maximum current through the discharge transistor. Resistors R2 establishes a minimum value for RB and to compensate for the addition of R1 to the network. TO DESIGN, FABRICATE AND TEST A MONOSTABLE MULTIVIBRATOR. Theory: Circuit diagram of monostable multivibrator using IC 555 is given Fig. 15. To understand the working of monostable multivibrator, refer to the internal block diagram of IC 555. The external capacitor CT is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 Vcc to trigger point (pin-2), the flipflop is set which then release the short circuit across the capacitor and drives the output high. Vcc=10V 330E 3 Fig. Monostable multivibrator r1 = 1k, ra = 2k7, rl = 1k, cd = 6800 pf, ct = 1µf The voltage across the capacitor, now, increases exponentially with the time constant ( t = 1.1 RACT). When the voltage across the capacitor equals 2/3 Vcc, the comparator resets the flipflop, which in turn discharges the capacitor rapidly, and drives the output to its low state. Fig. 16 shows the actual wave forms generated in this mode of operation. 28

29 Fig. Output wave forms The circuit triggers on a negative going input signal when the level reaches 1/3 Vcc. Once triggered, the circuit will remain in this state until the set time is elapsed, even if it is triggered again during this interval. The time that the output is in the high state is given by t = 1.1 RACT and can easily be determined by Fig. 17. Since the charge rate, and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. Applying a negative pulse to the reset terminal (pin 4) during the timing cycle, discharges the external capacitor and causes the cycle to start over again. The timing cycle will now commence on the positive edge of the reset pulse. During the time, the reset pulse is applied, the output is driven to its low states. When the reset function is not in use, it should be connected to Vcc to avoid any possibility of false triggering. 100 Design considerations: Capacitance - uf u Sec. u Sec. M Sec.M Sec.M Sec.Sec. Sec. Time Delay Fig. Time delay vs, ra and ct. Monostable Multivibrator can be triggered by negative going input signal and the output will become high. Duration of high output is governed by the values of RA and CT and given by t = 1.1 RACT Suppose, we have the input signal of 1 KHz, square wave and we want to have the duration of monostable multivibrator as 1.1 m sec. For this if we choose RA = 1K, then 29

30 1.1 X 10-3 CT = = F 1.1 X 103 Hence the calculated values of the components for output high duration of 1.1 m sec. will be : RA = 1K, CT = 1 µf Circuit connections: 01 Connect the circuit components by patch cords on the training board as shown in Fig Apply positive pulses or clock of frequency 1 KHz to N terminal. 03 Observe the output between the points 3 and ground. It will be same as shown in Fig. 16. Note the pulse duration on calibrated CRO. Observations: Connect the mains lead to the nearest mains socket and keep the power switch to ON position. Jewel light will glow indicating that the instrument is ready for use. Observe the output on CRO between the terminals 3 and ground wave forms at the output will be same as shown in Fig. 16. Note the pulse duration on calibrated CRO. Remarks: Pulse duration can be varied by varying either RA or CT Fig. 15 shows the various possible combinations of RA and CT for different time delays. The graph is very important, when monostable multi, is used as a time delay circuit. TO STUDY THE FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER AND CALCULATE ITS BANDWIDTH. Components/ Equipment: Theory: The common emitter configuration is widely used as a basic amplifier as it has both voltage and current amplification. Resistors R1 and R2 form a voltage divider across the base of the transistor. The function of this network is to provide necessary bias condition and ensure that emitter-base junction is operating in the proper region. In order to operate transistor as an amplifier, biasing is done in such a way that the operating point is in the active region. For an amplifier the Q-point is placed so that the load line is bisected. Therefore, in practical design V CE is always set to V CC /2. This will confirm that the Q-point always swings within the active region. This limitation can be explained by maximum signal handling capacity. For the maximum input signal, output is produced without any distortion and clipping. The Bypass Capacitor: The emitter resistor R E is required to obtain the DC quiescent point stability. However the inclusion of R E in the circuit causes a decrease in amplification at higher frequencies. In order to avoid such a condition, it is bypassed by a capacitor so that it acts as a short circuit for AC 30

31 and contributes stability for DC quiescent condition. Hence capacitor is connected in parallel with emitter resistance. The Input/ Output Coupling (or Blocking) Capacitor: An amplifier amplifies the given AC signal. In order to have noiseless transmission of a signal (without DC) ), it is necessary to block DC i.e. the direct current should not enter the amplifier or load. This is usually accomplished by inserting a coupling capacitor between two stages. XC C << ( R i h ie ) C C - Output Coupling Capacitor C B - Input Coupling Capacitor Frequency response of Common Emitter Amplifier: Emitter bypass capacitors are used to short circuit the emitter resistor and thus increases the gain at high frequency. The coupling and bypass capacitors cause the fall of the signal in the low frequency response of the amplifier because their impedance becomes large at low frequencies. The stray capacitances are effectively open circuits. In the mid frequency range large capacitors are effectively short circuits and the stray capacitors are open circuits, so that no capacitance appears in the mid frequency range. Hence the mid band frequency gain is maximum. At the high frequencies, the bypass and coupling capacitors are replaced by short circuits. The stray capacitors and the transistor determine the response. Characteristics of CE Amplifier: 1. Large current gain. 2. Large voltage gain. 3. Large power gain. 4. Current and voltage phase shift of Moderated output resistance. 31

32 Circuit Diagram: Procedure: 1. Connect the circuit as shown in the circuit diagram. 2. Set source voltage V S = 50mV (say) at 1 KHz frequency using the function generator. Observe the phase difference between input and output by giving these two signals to the dual channels of CRO. 3. Keeping input voltage constant, vary the frequency from 50 Hz to 1 MHz in regular steps and note down the corresponding output voltage. Calculate gain in db as shown in the tabular column. 4. Plot the graph: gain (db) verses Frequency on a semi log graph sheet. 5. Calculate the 3-dB bandwidth from the frequency response. Expected waveform: (a) The Input & Output Waveforms at 1 KHz 32

33 (b) Frequency Response Curve In the usual application, mid band frequency range are defined as those frequencies at which the response has fallen to 3dB below the maximum gain ( A max). These are shown as f L and f H and are called as the 3dB frequencies (Lower and Upper Cut-Off Frequencies respectively). The difference between higher cut-off and lower cut-off frequency is referred to as bandwidth (f H - f L ). Fig: Frequency Response Curve Calculations from the graph Bandwidth = f H f L (in Hz) Observation tables: V S = 50mV Frequency Vo(Volts) Gain = Vo/Vs Gain(dB) = 20 log(vo/vs) Result: Common Emitter Amplifier is studied and its Bandwidth is calculated. 1. Maximum Gain ( A max ) = db 2. 3dB Gain = db 3. 3dB Lower cut-off frequency, f L = Hz 33

34 4. 3dB Upper cut-off frequency, f H = Hz 5. 3dB Bandwidth ( f H - f L ) = Hz Outcomes: Students are able to 1. Calculate the Bandwidth of BJT Common Emitter amplifier. RC OSCILLATORS Objective: 1) To study the characteristics of RC Phase shift oscillators. Equipments Components 1- Dual Power supply 2- Oscilloscope 3- Operational amplifier 4- Transistors 5- Components as shown in figures 6- Function generator Theory The oscillator is an amplifier with positive feedback that generates a number of waveforms usually used in instrumentation and test equipments. An oscillator that generates a sinusoidal output is called a harmonic oscillator; the transistor is usually acts in the active region. The output of the relaxation oscillator is not sinusoidal depending on the transient rise and decay of voltage in RC or RL circuits. 1. Phase shift oscillators in which the output of an amplifier must be 180 o out of phase with input. A general circuit diagram of a phase shift oscillator is shown in Fig.(l), where the amplifier is an ideal one. A phase shift network (usually a resistor-capacitor network) is used to produce an additional phase shift of 180 at one particular frequency to develop the required positive feedback. From the mesh network equations of the feedback network, we find the feedback factor β as, 34

35 The phase shift of the feedback network must be 180 then: At this frequency = 1/29 and it is required that (A) must be at least 29 to satisfy oscillation condition as shown in Fig.(2). The phase shift oscillator is used to the range of frequencies for several hertz to several kilohertz and so includes the range of audio frequencies. The frequency depends on the impedance elements in the phase shift network. The phase shift oscillator circuit is not very suitable for generating variable frequency because the resistors and capacitors must be simultaneously changed to obtain the required frequency control over a wide range therefore it is used mostly in fixed frequency applications. Procedure 7. Connect the circuit as shown in Fig.(2), insert potentiometer of l k in the feedback arm. 8. Measure the frequency of oscillation (f o ) and the amplitude of the output voltage. 9. Measure and draw the waveforms of points A, B, C and D. 10. Observe the effect of variation of the potentiometer on the frequency of oscillation. 11. Observe the effect of the variation of R E and R B on f o. 12.Break the feedback network and measure the gain by connecting the signal generator to point d. 7. Connect the circuit as shown in Fig.(3). 8. Measure the frequency and amplitude of oscillation. 9. Change the value of R and C their effect on the frequency and amplitude of oscillation. 35

36 Fig.: RC phase shift oscillator Graph: Conclusion: 36

37 TRANSISTOR POWER AMPLIFIERS OBJECTIVE: To study some important aspects of different power amplifiers configurations. EQUIPMENTS AND COMPONENTS: 1. Signal generator 2. DC Power supply 3. Oscilloscope 4. AVO meter 5. Transistor and components as shown in Fig.(2) and Fig.(4). THEORY: An amplifier designed to deliver electric power to a desired load is known as a power amplifier. Power amplifiers find applications in transmitter, servomotor amplifiers, industrial control circuits, and audio amplifiers. In general, power amplifiers designed to del1iver the maximum power output at the highest efficiency. Since power amplifiers inherently involve excursions in voltage and current, the transistor may operated in the non-linear regions of the characteristic curve resulting distortion in the output. Furthermore, the transistor subjected to large values of current and voltage, thermal instability may become a problem and thus the power amplifier must biased to guard against thermal runaway. Depending on their operation, power amplifiers can be grouped into four main classes: - CLASS A operation - CLASS AB operation - CLASS B operation - CLASS C operation The output signal as result of a sinusoidal input signal for each of the four classes can show in Fig.(1). In class A operation, the entire input signal is reproduced faithfully at the output resulting minimum distortion. The power delivered by the power supply is constant and not affected by input signal. This means that, power being dissipated by the circuit even through no signal is present. Further more, the maximum lower dissipated in the transistor under up signal condition. Therefore the efficiency in class A operation is poor. Fig.(2 ) shows the typical circuit used for class A power amplification. 37

38 In class AB operation output (collector) current flows for more than half of the input signal cycle. Hence, more than half of the signal is amplify and appears at the output. Class A Class AB Class B Class C Fig.(1): Signal waveform for Classes (A, AB, C, D) In class B operation, exactly half of the input signal appears amplified at the output. Transistor is biased such that Ic =0. Therefore the amplifier dissipates power only when it is being used to amplify signal (input signal present). Hence, the efficiency is higher but the distortions are considerable. In order to obtain high efficiency and low distortion, circuit shown in Fig.(3) is used. This is known as PUSH PULL amplifier. In positive half cycle one transistor provides output current while in negative half cycle other transistor provides output current. By this way output current is continuous. Fig.(2) : shows type of coupling In class C operation, somewhat less than half of the input signal appears amplified at the output. The output signal waveform is high distorted and rich in 38

39 harmonic. Generally, in class C amplifier, load is a tuned circuit, which selects the fundamental or the desired harmonic rejecting all other frequency components. Efficiency in class C amplifier is the highest. These generally used to amplify radiofrequency (r.f.) single in transmitters. PROCEDURE: 1. Connect the circuit as shown in Fig.(2a). Adjust V BB to obtain Ic=4.5mA. Then measure VBE and VCE. 2. Draw the load line on the given output characteristics. Locate Q point. 39

40 3. Apply a sinusoidal input signal of 1kHz and adjust the input voltage to obtain maximum undistorted output. Draw input and output waveform accurately. 4. Calculate efficiency and distortions. 5. Adjust V BB equal to the half value set in step 1. Measure Ic, VBE, and VCE. 6. Apply a sinusoidal input signal of magnitude applied in step 3. Draw input and output waveform. Then measure rms output voltage (hence calculates rms and average current). Repeat step Adjust V BB to obtain Ic = 0 (class B operation). Repeat step Adjust V BB = -0.5 volt. Measure VBE, VCE and Ic. 9. Apply a sinusoidal input signal of magnitude apply in step 3. Draw input and output waveform. Then calculate efficiency. 10. Connect the circuit as shown in Fig.(3). Measure the dc current pass through each transistor. 11. Measure the ac and dc current pass through the load. Then calculate efficiency. Graph: Conclusion: 40