Analog Fundamentals of the ECG Signal Chain

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1 Analog Fundamentals of the ECG Signal Chain Prepared by Matthew Hann, Texas Instruments Precision Analog Applications Manager Presented by Jose Duenas, Precision Analog Product Marketing Engineer 1

2 Objectives Introduce Basic ECG Concepts Motivate the Need for TINA and SPICE Simulation for ECG Analysis Introduce Discrete Analog Functions of the ECG Signal Chain Motivate Need for Low Cost Integrated ECG Conditioning System Introduce the ADS1298 and Its Embedded ECG Circuitry and Functions 2

3 Analog Fundamentals of the ECG Signal Chain What is a Biopotential? What is ECG? The Einthoven Triangle Analog Lead Definitions, Derivations, and Purpose Modeling the Electrode Interface Input Filtering and Defibrillation Protection The INA front end AC vs. DC coupling Right Leg Drive (RLD) Amplifier Selection and Design The ECG Shield Drive Lead Off Detection PACE Detection INA post Gain Analog Filtering A/D Conversion Options and Filtering ADS129x Introduction, Features, and Advantages 3

4 What is a Biopotential? 41

5 What is a Biopotential An electric potential measured between living cells 5

6 What is a Biopotential Every cell is like a little battery Cell membrane (lipids) Intracellular medium/ Cytoplasmic fluid Extracellular medium/fluid Ion channels (proteins) Resting ion chs. Active ion pumps Gated ion chs. 6

7 What is a Biopotential Every cell is like a little battery K is 30 to 50x rest Cell membrane (lipids) Electrostatic Force Na conc. is 10x rest Ion channels (proteins) Resting ion chs. Active ion pumps Gated ion chs. Diffusional force 7

8 Cell membrane (lipids) Intracellular medium/ Cytoplasmic fluid What is a Biopotential Every cell is like a little battery Neurotransmitter are received at dendrites Extracellular medium/fluid Ion channels (proteins) Resting ion chs. Active ion pumps Gated ion chs. 8

9 What is a Biopotential Biopotentials from cells electrodes 9

10 What is ECG? 101

11 What is ECG? A measure of the electrical activity of the heart 11

12 What is ECG? ECG and blood pressure waves 12

13 What is ECG? Actual ECGnormal 13

14 What is ECG? ECG irregular tracings due to external artifacts 14

15 What is ECG? Modeling the electrode interface Electrical characteristics include a DYNAMIC resistance, capacitance, and offset voltage 15

16 Analog Lead Derivation 161

17 Analog Lead Derivation ECG Einthoven Triangle, Body Electrodes, 3 Derived Leads = I, II, III LEAD I = V LARL V RARL LEAD II = V LLRL V RARL LEAD III = V LLRL V LARL Einthoven s Law Right Leg Reference, RL In electrocardiogram at any given instant the potential of any wave in Lead II is equal to the sum of the potentials in Lead I and III. 17

18 Analog Lead Derivation The Wilson Central (WCT) Provides Chest Lead Reference at Center of Einthoven Triangle Assuming: R RA = R LA = R LL Then: 3 WCT R RA RA LA R RA LL RA LA WCT 3 LL 18 *Drawing Taken From Bioelectromagnetism, Jaako Malmivuo and Robert Plonsey

19 Analog Lead Derivation The Wilson Central is the AVERAGE potential between RA, LA, and LL R RA R LA V OUT = V (16) V WCT R LL The Wilson Central is used to derive a reference potential for the Chest Leads, V 1 V 6 19

20 Analog Lead Derivation Chest Lead Signals Provide Different Information at Different CrossSectional Angles Different Chest Leads Provide: *Unique ECG Signature *Enhanced Pattern Recognition *Isoelectric V 3 V 4 20

Analog Lead Derivation Augmented Leads Derived via WCT to Provide Enhanced Vector Information Each lead provides unique information about the ECG Output

21 Analog Lead Derivation Augmented Leads Derived via WCT to Provide Enhanced Vector Information Each lead provides unique information about the ECG Output Signal Multiple Angles Give a Better Than 2D Picture of the ECG Output AVR, AVL, AVF derived via midpoint of 2 limbs (resistor divider) with Respect to 3 rd limb 21

Analog Lead Derivation IEC60601251 Diagnostic Standards Electrodes Needed 1

22 Analog Lead Derivation IEC Diagnostic Standards Electrodes Needed 1 Lead LA, RA 3 Lead LA, RA, LL 6 Leads LA, RA, LL 12 Leads LA, RA, LL, V16 22

23 Analog Lead Derivation Different Lead Combinations Reveal Axis Deviation QRS in LEAD I QRS in AVF Left Axis Deviation (LAD) and = Mean QRS Vector Points Toward Area of Infarction (Damage) 23

24 Analog Lead Derivation Different Lead Combinations Reveal Axis Deviation I AVF Extreme RAD LAD I AVF I RAD Normal I AVF AVF 24

25 ECG Input Filtering, Defibrillation Protection, and Isolation 251

26 ECG Input Filtering and Protection Example: LEAD I Protection with Input Filtering Series Resistance Limits Input Current C F, C cm, and C diff R filter form LPF Protection Diodes V s LA R Patient R filter1 R filter2 RA NE2H R Patient R filter1 C F R filter2 C CM C diff V s V s Zener Diode NE2H C F C CM V s Patient Protection 10 20k ohms Ne2H Lamps/TVS Protect Against Defibrillation Voltages C diff = 10 x C cm 26

27 System Block Diagram 271

28 System Block Diagram RA Wilson INA I II MUX dv/dt QRS and PACE Detect LA III avr LL avl avf RL Filter MUX Isolation WCT V 1 INA A/D V 2 DIO V 3 V 4 V 5 V 6 28

29 The INA Front End 291

30 The INA Front End Key Features of the INA Front End *Important* Less Important Input Bias Current Input Impedance Input Current Noise Input Voltage Noise Power Consumption DC/AC CMRR Input Offset Voltage Input Offset Voltage Drift Gain Error Nonlinearity PSRR *DC Errors such as VOS are swamped out by the Offsets Introduced by the SkinElectrode Contacts 30

31 C12 33p C10 33p C20 330p C19 33p C18 33p nv The INA Front End Ideal Simulation Circuit with Current and Voltage Noise Sources ECG Skin Impedance C6 100p Electrode Impedance Offset C7 47n Input CM Differential Filtering Ideal INA Front End R21 1k R19 1k V4 0 R1 63.4k R3 63.4k Vn12 Vnoise ECGp R14 100k R20 1k Vout Vref C8 100p R23 1k C9 47n V5 0 R4 63.4k R5 63.4k INA 1 Vref R25 1k R22 100k R24 1k fa In12 In_fA 31

32 Total noise (V) The INA Front End Simulation Showing OutputReferred Total RMS Noise vs. Bandwidth (G = 110) V CM V dif 2 Rg 1k Vin 50k 50k A1 Va1 150k 150k A3 Vout Noise may NOT necessarily increase linearly with gain (INA or PGA topology dependent) V dif 2 Vin A2 150k Va2 150k T 32.00u 28.00u 24.00u 20.00u 16.00u 12.00u 8.00u 4.00u k Frequency (Hz) 32

33 Voltage (V) The INA Front End TINA Simulations Showing OutputReferred ECG Signal (G = 110) Snapshot of R Wave from ECG Waveform T ECG Signal Varies LINEARLY with Increase in Gain m m m Time (s) 33

34 The INA Front End What is the MAX gain on the INA When Using a DC Removal Circuit? Integrator Removes Gained up DC offsets and servos INA output to V ref (3) V ref (1) (2) (1) Electrode Offset MAX = / 300mV (2) Swing of INA = V() 50mV (3) Integrator Compliance = (ECGp ECGn VOS VOS electrode )* Gain < V CC V ref 34

35 33p 100n 33p 330p 33p 33p 100k The INA Front End Simulation Circuit with Ideal INA and V ref = 2.5V as Integrator Input 1k ECGp 47n 52k 150m 63.4k 63.4k VCVS1 1 Vout Vref Vref ECGn 1k 47n 52k 150m 63.4k 63.4k OPA333 OPA333 Used as Integrator to Remove DC and Simulate Real Response During Saturation 35

36 The INA Front End ECG Integrator Output of INA vs. Gain for V ref = 2.5V 2.50 Vout[G = 1] Vout[G = 3] Vout[G = 6] Vout[G = 8] As the output of the Integrator Saturates from Increased Gain, V out of the INA pulls away from V ref Vout[G=9] Vout[G=10] m 1.50 Time (s) 36

37 The INA Front End If it is Advantageous to Maximize Gain with a Low Noise INA up Front, Why not AC Couple? ECGp V CM ECGp VOS electrode1 V CM ECGn VOS electrode2 (ECGp ECGn)*Gain ECGn *AC Coupling Removes Electrode Offsets so that Higher Gain Can Be Used for Potentially Better SNR in the Signal Chain Path 37

38 C7 33p C8 33p C9 330p C6 33p C5 33p The INA Front End TINA Simulation Circuit to Show ACCoupled INA Gain Sweep C2 47n V3 0 R8 63.4k R9 63.4k Vref R14 10M CCp 1u Vref ECGp ECGn R4 52k C4 47n V4 0 R k R k CCn 1u INA 1 Vref Vout R7 52k Vref R13 10M 38

39 Voltage (V) The INA Front End INA Gain = with V REF = 2.5V AC Coupled m m 1.22 Time (s) 39

40 The INA Front End What is CMRR? Why is it Important in ECG? ECGp V V out V OS Gain CM ECGn Lower CMRR = More Unwanted Output Signal CMRR 20 V CM log 10 V OS 20 V CM Gain V out V out ECGp ECGn VOS electrode VOS OPA 10 V CM CMRR 20 Gain 40

41 The INA Front End What is CMRR? Why is it Important in ECG? R P1 V CM ECG p C C1 Amp The INA includes the R and C and must be considered in the overall CMRR Analysis ECG n C C2 2 2 R p1 R p2 V diff_actual V inp V 2 inn 2 j R 2 j p1 C R p2 c1 C c2 R P2 2 Mismatch in R p and C c causes a differential signal error Even a 1% tolerance on Cc cause a 20dB attenuation in CMRR 41

42 C7 33p C8 33p C9 330p R1 20k C6 33p C5 33p The INA Front End 50/60Hz Common Mode Simulation Circuit with 1µF Coupling Capacitors Mismatched CMR TINA Circuit Test By Sweep of Mismatch of Input Coupling Capacitors C2 47n V3 0 R8 63.4k R9 63.4k Vref R14 10M C1 1u Vref R4 52k RG V Ref Out Vout VCM C4 47n V4 0 R k R k C12 1u RG V U1 INA333_C R7 52k Vref R13 10M 42

43 Voltage (V) The INA Front End Plot of CMRR vs. Frequency for.01.5% Coupling Capacitor Mismatch T % Mismatch % Mismatch m Frequency (Hz) 43

44 Voltage (V) The INA Front End Plot of ECG Response to 5Hz CM Input Signal (0%.5%) CC Mismatch T 2.51 Lower Frequency Signals Couple Directly Into the ECG Signal to the Output m m Time (s) 44

45 The INA Front End Plot of ECG Response to 50/60 Hz CM Input Signal T Vout /60Hz Noise Rejection is Virtually Unaffected by AC Coupling Dependent Primarily on the Noise Magnitude and the CMRR of the Front End INA m m Time (s) 45

46 The Right Leg Drive Amplifier 461

47 The RL Drive Amplifier The RL Drive Amplifier Serves 2 Purposes: (1) Common Mode Bias (2) Noise Cancellation ECG p CM noise CM noise ECG n Average VCM is Inverted and Fed Back to RL; Cancels 50/60Hz noise *Tapping off center of split gain resistor feeds the following voltage to the RL Drive Circuit [(V cm ECG P ) (V cm ECG n )]/ 2 = V cm (ECG p ECG n )/2 47

48 R13 1M R16 1M R14 1M Noise C7 33p C8 33p C9 330p C6 33p C5 33p R12 1M Vref The RL Drive Amplifier Simulation Circuit for Response to 50/60 Hz CM Noise Injection Source NS3 2.5 NS R1 1k C2 47n R15 1M U1 OPA333 R4 1k R8 63.4k R9 63.4k ECGp ECGn C4 47n R k R k RG1 10k RG2 10k RG RG V V C10 1u Ref Out U3 INA333 NS NS2 2.5 Vout Vref R2 1k R7 1k R6 1k R5 1M R3 10k U2 OPA333 Vref U4 OPA333 NS1 2.5 NS = Included for TINA spice Convergence 48

49 T ECGn u The RL Drive Amplifier TINA Simulation with NO RL Drive; CM Noise is Coupled to Output u u ECGp u 1.00 Noise Vout m 1.33 Time (s) 49

50 The RL Drive Amplifier TINA Simulation with RL Drive; Output Noise is Reduced T ECGn u u u ECGp u 1.00 Noise Vout m m m Time (s) 50

51 The RL Drive Amplifier Analyzing the RLD Amplifier Loop V ECGp V ep V CM V ref V outa1 V RL R I R F V ref ECG p V ep R G /2 R A More Gain = Better CMRR Loop Corrects for Electrode Offset, VOS A1, and VOS RLD R F ECG n V en R G /2 R A V REF R I V ECGn V en V CM V cm V ECGn V cm V ECGp V ep V outa1 R G V en R G 2 VOS A1 51

52 R13 100k R14 100k R16 10M R_RLD 52k C_RLD 47n C7 33p C8 33p R17 1M C9 330p C6 33p C5 33p R12 1M Vref Sweep Feedback Resistor Gain to show Effects of 50/60Hz Vcm The RL Drive Amplifier Simulation Circuit for CMRR of RLD Loop V3 0 C2 47n R4 52k V4 0C4 47n R7 52k R8 63.4k R9 63.4k R k R k RG1 25k RG2 25k R15 1M RG RG V V Ref Out C10 1u U3 INA333 U1 OPA333 Vout NS1 2.5 R2 100k RF 10k NS R3 10k U4 OPA333 Vref V1 2.5 V2 2.5 Vref U2 OPA333 52

53 CMRR (db) The RL Drive Amplifier CMRR Plots vs. Gain in RLD Loop T R F = 10k R F = 100k R F = 1M R F = 10M Frequency (Hz) 53

54 C1 1G R14 100k R_RLD 52k C_RLD 47n C7 33p C8 33p R17 1M C9 330p C6 33p C5 33p R12 1M Vref Electrode Resistance Varies With Contact and Moisture, Presents Problems for RLD Stability The RL Drive Amplifier RL Drive Stability Simulation Circuit V3 0 V4 0 C2 47n R4 52k C4 47n R7 52k R8 63.4k R9 63.4k R k R k RG1 25k RG2 25k R15 1M RG RG V V C10 1u Ref Out U3 INA333 U1 OPA333 R2 100k R5 10M L1 1G R3 10k U4 OPA333 Vref V1 2.5 Local RLD Loop is Broken to Ensure Proper Phase Margin Over Range of Electrode Resistance VoA Vref U2 OPA333 Vloop Vin V

55 Gain (db) T The RL Drive Amplifier RL Drive Simulation Showing Instability in the RLD Feedback Loop AOL > 20dB/dec ROC (Rate of Closure) = INSTABILITY /Beta k 10.00k k 1.00M 10.00M Frequency (Hz) 55

56 Gain (db) The RL Drive Amplifier Using RLD Simulation to Compensate for 1/Beta Variation With Electrode Resistance T Intersection of 1/ß and AOL curve > 40dB/dec Feedback Comp Placed vs. Worst Case Electrode Resistance and RLD AOL k 10.00k k 1.00M 10.00M Frequency (Hz) 56

57 R14 100k R16 10M R13 100k C1 1G R_RLD 52k C_RLD 47n C7 33p C8 33p R17 1M C9 330p C6 33p C5 33p R12 1M R18 10M Vref The RL Drive Amplifier RL Drive Stability Simulation Circuit of Feedback #1 C2 47n R15 1M U1 OPA333 R4 52k V3 0 V4 0C4 47n R8 63.4k R9 63.4k RG1 25k RG V C10 1u Ref Out R7 52k R k R k RG2 25k RG V U3 INA333 L1 1G R3 10k R19 10M R2 100k VoA Vref U2 OPA333 Vloop U4 OPA333 Vref V1 2.5 V2 2.5 Vin 57

58 C1 1G R14 100k R16 10M R13 100k R_RLD 52k C_RLD 47n C7 33p C8 33p R17 1M C9 330p C6 33p C5 33p R12 1M Vref The RL Drive Amplifier RL Drive Stability Simulation Circuit of Feedback #2 C2 47n R15 1M U1 OPA333 V3 0 V4 0 R4 52k C4 47n R7 52k R8 63.4k R9 63.4k R k R k RG1 25k RG2 25k RG RG V V C10 1u Ref Out U3 INA333 R2 100k R1 10M VoA Vref U2 OPA333 L1 1G Vloop R3 10k Vref U4 OPA333 Vref V1 2.5 V2 2.5 Vin 58

59 R13 100k R14 100k R16 10M R_RLD 52k C_RLD 47n C7 33p C8 33p R17 1M C9 330p C6 33p C5 33p R12 1M Vref The RL Drive Amplifier RLD Stability Circuit with Compensated Amplifier C2 47n R15 1M U1 OPA333 Vcm R4 52k V3 0 V4 0C4 47n R8 63.4k R9 63.4k RG1 25k RG V C10 1u Ref Out Vout R7 52k R k R k RG2 25k RG V U3 INA333 R2 100k R5 10M C3 3.3n R1 10k NS1 2.5 NS R3 10k U4 OPA333 Vref V1 2.5 V2 2.5 Vref U2 OPA333 59

60 Gain (db) The RL Drive Amplifier RL Drive Stability Simulation of Separate Feedback Paths T AOL RLD Local R Feedback INA Electrode Loop Feedback Compensation Feedback Composite Feedback 1/ß k 10.00k k 1.00M 10.00M Frequency (Hz) 60

61 Gain (db) The RL Drive Amplifier Compensated RLD Circuit Simulation of 1/Beta and AOL Intersection T Intersection of 1/Beta and AOL curve is 20dB/dec = STABLE k 10.00M Frequency (Hz) 61

62 Phase [deg] TGain (db) The RL Drive Amplifier Gain and Phase Margin Plots of Compensated RLD Amplifier Loop Gain Phase 0dB = 70 degrees k 10.00M Frequency (Hz) 62

63 The RL Drive Amplifier Step Response of RLD Amplifier and ECG Output T m Vin VoA m 2.55 Vout m 10.00m Time (s) 63

64 The ECG Shield Drive 641

Eliminates Leakage from C P1 and C P2 Capacitance of cable can be 500

65 The ECG Shield Drive Shield drive eliminates leakage to ECG Inputs ECG P C P1 ECG N V CC /2 C P2 Shield is driven to (V IN() V IN( ) ) /2 Eliminates Leakage from C P1 and C P2 Capacitance of cable can be 500 pf to 1.5 nf Isolation resistor Necessary for improved EMI/RFI filtering 65

66 C1 1n C3 1T VG1 C7 33p C8 33p C9 330p C6 33p C5 33p R12 1M Vref The ECG Shield Drive AC Stability Simulation Circuit for OPA333 as Shield Driver NS3 2.5 NS R15 1M U1 OPA333 VF2 R4 10k C2 47n R8 63.4k R9 63.4k Vref R3 10k R5 1k C4 47n R7 1k R k R k R1 10k R2 10k RG RG V V C10 1u Ref Out U2 INA333 VF1 VinP VF3 Effective Cable Shield Capacitance U3 OPA333 Vout L1 1T VinN VF 66

67 Gain (db) The ECG Shield Drive AOL 1/Beta Response of OPA333 Shield Drive and 1nF Cable Capacitance dB/decade Intersection of AOL and 1/Beta = UNSTABLE k 10.00k k 1.00M Frequency (Hz) 67

68 C1 1n C7 33p C8 33p C9 330p C6 33p C5 33p R12 1M Vref The ECG Shield Drive TINA Simulation Circuit for Stabilized OPA333 Shield Driver NS3 2.5 NS R15 1M U1 OPA333 VF2 R4 10k C2 47n R8 63.4k R9 63.4k Vref R3 10k R5 1k C4 47n R7 1k R k R k R1 10k R2 10k RG RG V V C10 1u Ref Out U2 INA333 VF1 VinP VF3 U3 OPA333 R6 2k L1 1T VF C3 1T VG1 Shield Drive Compensation Network Vout C11 1n R13 10k 68

69 Phase [deg] Gain (db) The ECG Shield Drive TINA Simulation Shows > 45 Degrees Phase Margin for OPA333 Shield Driver k 1.00M Frequency (Hz) 69

70 Lead Off Detection 701

71 Lead Off Detection Lead Off Differentiates a Bad Lead from an Arrythmia BodyElectrode Model V CC V TH V REF V TH Pull up Resistors Force IN to Comparator High When Lead is Removed Comparator Voltage triggers ALERT Lead Off Indicative of Weak Lead 71

72 R20 1M R19 1M R5 1M SW2 1 R3 10M C7 33p R12 1M C8 33p C9 330p C6 33p C5 33p SW1 1 R15 10M R M R6 1M R13 10M VoltageControlled Switches Simulate Disconnected Lead R1 1k C2 47n Lead Off Detection TINA Simulation Circuit for Lead Off Detect VS VR R8 63.4k R9 63.4k VF3 VF1 Vref U1 TLV3701 VM1 NS1 2.5 NS R4 52k RG1 10k RG V Ref Out Vout C4 47n R k R k RG2 10k RG V U3 INA333 VS R2 1k R7 52k VF2 VG1 VS2 C3 47n R21 52k R18 100k R22 10k C1 10n R17 1M VR U2 TLV3701 VM2 VS2 VG2 U5 OPA348 R16 10k U4 OPA348 Vref 72

73 Lead Off Detection TINA Simulation Results for Lead Off Detect T 2.00 Vswitch VComparator u u u Time (s) 73

74 Pace Detection 741

75 Pace Detect Pace Maker Pulse Specifications d p a p t 0 a o a p = Amplitude (2700mV) a o = Overshoot d p = Pulse Width (.1100us) t 0 = Overshoot Time Constant (4100ms) Rise Time = 100us 75

R23 1M R22 1M R8 400k 100k R7 2M 33p 10k R17 1M R3 1M C9 330p R1 100k 10k 33p R6 2M R5 2M Pace Detect Pace Detect Circuitry in Parallel with ECG Signal Path Vpace Pos 47n ECGp 52k ECGn 47n Vpace Neg

76 R23 1M R22 1M R8 400k 100k R7 2M 33p 10k R17 1M R3 1M C9 330p R1 100k 10k 33p R6 2M R5 2M Pace Detect Pace Detect Circuitry in Parallel with ECG Signal Path Vpace Pos 47n ECGp 52k ECGn 47n Vpace Neg 52k 10n R20 100k U7 OPA348 Vref 63.4k 63.4k R18 10k U6 OPA348 RG V RG V Vref Vout Ref Out U5 INA333 OPA348 10n VECG_block R2 1k OPA348 Vref R4 100k C2 100p AC Coupled Input Blocks ECG Signal and Retains the PACER Pulse Window Comparator Triggers if PACER Signal Detected Separate PACER Processing Circuitry TLV3701 Vpace1 VPDetect Vpace2 TLV

77 2.51 Pace Detect PACE Signal Extracted From PACE ECG Waveform Vout m Vpace Pos m m m Time (s) 77

78 INA Post Gain and Filtering 781

79 INA Post Gain and Filtering Choice of High Gain SAR ADC OR Low Gain 24 bit Delta Sigma ADC At electrode High Gain with low noise amplifiers At ADC At At electrode Low gain At At ADC Amplitude x200 Noise free Dynamic range Amplitude Amplitude x5 A m p p n n o o i s i s e e ADC Noise Noise free Dynamic range Signal Chain Signal Chain a) Using a low resolution ADC b) Using a high resolution ADC SAR filter Option Results in Same InputReferred Noise as the DC Coupled DeltaSigma, but at what COST? 79

80 R13 1M R16 1M R14 1M R12 1M R20 2M C7 33p R17 10M C8 33p NS NS4 2.5 C9 330p C6 33p C5 33p R23 1M R15 2M C1 10p Vref INA Post Gain and Filtering INA Post Gain Amp With Differential Noise Source R21 2M Noise NS5 2.5 NS R1 1k C2 47n R4 1k R22 1M U1 OPA333 R18 2M ECGp ECGn C4 47n R8 63.4k R9 63.4k R k R k RG1 10k RG2 10k RG RG V V C10 1u Ref Out U3 INA333 NS NS2 2.5 R19 10k Vref U5 OPA333 Vout VF1 R2 1k R7 1k R6 1k R5 1M R3 10k U2 OPA333 Vref U4 OPA333 NS1 2.5 NS 80

81 INA Post Gain and Filtering Noise Coupled Differentially Translates to Output /60Hz Vout 50/60 Hz Couples Differentially; How Do We Get Rid of It? m m Time (s) 81

82 INA Post Gain and Filtering Use Filter Pro to Design a 50/60 Hz Notch 82

83 R13 1M R16 1M R23 1M R14 1M R k R12 1M R k R20 2M C7 33p R22 1M C8 33p R k R17 1M NS NS4 2.5 C9 330p C6 33p C5 33p R15 2M R30 1M INA Post Gain and Filtering ECG Circuit with Added 50/60Hz Notch Post Gain R1 1k ECGp ECGn C2 47n C4 47n R4 52k C1 10p R21 2M Noise R8 63.4k R9 63.4k R k R k RG1 10k RG2 10k U3 OPA333 C11 1u V RG Ref Out Vref Vout RG V U5 INA333_C C12 330n R k Vref R19 10k R18 1M U4 OPA348 U7 OPA378 VF2 R k C3 330n VF1 R2 1k R6 1k R7 52k C10 1n R3 10k R5 1M U2 OPA348 Vref U6 OPA348 NS1 2.5 NS Vref NS NS3 2.5 R k U1 OPA348 83

84 INA Post Gain and Filtering Plots of ECG Output with Gain and 60Hz Notch m Noise Vout_Filter Vout_PostGain Vout_INA m m m Time (s) 84

85 ECG (V) INA Post Gain and Filtering Line Cycle Sampling with SAR converter on T Wave at Common Frequency Multiples of 50/60Hz m m m m m 417m 433m 450m 467m 483m 500m 517m 533m 550m Time (s) F sample (Hz) = n*(1/50hz 1/60Hz) 1 = n*(27.27) Hz 85

86 INA Post Gain and Filtering Comparison of Delta Sigma ADC vs. Lower Resolution SAR ADC Using a low resolution ADC00 x Hz x Hz Elec 1 Elec 2 INA Elec 8 Elec 9 RL Elec 1 Elec 2 Patient Protection, Lead selection INA x5 INA DC blocking HPF Additional gain High order Anti aliasing filter Using a high resolution ADC 100 Hz MUX ADC 16 bit, 100KSps ADS1258 ` DOUT Reduced Hardware Filter Requirements Relaxed Lower Power Lower System Cost Electrode Offset Info Retained Patient Protection, Lead selection Simple RC filter MUX ADC DOUT Elec 8 INA 24 bit, 100KSps ` Elec 9 RL 86

87 INA Post Gain and Filtering Block Diagram of INA Gain, Simple RC Filter, and ADS1258 x5 x5 100 Hz 100 Hz lec 1 ec 2 Elec 1 Elec 2 INA INA ADS1258 ADS1258 Patient Protection, Lead selection Patient Protection, Lead selection Simple RC filter Simple RC filter MUX MUX ADC DOUT ADC DO ec 8 Elec 8 INA INA 24 bit, 100KSps ` 24 bit, 100KSps ` lec 9 Elec 9 L RL A single ADC in the MUX approach does not necessarily mean lower power due to the higher speed needed to perform MUX switching 87

88 ADS1298 Introduction 881

89 The ADS129x The AllInOne ECG Chip 89

90 ADS129x Input Amplifier Specifications for Single Channel AFE CH1P PGA BUF RLD 24bit DeltaSigma ADC CH1M PGA BUF CMOS input PGA High input impedance Low input current noise Rail to rail input Low Input Voltage Noise Current Noise = 0.1pA Hz Over Bandwidth No Output Phase Reversal 100dB 50/60 Hz 90dB 50/60 Hz IB = 150pA MAX vs. Temperature ZIN >100MΩ, CIN = 100pF max 90

91 ADS129x Noise Model for ECG AFE Noise is optimized with amplifier gain=4 The 4uV pp includes the crest factor of 6.6 to convert rms to pkpk Noise is referred to the input CH1P CH1M AFE ADC 91

92 ADS129x Programmable Data Rates for Low Power and High Resolution Modes 92

93 ADS129x MUX Selects Inputs to Front End PGA Normal Electrode Input Shorted RLD Input VDD TMP Sensor Input Test Signal 93

94 ADS129x Wilson Central Terminal Wilson Central Voltage 0.333(RALALL) Augmented Lead Voltages 0.5(RALA) 0.5(LALL) 0.5(RALL) *The Same Amplifiers Used to Derive the WCT Voltage Can be Switched to Obtain the Augmented Leads 94

ADS129x Input Amplifier and RLD Selection Lead I configuration /V CM2 V S R S AVDD V O = V S (1R2/R1) V CM1 (V CM2 V CM1 ) x (R2/R1) V O1 Right leg drive External RC R1 R2 200K 100K R S 5M

95 ADS129x Input Amplifier and RLD Selection Lead I configuration /V CM2 V S R S AVDD V O = V S (1R2/R1) V CM1 (V CM2 V CM1 ) x (R2/R1) V O1 Right leg drive External RC R1 R2 200K 100K R S 5M AVDD 200K RLD Sum (Register set) ADC2 /V CM2 V S R S AVDD V CM1 = AVDD/2 V O2 R1 R2 *Compensation of RLD Amplifier is Based on the Gain Selected and the Number of Amplifiers in the Loop 95

96 ADS129x RLD Selection 8 Channel Case Cext 264pF CH1P CH1N CH3P CH3N CH5P CH5N CH7P CH7N RLDINV Rext 10M RLDOUT RLDREF RLDREF_INT RLDP1 50K 50K RLDP3 50K 220K 220K 220K 50K 220K RLDM3 RLDP5 50K 220K RLDP7 50K RLD AMP 20K RLDM1 20K 20K 220K 50K 220K RLDM5 20K 50K 220K RLDM7 220K 220K 220K 220K 220K 220K 220K 220K RLDP2 20K RLDM2 RLDP4 20K RLDM4 RLDP6 20K RLDM6 RLDP8 20K RLDM8 50K 50K 50K 50K 50K 50K 50K 50K RLDREF_INT AVDD AVSS WCT_TO_RLD 2 CH2N CH2N CH4P CH4N CH6P CH6N CH8P CH8N WCT RLD Electrode REXT 2M RLIM R1 R2 RLD_INV CEXT 264pF RLD_OUT RLD_REF RLD AMP /RLDREF_INT All switches can be controlled by register settings ADS129x 220K 220K CH1P CH8M AVDD AVSS RLDREF_INT 2 *Multiple PGA Outputs Can Be Switched to Derive Inverting RLD 96

97 To Input Mux To Input Mux To Input Mux To Input Mux To Input Mux ADS129x RLD with Multiple Devices To Input Mux Device 1 VA18 Device 2 Power Down VA18 Device 1 VA18 RLD IN RLD REF RLD OUT RLD INV RLD IN RLD REF RLD OUT RLD INV RLD IN RLD REF RLD OUT RLD INV Device n Device 2 Device 1 Power Down Power Down VA18 VA18 VA18 RLD IN RLD REF RLD OUT RLD INV RLD IN RLD REF RLD OUT RLD INV RLD IN RLD REF RLD OUT RLD INV *With Multiple Devices the RLD Output Becomes the Amplified Difference Between RLD REF and the Summation of Multiple Lead Outputs 97

98 100K 200K ADS129x Pace Detect 100K 100K >From CH1P >From CH1N >From CH3P >From CH3N >From CH5P >From CH5N >From CH7P >From CH7N 00xx 50K 50K 500K 500K 500K 01xx 50K 50K 500K 01xx 500K 10xx 50K 50K 20K 00xx 20K 20K 500K 10xx 500K 11xx 50K 20K 50K 500K 11xx VREFCM PACE_ODD [4:1] 500K 500K 500K 500K 500K 500K 500K 500K xx00 20K xx00 xx01 20K xx01 xx10 20K xx10 xx11 20K xx11 50K 50K 50K 50K 50K 50K 50K 50K From CH2P< From CH2N< From CH4P< From CH4N< From CH6P< From CH6N< From CH8P< From CH8N< *Separate Pace Amplifiers Allow External Processing of Pace Signal; All Channels do Not Have to Operate at Higher Data Rates PACE_OUT1 PACE_OUT2 PDB_PACE_ODD PACE AMP 100K PDB_PACE_EVEN PACE AMP VREFCM VREFCM 250K 250K 250K 250K 250K 250K 250K ADS129x CH1P CH7P PACE_ODD[0:1] CH1M CH7M CH2P CH8P PACE_EVEN[0:1] CH2M TESTN_PACE_OUT2 PDB_PACE PACE AMP 100K (AVDDAVSS)/2 GPIO1 PACE_IN(GPIO1) PACE ODD PACEO1 100K PACEO0 PACE EVEN PACEE1 250K PACEE0 CH8M CHANNEL SELECTED TESTP_PACE_OUT1 PDB_PACE 200K PACE AMP x 0 x 0 x 1 x 1 x 0 x 1 x 0 x 1 0 x 0 x 1 x 1 x 0 x 1 x 0 x 1 x Channel #1 Channel #2 Channel #3 Channel #4 Channel #5 Channel #6 Channel #7 Channel #8 98

99 < R1 ~ 10M > ADS129x Lead Off Detection AVDD AVSS LOFF_FLIP FLEAD_OFF[0:1] FREQ = DC, FDR/2 or FDR/4 Patient Skin Electrode Contact Model Patient Protection Resistor FLEAD_OFF[[1:0] V X AntiAliasing Filter <512KHz Z 1 47nF LOFF_SENSP & VLEAD_OFF_EN LOFF_SENSM & VLEAD_OFF_EN LOFF_STATP 51K 51K 100K 100K R 2 R 2 EMI Filter V INP V INM To ADC Z 2 47nF LOFF_SENSP & VLEAD_OFF_EN LOFF_SENSM & VLEAD_OFF_EN LOFF_STATM LOFF_FLIP 25, , 12.5, & 6.25nA 4bit DAC COMP_TH[2:0] Z 3 51K 100K R 3 AVDD AVSS ILEAD_OFF[0:1] RLD OUT 99

100 ADS129x Respiration Testing Measures the Change in Thoracic Impedance with Inhalation of O 2 PATIENT S CHEST E4 ADS129x R PROTEC T 100K PATIENT S CHEST E2 ADS129x R PROTEC T 100K E3 R PROTEC T 100K R THORAX E1 R PROTEC T 100K V 64KHz R THORAX E2 R PROTEC T 100K V 64KHz *AC Current is injected into the Patient s Thorax and the Change in Voltage is Measured to Calculate Change in Impedance E1 R PROTEC T 100K 100

101 RESPIRATION GPIO ADS129x Respiration Functions ADS129x GPIO1 GPIO2 GPIO3/ RESP_OUT GPIO4/ RESP_PH_OUT RESP_MODE RESP_PH [4:2] Changing Phase Allows Measurement/Compensation for Complex Impedance Phase Shifts Between Modulator and Demodulator RESP_PH[4:2] bit CODE RESP_ PH RESP_ PH RESP_P H PHASE SELECTED 22.5 Deg 45 Deg 67.5 Deg 90 Deg Deg 135 Deg Deg 180 Deg 101

102 ADS129x Internal Voltage Reference Simplified ADS129x internal reference block diagram The Internal Band Gap Accuracy = 1% Internal REF can be Powered Down VREFP Can Be Supplied Externally 102

103 Thank You Contact Information: 103

104 Questions? 1041

105 Acknowledgements Beraducci, Mark and Soundarapandian, Karthik. Sbaa160, Application Report: Analog Front End Design of ECG Systems Using DeltaSigma ADCs. March Brown, John Burr Brown Strategic Marketer, general information Brown, John and Joseph Carr. Introduction to Biomedical Equipment Technology. Prentice Hall Inc. New Jersey. 1981, Dubin, Dale. Rapid Interpretation of EKG s. Cover Publishing Company. Fort Myers Fraden, Jacob. Handbook of Modern Sensors Physics, Designs, and Applications. Advanced Monitors Corporation. San Diego Franco, Sergio. Design with Operational Amplifiers. McGrawHill Inc. NY Fredericksen, Thomas M. Intuitive Operational Amplifiers. McGrawHill Inc Graeme, Toby, Huelsman. Operational Amplifiers Design and Applications. McGraw Hill Publishing Company. New York Gray, Paul R. and Meyer, Robert G. Analysis and Design of Analog Integrated Circuits. John Wiley & Sons. New York Green, Timothy Linear Applications Manager, general information Kuehl, ThomasLinear Applications Engineer, general information Norton, Harry N. Sensor and Analyzer Handbook. Prentice Hall Inc. New Jersey Soundarapandian, KarthikOver sampling Manager, general information 105

Analog Signal Chain considerations for Medical applications. Bio-Potential signals (ECG/EEG)

Analog Signal Chain considerations for Medical applications Bio-Potential signals (ECG/EEG) Bio-potential signals Types of bio-potential signals & other related measurements Electro-Cardiogram Signal chain