High Common-Mode Voltage, Single-Supply Difference Amplifier AD8202

Transcription

1 Data Sheet High Common-Mode Voltage, Single-Supply Difference Amplifier AD FEATURES High common-mode voltage range V to + V at a V supply voltage Operating temperature range: C to + C Supply voltage range:. V to V Low-pass filter (-pole or -pole) Excellent ac and dc performance ± mv voltage offset ± ppm/ C typical gain drift db CMRR min dc to khz Qualified for automotive applications APPLICATIONS Transmission control Diesel injection control Engine management Adaptive suspension control Vehicle dynamics control GENERAL DESCRIPTION The AD is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage (CMV). The input CMV range extends from V to + V at a typical supply voltage of V. The AD is available in die and packaged form. The MSOP and SOIC packages are specified over a wide temperature range, from C to + C, making the AD well-suited for use in many automotive platforms. Automotive platforms demand precision components for better system control. The AD provides excellent ac and dc performance keeping errors to a minimum in the user s system. Typical offset and gain drift in the SOIC package are. µv/ C and ppm/ C, respectively. Typical offset and gain drift in the MSOP package are µv/ C and ppm/ C, respectively. The device also delivers a minimum CMRR of db from dc to khz. BATTERY BATTERY kω FUTIONAL BLOCK DIAGRAMS kω A A CLAMP DIODE V V CLAMP DIODE A kω G = G = A Figure. SOIC (R) Package Die Form POWER DEVICE COMMON -TERM SHUNT INDUCTIVE LOAD V AD A Figure. High Line Current Sensor -TERM SHUNT POWER DEVICE INDUCTIVE LOAD kω kω A AD 9- PUT V AD A A PUT 9- The AD features an externally accessible kω resistor at the output of the Preamp A that can be used for low-pass filter applications and for establishing gains other than. COMMON Figure. Low Line Current Sensor 9- Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel:.9. Analog Devices, Inc. All rights reserved. Technical Support

2 AD TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Revision History... Specifications... Single Supply... Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... Data Sheet Theory of Operation... Applications... Current Sensing... Gain Adjustment... Gain Trim... Low-Pass Filtering... High Line Current Sensing with LPF and Gain Adjustment Driving Charge Redistribution ADCs... Outline Dimensions... Ordering Guide... Automotive Products... REVISION HISTORY / Rev. G to Rev. H Added Unit of mv to Initial Input Offset (RTI), TOPR Parameter; Table... / Rev. F to Rev. G Changes to Features Section and General Description Section... Changes to Table... Changes to Ordering Guide... / Rev. E to Rev. F Changes to Table and Figure... / Rev. D to Rev. E Change to Features Section... Changes to Ordering Guide... Updated Outline Dimensions... Added Automotive Products Section... / Rev. C to Rev. D Updated Format... Universal Changes to Typical Performance Characteristics... Added Figure... Added Figure to Figure... 9 Added Figure... Added Figure to Figure 9... Changes to Theory of Operation... Added Figure... / Rev. B to Rev. C Changes to Table... Changes to Figure... Changes to Figure... 9 / Rev. A to Rev. B Changes to the General Description... Changes to Specifications... Added Figure to Figure... Changes to Figure... Changes to Figure and Figure... Changes to Ordering Guide... / Rev. to Rev. A Changes to the Features... Changes to the General Description... Changes to Specifications (Table )... Changes to Absolute Maximum Ratings (Table )... Changes to Pin Function Descriptions (Table )... Changes to Figure... Changes to Figure 9 and Figure... Updated Outline Dimensions... Changes to the Ordering Guide... / Revision : Initial Version Rev. H Page of

3 Data Sheet AD SPECIFICATIONS SINGLE SUPPLY TOPR = operating temperature range, VS = V, unless otherwise noted, RTI = referred to input, VCM = common-mode voltage. Table. AD SOIC AD MSOP AD Die Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit SYSTEM GAIN Initial V/V Error vs. Temperature. V. V dc, TOPR ±. ±. ±. % Gain Drift TOPR ± ± ± ppm/ C VOLTAGE OFFSET Initial Input Offset (RTI), TOPR ± ± ± mv Offset vs. Temperature VCM = V, TOPR ± ± ± μv/ C INPUT Input Impedance Differential kω Common Mode kω CMV Continuous V CMRR VCM = V to + V f = dc to khz db f = khz db PREAMPLIFIER Gain V/V Gain Error ±. ±. ±. % Output Voltage Range V Output Resistance kω PUT BUFFER Gain V/V Gain Error. V. V dc, TOPR ±. ±. ±. % Output Voltage Range V Input Bias Current na Output Resistance Ω DYNAMIC RESPONSE System Bandwidth VIN =. V p-p; V =. V p-p khz Slew Rate VIN =. V dc; V = V step... V/μs NOISE. Hz to Hz μv p-p Spectral Density, khz (RTI) nv/ Hz POWER SUPPLY Operating Range... V Quiescent Current vs. VO =. V dc ma Temperature PSRR VS =. V to V db TEMPERATURE RANGE For Specified Performance TOPR C Die is specified for operation from C to + C ( TOPR for DIE). Source imbalance < Ω. The AD preamplifier exceeds db CMRR at khz. However, because the signal is available only by way of a kω resistor, even the small amount of pin-topin capacitance between Pin, Pin and Pin, Pin might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-to-pin coupling can be neglected in all applications by using filter capacitors at Node. The output voltage range of A assumes that Pin (A output) and Pin (A Input) are shorted together. A kω load resistor was used for testing. Rev. H Page of

4 AD ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage. V Transient Input Voltage ( ms) V Continuous Input Voltage (Common Mode) V Reversed Supply Voltage Protection. V Operating Temperature Range Die C to + C SOIC C to + C MSOP C to + C Storage Temperature C to + C Output Short-Circuit Duration Indefinite Lead Temperature Range (Soldering, sec) C Data Sheet Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. H Page of

5 Data Sheet AD PIN CONFIGURATION AND FUTION DESCRIPTIONS A A AD TOP VIEW (Not to Scale) 9- Figure. Pin Configuration Table. Pin Function Descriptions Pin No. Mnemonic X Y IN +9 + A 9 A 9 + +VS + N/A N/A N/A = not applicable. (CIRCUIT SIDE) Figure. Metallization Photograph 9- Rev. H Page of

6 AD Data Sheet TYPICAL PERFORMAE CHARACTERISTICS TA = C, VS = V, V CM = V, RL = kω, unless otherwise noted. 9 PSRR (db) COMMON-MODE VOLTAGE (V) C C + C + C k k k 9- + C FREQUEY (Hz) POWER SUPPLY (V) Figure. Power Supply Rejection Ratio vs. Frequency Valid for CM Range V to + V Figure 9. Negative Common-Mode Voltage vs. Voltage Supply PUT (db) k k k M FREQUEY (Hz) Figure. Bandwidth 9- COMMON-MODE VOLTAGE (V) C C + C + C + C 9 POWER SUPPLY (V) Figure. Positive Common-Mode Voltage vs. Voltage Supply CMRR (db) 9 PUT SWING (V)..... k k k 9-.. k k 9- FREQUEY (Hz) LOAD RESISTAE (Ω) Figure. Common-Mode Rejection Ratio vs. Frequency Valid for Common-Mode Range V to + V Figure. Output Swing vs. Load Resistance Rev. H Page of

7 Data Sheet AD TEMPERATURE = C PUT MINUS SUPPLY (mv) NO LOAD k LOAD 9 SUPPLY VOLTAGE (V) Figure. Output Minus Supply vs. Supply Voltage 9- CMRR (µv/v) Figure. CMRR Distribution, V to + V Common Mode 9- PUT V SUPPLY = V C TO + C INPUT CH mvω CH mvω M µs.ms/s NS/PT A CH.V Figure. Pulse Response 9- V OS DRIFT (µv/ C) Figure. Offset Drift Distribution, MSOP, Temperature Range = C to + C 9- V SUPPLY = V C TO C V OS (µv) C + C + C + C COMMON-MODE VOLTAGE (V) Figure. VOS vs. Common-Mode Voltage 9- V OS DRIFT (µv/ C) Figure. Offset Drift Distribution, MSOP, Temperature Range = C to C 9- Rev. H Page of

8 AD Data Sheet 9 V SUPPLY = V C TO C 9 TEMPERATURE = C V OS DRIFT (µv/ C)..... V OS (µv) Figure. Offset Drift Distribution, MSOP, Temperature Range = C to C Figure. VOS Distribution, MSOP, Temperature = C TEMPERATURE = C TEMPERATURE = C 9-9- V OS (µv) ERROR (%) Figure 9. VOS Distribution, MSOP, Temperature = C Figure. MSOP Gain Accuracy, Temperature = C 9 TEMPERATURE = C TEMPERATURE = C V OS (µv) ERROR (%) 9- Figure. VOS Distribution, MSOP, Temperature = C Figure. MSOP Gain Accuracy, Temperature = C Rev. H Page of

9 Data Sheet AD TEMPERATURE = C 9 V SUPPLY = V C TO C ERROR (%) Figure. MSOP Gain Accuracy, Temperature = C 9- GAIN DRIFT (PPM/ C) Figure. Gain Drift Distribution, MSOP, Temperature Range = C to C 9-9 V SUPPLY = V + C TO C TEMPERATURE = C 9-9- GAIN DRIFT (PPM/ C) 9 V OS (µv) 9 Figure. Gain Drift Distribution, MSOP, Temperature Range = + C to C Figure. VOS Distribution, SOIC, Temperature = C 9 V SUPPLY = V C TO C TEMPERATURE = C GAIN DRIFT (PPM/ C) V OS (µv) 9 9- Figure. Gain Drift Distribution, MSOP, Temperature Range = C to C Figure 9. VOS Distribution, SOIC, Temperature = C Rev. H Page 9 of

10 AD Data Sheet TEMPERATURE = C V SUPPLY = V C TO C V OS (µv) V OS DRIFT (µv/ C) Figure. VOS Distribution, SOIC, Temperature = C Figure. Offset Drift Distribution, SOIC, Temperature Range = C to C V SUPPLY = V C TO + C TEMPERATURE = C V OS DRIFT (µv/ C).... Figure. Offset Drift Distribution, SOIC, Temperature Range = C to + C ERROR (%) Figure. Gain Accuracy, SOIC, Temperature = C 9- V SUPPLY = V C TO C TEMPERATURE = C V OS DRIFT (µv/ C) Figure. Offset Drift Distribution, SOIC, Temperature Range = C to C ERROR (%) Figure. Gain Accuracy, SOIC, Temperature = C 9- Rev. H Page of

11 Data Sheet AD TEMPERATURE = C V SUPPLY = V C TO C ERROR (%) Figure. Gain Accuracy, SOIC, Temperature = C V SUPPLY = V + C TO C GAIN DRIFT (PPM/ C) Figure. Gain Drift Distribution, SOIC, Temperature Range = C to C V SUPPLY = V C TO C GAIN DRIFT (PPM/ C) GAIN DRIFT (PPM/ C) Figure. Gain Drift Distribution, SOIC, Temperature Range = + C to C Figure 9. Gain Drift Distribution, SOIC, Temperature Range = C to C Rev. H Page of

12 AD THEORY OF OPERATION The AD consists of a preamp and buffer arranged as shown in Figure. Like-named resistors have equal values. The preamp uses a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of RA, RB, RC, and RG, attenuate input signals applied to Pin and Pin. When equal amplitude signals are asserted at Input and Input, and the output of A is equal to the common potential (that is, ), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A, and thus its output, is. Any common-mode voltage applied to both inputs keeps the bridge balanced and the A output at. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A. A responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pin and Pin, the amplifier inputs are held within the power supply range, even if Pin and Pin input levels exceed the supply or fall below common (ground). The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A feedback, forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at. Because the differential input signal is attenuated and then amplified to yield an overall gain of, Amplifier A operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pin and Pin. R G R A R B R C R A R B R C R CM R kω A CM (TRIMMED) R G A AD A R F R F Data Sheet To minimize these errors while extending the common-mode range, a dedicated feedback loop is used to reduce the range of common-mode voltage applied to A for a given overall range at the inputs. By offsetting the voltage range applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. Amplifier A detects the common-mode signal applied to A and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. The output of the dynamic bridge taken from A is connected to Pin by way of a kω series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. The output of the preamp drives a gain-of- buffer amplifier, A, implemented with carefully matched feedback resistors (RF). The -stage system architecture of the AD enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale, rail-to-rail signal from the preamp can be filtered at Pin, and a half-scale signal, resulting from filtering, can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A is approximately kω to minimize the effects of the input bias current of A. However, this current is quite small, and errors resulting from applications that mismatch the resistance are correspondingly small. The A input bias current has a typical value of na, however, this can increase under certain conditions. For example, if the input signal to the A amplifier is VCC/, the output attempts to go to VCC due to the gain of. However, the output saturates because the maximum specified voltage for correct operation is mv below VCC. Under these conditions, the total input bias current increases (see Figure for more information). COM 9- Figure. Simplified Schematic Rev. H Page of

13 Data Sheet AD A INPUT BIAS CURRENT (na) V SUPPLY = V + C TO C..... DIFFERENTIAL-MODE VOLTAGE (V) Figure. A Input Bias Current vs. Input Voltage and Temperature. The Shaded Area is the Bias Current from + C to C. 9- The total error at the input of A, mv, multiplied by the buffer gain generates a resulting error of mv at the output of the buffer. This is AD system output low saturation potential. The high output voltage range of the AD is specified as. V. Therefore, assuming a typical A input bias current, the output voltage range for the AD is mv to. V. For an example of the effect of changes in A input bias current vs. applied input potentials, see Figure. The change in bias current causes a change in error voltage at the input of the buffer amplifier. This results in a change in overall error potential at the output of the buffer amplifier. An increase in the A bias current, in addition to the output saturation voltage of A, directly affects the output voltage of the AD system (Pin and Pin shorted). An example of how to calculate the correct output voltage swing of the AD, by taking all variables into account, follows: Amplifier A output saturation potential can drop as low as mv at its output. A typical input bias current of na multiplied by the kω preamplifier output resistor produces na kω = mv at the A input Total voltage at the A input equals the output saturation voltage of A combined with the voltage error generated by the input bias current mv + mv = mv Rev. H Page of

14 AD APPLICATIONS The AD difference amplifier is intended for applications that require extracting a small differential signal in the presence of large common-mode voltages. The differential input resistance is nominally kω, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open collector output stage sources current to within mv of ground and to within mv of VS. CURRENT SENSING High Line, High Current Sensing Basic automotive applications using the large common-mode range are shown in Figure and Figure. The capability of the device to operate as an amplifier in primary battery supply circuits is shown in Figure ; Figure illustrates the ability of the device to withstand voltages below system ground. Low Current Sensing The AD is also used in low current sensing applications, such as the to ma current loop shown in Figure. In such applications, the relatively large shunt resistor can degrade the common-mode rejection. Adding a resistor of equal value on the low impedance side of the input corrects for this error. + Ω % Ω % V AD A A PUT Figure. to ma Current Loop Receiver 9- V CM A A R EXT Data Sheet V DIFF kω kω R EXT GAIN = R EXT + kω AD V DIFF kω R EXT = kω GAIN GAIN Figure. Adjusting for Gains Less than The overall bandwidth is unaffected by changes in gain by using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. This can often be ignored, but if desired, it can be nulled by inserting a resistor equal to kω minus the parallel sum of REXT and kω, in series with Pin. For example, with REXT = kω (yielding a composite gain of ), the optional offset nulling resistor is kω. Gains Greater Than Connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in Figure, increases the gain. The gain is multiplied by the factor REXT/(REXT kω); for example, the gain is doubled for REXT = kω. Overall gains as high as are achievable in this way. The accuracy of the gain becomes critically dependent on the resistor value at high gains. Also, the effective input offset voltage at Pin and Pin (about six times the actual offset of A) limits the part s use in high gain, dc-coupled applications. 9- GAIN ADJUSTMENT The default gain of the preamplifier and buffer are and, respectively, resulting in a composite gain of. With the addition of external resistor(s) or trimmer(s), the gain can be lowered, raised, or finely calibrated. V CM V DIFF kω kω R EXT GAIN = R EXT kω AD R EXT V DIFF kω R EXT = kω GAIN GAIN A A Gains Less than Because the preamplifier has an output resistance of kω, an external resistor connected from Pin and Pin to decreases the gain by a factor REXT/( kω + REXT) as shown in Figure. Figure. Adjusting for Gains > 9- Rev. H Page of

15 Data Sheet AD GAIN TRIM Figure shows a method for incremental gain trimming by using a trim potentiometer and external resistor, REXT. The following approximation is useful for small gain ranges: ΔG ( MΩ/REXT)% Thus, the adjustment range is ±% for REXT = MΩ; ±% for REXT = MΩ, and so on. V CM V DIFF V DIFF V AD A A R EXT Figure. Incremental Gain Trim Internal Signal Overload Considerations GAIN TRIM kω MIN When configuring gain for values other than, the maximum input voltage with respect to the supply voltage and ground must be considered because either the preamplifier or the output buffer reaches its full-scale output (approximately VS. V) with large differential input voltages. The input of the AD is limited to (VS.)/ for overall gains because the preamplifier, with its fixed gain of, reaches its fullscale output before the output buffer. For gains greater than, the swing at the buffer output reaches its full scale first and limits the AD input to (VS.)/G, where G is the overall gain. LOW-PASS FILTERING In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of., a raised cosine has a PAR of, and a half-wave sinusoid has a PAR of.. Signals having large spikes can have PARs of or more. When implementing a filter, the PAR should be considered so that the output of the AD preamplifier (A) does not clip before A because this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier ( for the default configuration). For example, if a PAR of is expected, the gain of A should be increased to. 9- Low-pass filters can be implemented in several ways by using the AD. In the simplest case, a single-pole filter ( db/decade) is formed when the output of A is connected to the input of A via the internal kω resistor by tying Pin and Pin and adding a capacitor from this node to ground, as shown in Figure. If a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and kω. V CM V DIFF V DIFF V AD A A C PUT f C = πc C IN FARADS Figure. Single-Pole, Low-Pass Filter Using the Internal kω Resistor If the gain is raised using a resistor, as shown in Figure, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of kω (for which the gain would be doubled), the corner frequency is now.9 Hz/µF (.9 µf for a Hz corner frequency). V CM V DIFF V DIFF V AD A C A Figure. -Pole, Low-Pass Filter C kω f C (Hz) = /C(µF) A -pole filter (with a roll-off of db/decade) can be implemented using the connections shown in Figure. This is a Sallen-Key form based on a amplifier. It is useful to remember that a -pole filter with a corner frequency f and a -pole filter with a corner at f have the same attenuation at the frequency (f /f). The attenuation at that frequency is log (f/f), which is illustrated in Figure. Using the standard resistor value shown and equal capacitors (see Figure ), the corner frequency is conveniently scaled at Hz/µF (. µf for a Hz corner). A maximally flat response occurs when the resistor is lowered to 9 kω and the scaling is then. Hz/µF. The output offset is raised by approximately mv (equivalent to µv at the input pins) Rev. H Page of

16 AD Data Sheet ATTENUATION FREQUEY db/decade db/decade by a -pole low-pass filter, set with a corner frequency of. Hz, providing about db of attenuation at Hz. A higher rate of attenuation can be obtained using a -pole filter with fc = Hz, as shown in Figure. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the -pole filter. LOG (f /f ) A -POLE FILTER, CORNER f, AND A -POLE FILTER, CORNER f, HAVE THE SAME ATTENUATION LOG (f /f ) AT FREQUEY f /f 9- BATTERY CLAMP DIODE V -TERM SHUNT INDUCTIVE LOAD V AD C kω kω PUT f f f /f Figure. Comparative Responses of -Pole and -Pole Low-Pass Filters POWER DEVICE A A kω HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT Figure 9 is another refinement of Figure, including gain adjustment and low-pass filtering. BATTERY CLAMP DIODE V -TERM SHUNT POWER DEVICE INDUCTIVE LOAD COMMON AD V A C A V OS/IB NULL Figure 9. High Line Current Sensor Interface; Gain =, Single-Pole, Low-Pass Filter V/AMP 9kΩ kω % CALIBRATION RANGE f C (Hz) =.9Hz/C(µF) (.µf FOR f C =.Hz) A power device that is either on or off controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically mv, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, conversely, extends from roughly V above ground for the on condition to about. V above the battery voltage in the off condition. The conduction of the clamping diode regulates the common-mode potential applied to the device. For example, a battery spike of V can result in an applied common-mode potential of. V to the input of the devices. 9- COMMON Figure. -Pole Low-Pass Filter C f C (Hz) = /C(µF) (.µf FOR f C = Hz) DRIVING CHARGE REDISTRIBUTION ADCS When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection ( Q) can cause a significant deflection in the output voltage of the AD. Though generally of short duration, this deflection can persist until after the sample period of the ADC expires due to the relatively high open-loop output impedance (typically kω) of the AD. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the AD. For these applications, the output signal should be taken from the midpoint of the RLAG CLAG combination, as shown in Figure. Because the perturbations from the analog-to-digital converter are small, the output impedance of the AD appears to be low. The transient response, therefore, has a time constant governed by the product of the two LAG components, CLAG RLAG. For the values shown in Figure, this time constant is programmed at approximately µs. Therefore, if samples are taken at several tenths of microseconds or more, there is negligible charge stack-up. V AD A kω R LAG kω C LAG.µF MICROPROCESSOR A/D 9- To produce a full-scale output of V, a gain is used, adjustable by ±% to absorb the tolerance in the shunt. Sufficient headroom allows % overrange (to. V). The roughly triangular voltage across the sense resistor is averaged kω Figure. Recommended Circuit for Driving CMOS A/D 9- Rev. H Page of

17 Data Sheet AD LINE DIMENSIONS. (.9). (.9).... (.). (.9). (.9). (.) COPLANARITY. SEATING PLANE. (.) BSC. (.). (.). (.). (.). (.). (.). (.9). (.). (.9). (.99). (.). (.) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; IH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. -A... PIN IDENTIFIER COPLANARITY.. BSC MAX MAX..9 COMPLIANT TO JEDEC STANDARDS MO--AA B Figure. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) Figure. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters ORDERING GUIDE Model, Temperature Range Package Description Package Option Branding ADWYC-P C to + C Die ADWYC-P C to + C Die ADWYRMZ C to + C -Lead Mini Small Outline Package [MSOP] RM- JWY ADWYRMZ-RL C to + C -Lead Mini Small Outline Package [MSOP] RM- JWY ADWYRZ C to + C -Lead Standard Small Outline Package [SOIC_N] R- ADWYRZ-RL C to + C -Lead Standard Small Outline Package [SOIC_N] R- ADYRMZ C to + C -Lead Mini Small Outline Package [MSOP] RM- JWY ADYRMZ-R C to + C -Lead Mini Small Outline Package [MSOP] RM- JWY ADYRMZ-RL C to + C -Lead Mini Small Outline Package [MSOP] RM- JWY ADYRZ C to + C -Lead Standard Small Outline Package [SOIC_N] R- ADYRZ-RL C to + C -Lead Standard Small Outline Package [SOIC_N] R- ADYRZ-R C to + C -Lead Standard Small Outline Package [SOIC_N] R- Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADW models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. H Page of

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20 AD Data Sheet NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--/(H) Rev. H Page of