36V System Power Supply with Watchdog Timer for Automotive Applications

Transcription

1 Series 36V System Power Supply with Watchdog Timer for Automotive Applications OUTLINE R511S is the system power supply and supervisor IC based on the high-voltage CMOS process technology, and has high accuracy and ultra low supply current voltage. R511S consists of a voltage regulator (VR), a voltage detector (VD), and a normal / window type of watchdog timer (WDT) in a chip, and can provide three functions of the system power supply, the supply voltage supervisor, and the supervision of system s misoperation. Voltage Regulator allows the output current of 5mA. And, VR has the inrush current protection circuit for rising pulse (Typ.4mA or less). Voltage Detector outputs a reset signal when a reduction of supply voltage (SENSE / V OUT ) is detected, and the reset signal is used as system reset. The detection voltage is internally fixed in an IC. And, the delay time is adjustable with an external capacitor because VD has the built-in release delay circuit (the power-on reset circuit). When the supply voltage is higher than the release output voltage, VD maintains the reset state during the delay time. The output type of RESETB and D OUT are Nch open-drain. In addition, R511Sxx2C and R511Sxx2D (Detector with SENSE pin) have a manual reset (MR) pin. Watchdog Timer detects the microprocessor output pulse. In addition to the normal type of WDT (R511Sxx1A / R511Sxx2C) that outputs a reset signal when the detected pulse period is longer than normal, R511S supports the window type of WDT (R511Sxx1B / R511Sxx2D) that outputs a reset signal when the detected pulse period is shorter or longer. RESETB outputs the reset signal when using R511Sxx1A / R511Sxx1B, and the WDO pin outputs L as the reset signal when using R511Sxx2C / R511Sxx2D. The output type of WDO is Nch open-drain. In addition, R511Sxx2C and R511Sxx2D have an inhibiting (INH) pin to stop the watchdog timer s monitoring function. The time out period of Watchdog Timer is also adjustable with an external capacitor. R511S supports the packages of HSOP-8E and HSOP-18. FEATURES Operating Voltage Range (Maximum Rating) 3.5V to 36.V (5.V) Operating Temperature Range 4 C to 125 C Supply Current Typ. 25µA Supply Current (On standby) Typ..1µA <Voltage Regulator (VR)> Output Voltage Range 1.8V to 5.V Dropout Voltage Typ..5V (V OUT = 5.V, 5mA) Output Voltage Accuracy ±1.5% ( 4 to 125 C) Output Voltage Temperature Coefficient Typ. ±1ppm/ C Built-in Short Current Limit Circuit Typ. 8mA Built-in Overcurrent Protection Circuit Min. 5mA Built-in Thermal Shutdown Circuit Typ.165 C Recommended Ceramic Capacitor.1µF or more 1

2 <Voltage Detector (VD)> Detector Threshold Range 1.6V ~ 5.5V Detector Threshold Accuracy ±1.8% ( 4 to 125 C) Release Delay Accuracy ±2% ( 4 to 125 C) Release Delay Time Typ. 242ms (C D =.22 µf) Delay Time is adjustable with an external capacitor. <Watchdog Timer (WDT)> Open Window Accuracy ±2% ( 4 to 125 C) Open Window Time Typ.18ms (C TW = 1nF) Closed Window Time Typ.18ms (C TW = 1nF) Long Open Window Time Typ.72ms (C TW = 1nF) Ignoring Time Typ.18ms (C TW = 1nF) Monitoring Time Typ.18ms (C TW = 1nF) Reset Time Typ.9.5ms (C TW = 1nF) Each time is adjustable with an external capacitor. APPLICATIONS Power source for car accessories including car audio equipment, car navigation system, and ETC system. Power source for control units including EV inverter and charge control. 2

3 BLOCK DIAGRAMS R511Sxx1A / R511Sxx1B VDD CE Thermal shut down ON/OFF Circuit VOUT Internal Supply Voltage Current Limit GND VOUT CD RESETB SCK CLOCK DETECTOR WATCHDOG TIMER (R511xx1A) WINDOW WATCHDOG TIMER (R511xx1B) TW R511Sxx2C / R511Sxx2D VDD CE Thermal shut down ON/OFF Circuit VOUT Internal Supply Voltage Current Limit GND MR CD SENSE DOUT INH TW SCK CLOCK DETECTOR WATCHDOG TIMER (R511Sxx2C) WINDOW WATCHDOG TIMER (R511Sxx2D) WDO 3

4 SELECTION GUIDE R511S user selectable options (Watchdog Timer type, Detector type, and additional functions with using MR / INH / WDO pins) are as follows: Product Name Package Quantity per Reel Pb Free Halogen Free R511Sxx1 -E2-#E HSOP-8E 1, pcs Yes Yes R511Sxx2 -E2-#E HSOP-18 1, pcs Yes Yes xx: Specify the set output voltage (V SET ) and the set detector threshold (-V SET ) by using serial numbers starting from 1. Refer to Mark Specification Table for details. Detector Watchdog Timer MR / INH / RESETB/ Package Monitoring Voltage Type WDO pins D OUT pins A V OUT HSOP-8E Normal RESETB B V OUT HSOP-8E Window RESETB C SENSE HSOP-18 Normal Yes D OUT D SENSE HSOP-18 Window Yes D OUT Specify the automotive class code. Operating Guaranteed Specs Temperature Range Temperature Range Screening A -4 C to 125 C 25 C High temperature K -4 C to 125 C -4 C to 125 C High and low temperature 4

5 PIN DESCRIPTION HSOP-8E HSOP-18 Top View Bottom View Top View Bottom View * HSOP-8E (R511Sxx1A / R511Sxx1B) Pin No. Symbol Description 1 V DD Supply Voltage pin 2 CE Chip Enable pin (Active "H") 3 GND GND pin 4 C D VD Release Delay Time Set pin 5 TW WDT Monitoring Time Set pin 6 SCK WDT Pulse Input pin 7 RESETB *2 Reset Output pin (Active "L"), Nch Open Drain Output type 8 V OUT VD Output pin *1 The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left open. *2 RESETB pin is required to pull up to a suitable voltage with an external capacitor. 5

6 HSOP-18 (R511Sxx2C / R511Sxx2D) Pin No. Symbol Description 1 V DD Supply Voltage pin 2 CE Chip Enable pin (Active "H") 3 NC No Connection 4 NC No Connection 5 GND GND pin 6 NC No Connection 7 NC No Connection 8 C D VD Release Delay Time Set pin 9 MR Manual Reset pin (Active "L") 1 TW WDT Monitoring Time Set pin 11 INH Inhibition pin (Active "L") 12 SCK WDT Pulse Input pin 13 WDO *2 WDT Output pin, Nch Open Drain Output type 14 D OUT * 3 Reset Output pin (Active "L"), Nch Open Drain Output type 15 SENSE VD Voltage SENSE pin 16 NC No Connection 17 NC No Connection 18 V OUT VR Output pin *1 The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left open. *2 WDO pin is required to pull up to a suitable voltage with an external capacitor. *3 DOUT pin is required to pull up to a suitable voltage with an external capacitor. 6

7 PIN EQUIVALENT CIRCUIT DIAGRAMS <V OUT pin> <CE pin> Driver CE VOUT <CD pin> Internal Supply Voltage <RESETB / D OUT pin> RESETB Driver C D Driver <SENSE pin> ( R511Sxx2C / R511Sxx2D) SENSE <MR pin> ( R511Sxx2C / R511Sxx2D) Internal Supply Voltage MR <SCK pin> Internal SupplyVoltage <TW pin> Internal Supply Voltage SCK TW Driver <INH pin> ( R511Sxx2C / R511Sxx2D) Internal Supply Voltage <WDO pin> ( R511Sxx2C / R511Sxx2D) WDO Driver INH 7

8 ABSOLUTE MAXIMUM RATINGS Symbol Item Ratings Unit Supply Voltage.3 to 5 V V DD Peak Voltage *1 6 V V CE C E Pin Input Voltage.3 to 5 V V OUT Output Voltage.3 to V IN V V CD C D Pin Output Voltage -.3 to 7. V V TW TW Pin Output Voltage -.3 to 7. V V RESETB Output Voltage RESETB Pin Output Voltage -.3 to 7. V V DOUT D OUT Pin Output Voltage -.3 to 7. V V WDO WDO Pin Output Voltage -.3 to 7. V V SCK SCK Pin Input Voltage -.3 to 7. V V INH INH Pin Input Voltage -.3 to 7. V Input Voltage V MR MR Pin Input Voltage -.3 to 7. V V SENSE SENSE Pin Input Voltage -.3 to 7. V PD Power Dissipation Ultra High Wattage Land (HSOP-8E) *2 Pattern 36 Power Dissipation JEDEC STD.51-7 Test Land (HSOP-18) *2 Pattern 3125 mw Tj Junction Temperature 4 to 15 C Tstg Storage Temperature 55 to 15 C *1 Within application time of 2ms *2 Refer to the section of Package Information for details. ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. RECOMMENDED OPERATING RATINGS Symbol Item Operating Ratings Unit V DD Input Voltage 3.5 to 36. V V CE C E Pin Input Voltage to 36. V V SCK SCKINH Pin Input Voltage to 5.5 V V INH INH Pin Input Voltage to 5.5 V V MR MR Pin Input Voltage to 5.5 V V SENSE SENSE Pin Input Voltage to 5.5 V Ta Operating Temperature Range 4 to 125 C RECOMMENDED OPERATING RATINGS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating ratings. The semiconductor devices cannot operate normally over the recommended operating ratings, even if when they are used over such ratings by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating ratings. 8

9 ELECTRICAL CHARACTERISTICS C IN = C OUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. R511Sxxxx-AE ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit I SS Supply Current I OUT = ma A Istandby I PD Power Consumption (on standby) CE Pull-downConstant Current V IN = 36V, V CE = V.1 2. A VCE = 5V.2.6 µa VCE = 36V µa V CEH CE Input Voltage "H" V V CEL CE Input Voltage "L" 1. V VR Part ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit V OUT Output Voltage I OUT = 1mA V V OUT / I OUT Load Regulation V IN = V SET + 2.V 1mA I OUT 5mA -2 3 mv V SET = V V DIF Dropout Voltage I OUT = 5mA V SET = V V SET = V V SET = V V OUT / V IN Line Regulation 3.5V V SET +.5V V IN 36V I OUT = 1mA.1.2 %/V I LIM Output Current Limit V IN = V SET + 3.V ma I SC Short current Limit V IN = 5V, V OUT = V ma T TSD T TSR R LOW Thermal Shutdown Temperature Thermal Shutdown Release Temperature V OUT Low Output Nch Tr.ON Resistance Junction Temperature C Junction Temperature C V CE = V, V OUT =.1V kω 9

10 C IN = C OUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. VD Part ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit -V DET Detector Threshold V OUT Set Detector Threshold: 1.6V to 5.5V x.982 x1.18 V V HYS Detector Threshold Hysteresis (-V DET ) x.1 (-V DET ) x.2 (-V DET ) x.3 tdelay Release Output Delay Time (Power-On Reset) C D =.22µF ms V RESETB RESETB Pull-up Voltage R511Sxx1A / R511Sxx1B 5.5 V V DOUT D OUT Pull-up Voltage R511Sxx2C / R511Sxx2D 5.5 V Nch. Output Current V IN = 3.5V, V RESETB =.1V R511Sxx1A / R511Sxx1B (RESETB Output Pin) ma Nch. Leakage Current R511Sxx1A / R511Sxx1B (RESETB Output Pin) V RESETB = 5.5V.3 µa Nch. Output Current R511Sxx2C / R511Sxx2D ma I OUTNRSTB I LEAKRSTB I OUTDOUT I LEAKDOUT (D OUT Output Pin) Nch. Leakage Current (D OUT Output Pin) V IN = 3.5V, V DOUT =.1V R511Sxx2C / R511Sxx2D V DOUT = 5.5V V.3 µa V MRH MR Input H V V MRL MR Input L.6 V MRW MR Input Pulse Width 2 µs RMR MR Pull-up Resistance kω R LCD C D Pin Discharge Nch Tr.ON Resistance V CE = V, V CD =.1V kω 1

11 C IN = C OUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. WDT Part R511S ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit t OW Open Window Time ms t CW Closed Window Time R511Sxx1B/ R511Sxx2D C TW = 1nF ms t OWL Long Open Window Time ms t IGN Ignoring Time C TW = 1nF ms t WD Monitoring Time R511Sxx1A/ R511Sxx2C C TW = 1nF ms t WR Reset Time C TW = 1nF ms V SCKH SCK Input H V V SCKL SCK Input L.65 V V INHH INH Input H V V INHL INH Input L.6 V R INH INH Pull-up Resistance kω t SCKWH SCK Minimum Input Pulse V Width H SCKL =.5, V SCKH = ns t SCKWL SCK Minimum Input Pulse V Width L SCKL =.5, V SCKH = ns V WDO WDO Pull-up Voltage 5.5 V Nch. Output Current V DD = 3.5V, V DS =.1V R511Sxx2C / R511Sxx2D (WDO Output Pin) ma Nch. Leakage Current R511Sxx2C / R511Sxx2D (WDO Output Pin) V WDO = 5.5V.3 µa R LTW C TW Discharge Nch Tr.ON Resistance V CE = V, V CTW =.1V kω I OUTNWDO I LEAKWDO All test items listed under Electrical Characteristics are done under the pulse load condition (Tj Ta = 25 C). 11

12 Product-specific Electrical Characteristics The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. VR Part ( Ta = 25 C) Product V OUT [V] V DIF [V] Name Min. Typ. Max. Typ. Max. R511S1xx R511S2xx R511S3xx R511S4xx R511S5xx R511S6xx R511S7xx R511S8xx R511S9xx R511S1xx R511S11xx R511S12xx VD Part ( Ta = 25 C) Product -V DET [V] V HYS [V] Name Min. Typ. Max. Min. Typ. Max. R511S1xx R511S2xx R511S3xx R511S4xx R511S5xx R511S6xx R511S7xx R511S8xx R511S9xx R511S1xx R511S11xx R511S12xx

13 R511Sxxxx-KE ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit I SS Supply Current I OUT = ma µa Istandby I PD Power Consumption (on standby) CE Pull-down Constant Current V IN = 36V,V CE = V.1 2. µa VCE = 5V.2.6 µa VCE = 36V µa V CEH CE Input Voltage "H" V V CEL CE Input Voltage "L" 1. V VR Part ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit V OUT Output Voltage I OUT =1mA V V OUT / I OUT Load Regulation V IN = V SET + 2.V 1mA I OUT 5mA -2 3 mv V SET = V V DIF Dropout Voltage I OUT = 5mA V SET = V V SET = V V SET = V V OUT / V IN Line Regulation 3.5V V SET +.5V V IN 36V I OUT = 1mA.1.2 %/V I LIM Output Current Limit V IN = V SET + 3.V ma I SC Short current Limit V IN = 5V, V OUT = V ma Thermal Shutdown Temperature Junction Temperature C Thermal Shutdown Release Temperature Junction Temperature C V OUT Low Output Nch Tr.ON Resistance V CE = V, V OUT =.1V kω T TSD T TSR R LOW 13

14 VD Part ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit V -V DET Detector Threshold OUT Set Detector Threshold: x.982 x1.18 V 1.6V to 5.5V Detector Threshold (-V V DET ) (-V DET ) (-V DET ) HYS V Hysteresis x.1 x.2 x.3 Release Output Delay tdelay C Time (Power-On Reset) D =.22µF ms V RESETB RESETB Pull-up Voltage R511Sxx1A / R511Sxx1B 5.5 V V DOUT D OUT Pull-up Voltage R511Sxx2C / R511Sxx2D 5.5 V Output Current R511Sxx1A / R511Sxx1B I OUTNRSTB ma (RESETB Output Pin) Nch, V DD = 3.5V, V DS =.1V Nch Leakage Current R511Sxx1A / R511Sxx1B I LEAKRSTB.3 µa (RESETB Output Pin) V RESETB = 5.5V Output Current R511Sxx2C / R511Sxx2D I OUTDOUT ma I LEAKDOUT.3 µa V MRH MR Input H V V MRL MR Input L.6 V MRW MR Input Pulse Width 2 µs RMR MR Pull-up Resistance kω C R D Pin Discharge V CE = V, V CD =.1V LCD kω Nch Tr.ON Resistance (D OUT Output Pin) Nch, V DD = 3.5V, V DS =.1V Nch Leakage Current R511Sxx2C / R511Sxx2D (D OUT Output Pin) V DOUT = 5.5V 14

15 WDT Part ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit t OW Open Window Time ms t CW Closed Window Time R511Sxx1B/ R511Sxx2D C TW = 1nF ms t OWL Long Open Window Time ms t IGN Ignoring Time C TW = 1nF ms t WD Monitoring Time R511Sxx1A/ R511Sxx2C C TW = 1nF ms t WR Reset Time C TW = 1nF ms V SCKH SCK Input H V V SCKL SCK Input L.65 V V INHH INH Input H V V INHL INH Input L.6 V R INH INH Pull-up Resistance kω t SCKWH SCK Minimum Input Pulse V Width H SCKL =.5, V SCKH =1.6 5 ns t SCKWL SCK Minimum Input Pulse V Width L SCKL =.5, V SCKH = ns V WDO WDO Pull-up Voltage 5.5 V Output Current V DD = 3.5V, V DS =.1V R511Sxx2C / R511Sxx2D (WDO Output Pin) ma Nch Leakage Current R511Sxx2C / R511Sxx2D (WDO Output Pin) V WDO = 5.5V.3 µa R LTW C TW Discharge Nch Tr.ON Resistance V CE = V, V CTW =.1V kω I OUTNWDO I LEAKWDO 15

16 Product-specific Electrical Characteristics VR Part ( 4 C Ta 125 C) Product V OUT [V] V DIF [V] Name Min. Typ. Max. Typ. Max. R511S1xx R511S2xx R511S3xx R511S4xx R511S5xx R511S6xx R511S7xx R511S8xx R511S9xx R511S1xx R511S11xx R511S12xx VD Part ( 4 C Ta 125 C) Product -V DET [V] V HYS [V] Name Min. Typ. Max. Min. Typ. Max. R511S1xx R511S2xx R511S3xx R511S4xx R511S5xx R511S6xx R511S7xx R511S8xx R511S9xx R511S1xx R511S11xx R511S12xx

17 TYPICAL APPLICATION CIRCUITS V IN Microprocessor V DD V OUT V CC C1 R511Sxx1A/B CE C2 R1 GND RESETB RESET C D C D SCK I/O TW C TW R511Sxx1A/B Typical Application V IN Microprocessor V DD V OUT V CC C1 R511Sxx2C/D CE SENSE C2 R1 GND DOUT RESET WDO C D C D SCK I/O INH MR TW C TW R511Sxx2C/D Typical Application 17

18 External Components Symbol C1 (C IN ) C2 (C OUT ) C TW C D R1 Description.1µF, Ceramic Capacitor.1µF, Ceramic Capacitor A capacitor corresponding to time setting for Watchdog Timer is required. Refer to Time Setting for WDT in Application Information for details. A capacitor corresponding to setting for Release Output Delay Time is required. Refer to Delay Operation and Release Output Delay Time (tdelay) in Application Information. A resistor is required to set with consideration of the output current and the leakage current. Refer to Electrical Characteristic for details. TECHNICAL NOTES Phase Compensation In the ICs, phase compensation is made for securing stable operation even if the load current is varied. For this purpose, use a capacitor C2 with 1 µf or more. If a tantalum capacitor is used, and its ESR (Equivalent Series Resistance) of C2 is large, the loop oscillation may result. Because of this, select C2 carefully considering its frequency characteristics. PCB Layout Make V DD and GND lines sufficient. If their impedance is too high, noise pickup or unstable operation may result. Connect.1 µf or more of the capacitor C1 between the V DD and GND, and as close as possible to the pins. In addition, connect the capacitor C2 between V OUT and GND, and as close as possible to the pins. 18

19 Prohibited Area for Fluctuations in Power Supply Voltage Please take note that miss-detection or miss-release might be invited when changing an input voltage abruptly in the following prohibited area. 15. Input Voltage peak Vp-p (V) Prohibited Area V IN Vp-p tf Input Voltage Falling Time tf (μs) GND Prohibited Area of Fluctuation at Falling of V IN 15 Prohibited Area tr Input Voltage peak Vp-p (V) 1 5 V IN Vp-p Input Voltage Rising Time tr (μs) GND Prohibited Area of Fluctuation at Rising of V IN 19

20 TYPICAL APPLICATION FOR IC CHIP BREAKDOWN PREVENTION V IN Microprocessor C1 V DD V OUT R511Sxx1A/B CE C2 D1 R1 V CC GND RESETB RESET C D C D SCK I/O TW C TW C1 = Ceramic.1μF C2 = Ceramic.1μF R511Sxxxx Typical Application When a sudden surge of electrical current travels along the V OUT pin and GND due to a short-circuit, electrical resonance of a circuit involving an output capacitor (C2) and a short circuit inductor generates a negative voltage and may damage the device or the load devices. Connecting a schottky diode (D1) between the V OUT pin and GND has the effect of preventing damage to them. 2

21 TIMING CHART R511Sxx1A / R511Sxx1B Voltage Detector V IN +V DET V OUT -V DET V CD V TCD tdelay (2) tdelay V RESETB (1) (3) (4) (3) R511Sxx1A / R511Sxx1B VD Timing Chart (1) When the V OUT pin voltage (V OUT ) becomes more than the release voltage (+V DET ), the RESETB pin voltage (V RESETB ) becomes H after the release output delay time (tdelay). (2) When the detect output delay time is less than 3 µs (Typ.) even if V OUT becomes lower than the detector threshold (-V DET ), the voltage detector (VD) does not go into the detecting state. (3) When V OUT becomes lower than -V DET, V RESETB becomes "L" after the detect output delay time (Typ.3µs) and the VD goes into the detecting state. (4) When V OUT becomes more than +V DET. V RESETB becomes "H" after the release output delay time. (V TCD = Typ.1V) 21

22 R511Sxx2C / R511Sxx2D Voltage Detector V IN +V DET V SENSE -V DET (2) V MR V CD V TCD tdelay tdelay tdelay V DOUT (1) (3) (4) (5) (6) (3) R511Sxx2C / R511Sxx2D VD Timing Chart (1) When the SENSE pin voltage (V SENSE ) becomes more than the release voltage (+V DET ), the D OUT pin voltage (V DOUT ) becomes H after the release output delay time (tdelay). (2) When the detect output delay time is 3µs (Typ.) or less even if V SENSE becomes lower than the detector threshold (-V DET ), the voltage detector (VD) does not go into the detecting state. (3) When V SENSE becomes lower than -V DET, V DOUT becomes "L" after the detect output delay time (Typ. 3µs) and the VD goes into the detecting state. (4) When V SENSE becomes more than +V DET, V DOUT becomes H after the release output delay time. (V TCD = Typ.1V) (5) When the MR pin voltage (V MR ) becomes L, V DOUT is fixed to "L" after the detect output delay time (Typ. 3µs). (6) When V MR becomes L to H, V DOUT becomes H after the release output delay time. 22

23 R511Sxx1A Watchdog Timer (Normal Type) V IN V OUT +V DET -V DET V RESETB V TW TWVREFH tdelay t IGN t WD t W t IGN <t WD t WD t WR t IGN TWVREFL IGN WD RST IGN WD WD RST IGN WD (1) (3) (4) (5) V SCK (2) (6) R511Sxx1A WDT Timing Chart (1) When the V OUT pin voltage (V OUT ) becomes more than the release voltage (+V DET ), the RESETB pin voltage (V RESETB ) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (V TW ) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has three states: Ignoring, Reset, and Monitoring. In each state, the TW pin is charged from V or TWFREFL (Typ..8V). (2) After the WDT starts, the WDT is in an ignoring state until V TW is charged up to TWVREFH (Typ.2V). So, a pulse to the SCK pin is ignored during the ignoring state. (3) When charging V TW up to TWVREFH has completed, the TW pin starts discharging and the WDT goes into a monitoring state. (4) When a pulse is not sent to the SCK pin before V TW reaches TWVREFH during the monitoring state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, V RESETB becomes L. (5) When V TW is charged up to TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into the ignoring state. (6) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the monitoring state, the TW pin start discharging and the WDT goes into the next open window state. 23

24 R511Sxx1B Watchdog Timer (Window Type) V IN V OUT +V DET -V DET V RESETB V TW TWVREF tdelay t IGN <t OW <t CW t WR t IGN <t OW t CW t OW t WR t IGN TWVREFL IGN LOW CW RST IGN LOW CW OW RST IGN LOW (1) (3) (6) (7) (8) V SCK (2) (4) (5) R511Sxx1B WDT Timing Chart (1) When the V OUT pin voltage (V OUT ) becomes more than the release voltage (+V DET ), the RESETB pin voltage (V RESETB ) becomes H after the release output delay time (tdelaly) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (V TW ) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has four states: Ignoring, Reset, Open Window, and Closed Window. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). (2) After WDT starts, the WDT is in an ignoring state until V TW is charged up to TWVREFH (Typ.2V). So, a pulse to the SCK pin is ignored during the ignoring state. (3) When V TW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into an open window state. This open window state is four times longer than the normal open window state. (4) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a closed window state. (5) When a pulse is sent to the SCK pin before V TW reaches TWVREF during the closed window state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, V RESETB becomes L. (6) When V TW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into the ignoring state. 24

25 (7) When a pulse is not sent to the SCK pin before V TW reaches TWVREFH during the closed window state, the TW pin starts discharging and the WDT goes into the open window state. (8) When a pulse is not sent to the SCK pin before V TW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into the reset state. R511Sxx2C Watchdog Timer (Normal Type) V IN +V DET V SENSE -V DET V INH V DOUT V WDO V TW TWVREFH tdelay t IGN t WD t WR t IGN <t WD t WD t IGN TWVREFL IGN WD RST IGN WD WD RST IGN WD (1) (3) (4) (5) (7) (8) V SCK (2) (6) R511Sxx2C WDT Timing Chart 25

26 (1) When the SENSE pin voltage (V SENSE ) becomes more than the release voltage (+V DET ), the D OUT pin voltage (V DOUT ) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (V TW ) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has three states: Ignoring, Reset, and Monitoring. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). (2) After the WDT starts, the WDT is in an ignoring state until V TW is charged up to TWVREFH. So, a pulse to the SCK pin is ignored during the ignoring state. (3) When V TW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into a monitoring state. (4) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the monitoring state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, the WDO pin voltage (V WDO ) becomes L. (5) When V TW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into an ignoring state. (6) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the monitoring, the TW pin starts discharging and the WDT goes into the next monitoring state. (7) The WDT stops monitoring by setting the INH pin voltage (V INH ) to L. Then, V WDO is fixed to H and V TW is fixed to L. (8) When changed V INH from L to H, the WDT goes into the ignoring state and restarts monitoring. 26

27 R511Sxx2D Watchdog Timer (Window Type) V IN V SENSE +V DET -V DET V INH V DOUT V WDO V TW TWVREF tdelay t IGN <t OW <t CW t WR t IGN <t OW t CW t OW t IGN TWVREFL IGN LOW CW RST IGN LOW CW OW RST IGN LOW (1) (3) (6) (7) (8)(9) (1) V SCK (2) (4) (5) R511Sxx2D WDT Timing Chart (1) When the V OUT pin voltage (V OUT ) becomes more than the release voltage (+V DET ), the D OUT pin voltage (V DOUT ) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (V TW ) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has four states: Ignoring, Reset, Open Window, and Closed Window. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). (2) After WDT starts, the WDT is in an ignoring state until V TW is charged up to TWVREFH. So, a pulse to the SCK pin is ignored during the ignoring state. 27

28 (3) When V TW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into an open window state. This open window state is four times longer than the normal open window state. (4) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a closed window state. (5) When a pulse is sent to the SCK pin before V TW reaches TWVREFH during the close window state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, V DOUT becomes L. (6) When V TW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into an ignoring state. (7) When a pulse is not sent to the SCK pin before V TW reaches TWVREFH during a closed window state, the TW pin starts discharging and the WDT goes into an open window state. (8) When a pulse is not sent to the SCK pin before V TW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a reset state. (9) The WDT stops monitoring by setting the INH pin voltage (V INH ) to L. Then, V WDO is fixed to H and V TW is fixed to L. (1) When changed V INH from L to H. the WDT goes into the ignoring state and restarts monitoring. 28

29 APPLICATION INFORMATION Delay Operation and Released Output Delay Time (tdelay) V OUT / SENSE Pin Released Voltage (+V DET ) Detector Voltage (-V DET ) C D Pin Voltage C D Pin Threshold Voltage (V TCD ) GND RESETB / D OUT Pin Release Output Delay Time (tdelay) GND Detect Output Delay Time (t PHL ) Released Output Delay Timing Diagram When the operating voltage higher than the released voltage is applied to V OUT pin (R511Sxx1A/R511Sxx1B) or SENSE pin (R511Sxx2C/R511Sxx2D), charge to an external capacitor starts, then C D pin voltage (V CD ) increases. RESETB pin (R511Sxx1A/R511Sxx1B) or D OUT pin (R511Sxx2C/R511Sxx2D) maintains the released output until V CD reaches the threshold voltage of the release output delay pin (V TCD ). And when V CD is over V TCD, RESETB pin or D OUT pin is inverted from L to H. That is, the charged external capacitor starts discharging. When the operating voltage lower than the detector threshold is applied to V DD pin, the detect output delay time, which is the time until the output voltage is inverted from H to L, remains constant independent of the external capacitor. V OUT / SENSE -V DET 2.V RESETB / D OUT 1.5V GND 5.V 2.5V GND t PHL tdelay Released Output Delay Time Released Output Delay Time (tdelay) indicates the time between the instance when V OUT pin (R511Sxx1A / R511Sxx1B) or SENSE pin (R511Sxx2C / R511Sxx2D) shifts from 1.5 V to V DET + 2. V by the application of a pulse voltage and the instance when the output voltage reaches 2.5 V after pulled up RESETB pin (R511Sxx1A / R511Sxx1B) or D OUT pin (R511Sxx2C/ R511Sxx2D) to 5. V with a resistor of 1 kω. 29

30 This is given by the expression tdelay (s) 1.1 C D (F) / ( ), where C D (F) represents capacitance of the external capacitor. If V OUT / SENSE pin goes up at a mild pace of.1v/s or less, connect a capacitor of 2 pf or more to C D pin. WDT State Transition Diagram Input Clock Time Out (1)R511SxxxA/C V OUT<Detector Threshold(R511Sxx1A) SENSE<Detector Threshold(R511Sxx2C) or INH=Low(R511Sxx2C) INH=High or OPEN and V OUT >Released Output Voltage(R511Sxx1A) SENSE>Released Output Voltage(R511Sxx2C) (2)R511SxxxB/D V OUT<Detector Threshold(R511Sxx1B) SENSE<Detector Threshold(R511Sxx2D) or INH=Low(R511Sxx2D) INH=High or OPEN and V OUT >Released Output Voltage(R511Sxx1B) SENSE>Released Output Voltage(R511Sxx2D) Ignoring Ignoring Monitoring Long Open Window Reset Open Window Closed Window Reset Time Setting for Watchdog Timer The following time of WDT is dependent on a capacitor connecting to the TW pin. Relationship between the value of capacitor and time can be expressed by the following equations. t OW (s) = 1.8 x C(F) / (1. x 1-6 ) t CW (s) = 1.8 x C(F) / (1. x 1-6 ) t OWL (s) = 1.8 x C(F) / (.25 x 1-6 ) t GN (s) = 1.8 x C(F) / (1. x 1-6 ) t WD (s) = 1.8 x C(F) / (1. x 1-6 ) t WR (s) = 1.9 x C(F) / (2. x 1-6 ) 3

31 Inrush Current Prevention at Rising Characteristics R511S has the inrush current preventing circuit to control the inrush current within about 4mA limited. This circuit works during the rising periods. Therefore, the load current must be increased after rising up the output voltage (at typ.1us after being out of the inrush current limited condition) by the sequence control. When the load current is increased during the rising periods, the inrush current must be controlled within 25mA. VSET VOUT 4mA (TYP) 1us (TYP) IOUT IRUSH IOUT<25mA 25mA<IOUT Likewise, on the thermal shutdown and the foldback characteristic, the inrush current preventing circuit works when the output voltage re-rises after the output voltage fall down to a guideline (VSET x.4) or less. VOUT VSET.4 IOUT Voltage Setting in R511Sxx1A / R511Sxx1B In R511Sxx1A / R511Sxx1B, VD detects the drop of the VR output voltage (V OUT ). When the VD release voltage (+V DET ) is set to a voltage above the VR output voltage, the reset signal of VD is not released even if VD monitors the VR output voltage returns to the normal value after detecting the drop of VR. To prevent this issue, the following condition is required between V OUT and +V DET. (VR Set Output Voltage) x.985-3mv > (VD Set Detector Threshold) x 1.18 x 1.3 When using a device with the above conditions of V OUT and +V DET, careful consideration must be given to the system operation before use. 31

32 Manual Reset (MR) Function (R511Sxx2C, R511Sxx2D) Setting the MR pin to L forcefully sets D OUT to L. The maximum value of the delay time (t MR ), which is until D OUT outputs L, is 1µs as an index of the performance. The MR pin is pulled-up by an internal resistor (Typ.11kΩ). Current is passed to the MR pin when the voltage of MR > V DD. But, this current has no effect to the operation because the current is limited with a pull-up resistor. When setting the MR pin from L to H, D OUT is changed from L to H after the released output delay time and the WDT starts from the ignoring state. When the MR pin is L, the WDO pin outputs H. SENSE Function (R511Sxx2C, R511Sxx2D) In R511Sxx2C / R511Sxx2D, the internal voltage detector monitors the input voltage to the SENSE pin. To measure the proper detector threshold, setting of V DD 3.5V is required. Inhibition (INH) Function (R511Sxx2C, R511Sxx2D) In R511Sxx2C / R511Sxx2D, setting the INH pin to L stops the WDT pulse monitoring function and the WDO pin is fixed to H. The INH pin is pulled up with an internal resistor (Typ.11kΩ). 32

33 PACKAGE INFORMATION Power Dissipation (HSOP-8E) Power Dissipation (P D ) depends on conditions of mounting on board. This specification is based on the measurement at the condition below: Measurement conditions Environment Board Material Board Dimensions Copper Ratio Through - hole Ultra High Wattage Land Pattern Mounting on board (Wind velocity m/s) Glass cloth epoxy plastic (4 layers) 76.2mm x 114.3mm x.8mm Top side, Back side : 5mm square, Approx.95% 2nd, 3rd Layer: 5mm square, Approx. 1%.4mm x 21pcs Measurement Results Power Dissipation Thermal Resistance (Ta = 25 C, Tjmax = 15 C) Ultra High Wattage land pattern 36mW ja = (15-25 C)/3.6W = 35 C/W jc = 1 C/W Power Dissipation PD (W) On Board (Ultra High Wattage Land Pattern) Ambient Temperature ( Power Dissipation Measurent Board Pattern IC Mount Area Unit : mm 33

34 Package Dimension (HSOP-8E) 8 5 (.3) 2.9±.5 4.4±.2 6.2±.3 (.3) 2.7±.5 S 1.695TYP 4 5.2±.3.1 S 1.5±.1 ~ ±.2.4±.1 DETAIL A M *) The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating. DETAIL A.5±.5.8±.5 (Unit : mm) HSOP-8E Package Dimensions Mark Specification (HSOP-8E) : Product Code Refer to Mark Specification Table 789: Lot Number Alphanumeric Serial Number HSOP-8E Markings 34

35 R511S Mark Specification Table (HSOP-8E) R511Sxx1A/B Product Name Product Name V SET / -V SET VR VD R511S11A R S 7 A R511S11B R S 7 N 5.V 4.6V R511S21A R S 7 B R511S21B RS7P 1.8V 1.6V R511S31A R S 7 C R511S31B RS7R 5.V 4.5V R511S41A R S 7 D R511S41B RS7S 5.V 4.4V R511S51A R S 7 E R511S51B RS7T 5.V 4.3V R511S61A R S 7 F R511S61B RS7U 5.V 4.2V R511S71A RS7G R511S71B RS7V 5.V 3.7V R511S81A R S 7 H R511S81B RS7W 3.3V 3.V R511S91A RS7J R511S91B RS7X 3.3V 2.9V R511S11A R S 7 K R511S11B RS7Y 3.3V 2.8V R511S111A R S 7 L R511S111B RS7Z 3.3V 2.7V R511S121A RS7M R511S121B RS8A 5.V 4.1V 35

36 Power Dissipation (HSOP-18) Power Dissipation (P D ) depends on conditions of mounting on board. This specification is based on the measurement at the condition below: Measurement Conditions JEDEC STD.51-7 Test Land Pattern Environment Mounting on Board (Wind velocity=m/s) Board Material Glass cloth epoxy plastic (4 layers) Board Dimensions 76.2 mm mm 1.6 mm Copper Ratio Top side, Back side : 6mm square, Approx.1% 2nd, 3 rd Layer: 74.2mm square, Approx. 1% Through-holes.85mm x 44pcs Measurement Result: Power Dissipation Thermal Resistance (Ta = 25 C, Tjmax = 15 C) JEDEC STD.51-7 Test Land Pattern 3125 mw Θja = (15 25 C) / W = 4 C/W Θjc = 9 C/W Power Dissipation PD (mw) Power Dissipation On Board (JEDEC STD.51-7 Test Land Pattern) Ambient Temperature ( C) Power Dissipation Measurement Board Pattern IC Mount Area (Unit : mm) Measurement 基板レイアウト Board Pattern IC Mount Area (Unit : mm) IC 実装位置 ( 単位 : mm) 36

37 Package Dimensions (HSOP-18) 18 1 (.3) 2.9±.5 4.4±.2 6.2±.3 (.3) 2.7±.5 S 1.6TYP 9 5.2±.3.1 S 1.5±.1 ~1.5.4±.2.2±.1 DETAIL A.12 M *) The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating. DETAIL A.5±.5.8±.5 (Unit : mm) HSOP-18 Package Dimensions Mark Specification (HSOP-18) :Product Code Refer to Mark Specification Table 789:Lot Number Alphanumeric Serial Number HSOP-18 Markings 37

38 R511S Mark Specification Table (HSOP-18) R511Sxx2C/D Product Name Product Name V SET / -V SET VR VD R511S12C R S 1 2 A R511S12D R S 1 2 N 5.V 4.6V R511S22C R S 1 2 B R511S22D R S 1 2 P 1.8V 1.6V R511S32C R S 1 2 C R511S32D R S 1 2 R 5.V 4.5V R511S42C R S 1 2 D R511S42D R S 1 2 S 5.V 4.4V R511S52C RS12E R511S52D RS12T 5.V 4.3V R511S62C RS12F R511S62D RS12U 5.V 4.2V R511S72C R S 1 2 G R511S72D R S 1 2 V 5.V 3.7V R511S82C RS12H R511S82D RS12W 3.3V 3.V R511S92C R S 1 2 J R511S92D R S 1 2 X 3.3V 2.9V R511S12C R S 1 2 K R511S12D R S 1 2 Y 3.3V 2.8V R511S112C RS12L R511S112D RS12Z 3.3V 2.7V R511S122C R S 1 2 M R511S122D R S 1 3 A 5.V 4.1V 38

39 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. R511S 1) Power Consumption vs. Input Voltage (Ta = 25 C) VR=1.8V VR=3.3V Supply Current IIN (μa) Input Voltage V IN (V) Supply Current IIN (μa) Input Voltage V IN (V) Supply Current IIN (μa) VR=5.V Input Voltage V IN (V) 2) CE Pin Current vs. CE Pin Voltage (Ta = 25 C, V IN =14V) VR=5.V CE Crrent ICE (μa) CE Input Voltage V CE (V) 39

40 3) GND Pin Current vs. Output Current (Ta = 25 C) I GND (μa) Output Current I OUT (ma) 4) Output Voltage vs. Output Current (Ta = 25 C) VR=1.8V VR=3.3V Output Voltage VOUT (V) VIN=3.5V VIN=4.8V Output Current I OUT (ma) Output Voltage VOUT (V) VIN=3.8V VIN=4.3V VIN=6.3V Output Current I OUT (ma) VR=5.V Output Voltage VOUT (V) VIN=5.5V VIN=6.V VIN=8.V Output Current I OUT (ma) 4

41 5) Output Voltage vs. Input Voltage (Ta = 25 C) VR=1.8V VR=3.3V Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Input Voltage V IN (V) Input Voltage V IN (V) VR=5.V Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Input Voltage V IN (V) 6) Output Voltage vs. Temperature (V IN =14V, I OUT =1mA) VR=1.8V VR=3.3V Output Voltage V OUT (V) Output Voltage V OUT (V) Ta ( ) Ta ( ) 41

42 VR=5.V 5.1 Output Voltage V OUT (V) Ta ( ) 7) Dropout Voltage vs. Output Current VR=1.8V Dropout Voltage VDIF (mv) C 6 25 C C 2 (VIN=3.5V) Output Current I OUT (ma) Dropout Voltage VDIF (mv) VR=3.3V C 8 25 C C 6 (VIN=3.5V) Output Current I OUT (ma) VR=5.V Dropout Voltage VDIF (mv) C 25 C 125 C Output Current I OUT (ma) 42

43 8) Dropout Voltage vs. Output Voltage (Ta=25 ) Dropout Voltage VDIF (mv) IOUT=1mA IOUT=1mA IOUT=1mA IOUT=5mA (VIN=3.5V) Output Voltage V OUT (V) 9) リ Ripple Rejection vs. Input Voltage (Ta=25, Ripple =.2 Vpp) VR=1.8V, I OUT =1mA VR=1.8V, I OUT =3mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 1mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 3mA Input Voltage VIN (V) Input Voltage VIN (V) VR=3.3V, I OUT =1mA VR=3.3V, I OUT =3mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 1mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 3mA Input Voltage VIN (V) Input Voltage VIN (V) 43

44 VR=5.V, I OUT =1mA VR=5.V, I OUT =3mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 1mA Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz I OUT = 3mA Input Voltage VIN (V) Input Voltage VIN (V) 1) Ripple Rejection vs. Frequency (Ta=25, Ripple=.2 Vpp) VR=1.8V VR=3.3V 1 9 V IN = 4.V 1 9 V IN = 5.3V 8 8 Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Frequency [khz] Frequency [khz] VR=5.V 1 9 V IN = 7.V Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Frequency [khz] 44

45 11) Input Transient Respon (Ta=25 C) VR=1.8V, C OUT =.1μF VR=1.8V, C OUT =1μF C OUT =.1μF 5. C OUT = 1μF 5. Output Voltage VOUT (V) Input Voltage 3.5 <=> 4.5V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 3.5 <=> 4.5V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) VR=3.3V, C OUT =.1μF VR=3.3V, C OUT =1μF C OUT =.1μF 5.8 C OUT = 1μF 5.8 Output Voltage VOUT (V) Input Voltage 4.3 <=> 5.3V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 4.3 <=> 5.3V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) VR=5.V, C OUT =.1μF VR=5.V, C OUT =1μF C OUT =.1μF 7.5 C OUT = 1μF 7.5 Output Voltage VOUT (V) Input Voltage 6. <=> 7.V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 6. <=> 7.V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) 45

46 12) Load Transient Response (Ta=25 C) VR=1.8V, C OUT =.1μF VR=1.8V, C OUT =1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage.8 Output Voltage Time (μs) Time (ms) VR=3.3V, C OUT =.1μF VR=3.3V, C OUT =1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage 2.3 Output Voltage Time (μs) Time (ms) VR=5.V, C OUT =.1μF VR=5.V, C OUT =1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage 4. Output Voltage Time (μs) Time (ms) 46

47 13) CE Transient Response (Ta=25, V IN =14V, I OUT =1mA, C OUT =.1μ~47μF) CE Input Voltage VCE (V) Output Voltage VOUT (V) VR=1.8V, CE at rising Output Voltage Inrush Crurent Time (ms) CE Input Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) VR=1.8V, CE at falling CE Input Voltage Output Voltage Time (ms) VCE.1uF 1.uF 4.7uF 1uF 47uF VR=3.3V, CE at rising VR=3.3V, CE at falling CE Input Voltage V CE (V) Output Voltage V OUT (V) Output Voltage CE Input Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) CE Input Voltage Output Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Inrush Crurent Time (ms) Time (ms) VR=5.V, CE at rising VR=5.V, CE at falling CE Input Voltage V CE (V) Output Voltage V OUT (V) Output Voltage CE Input Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) CE Input Voltage Output Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Inrush Crurent Time (ms) Time (ms) 47

48 14) Detector Threshold vs. Temperature VD=1.6V VD=3.V Detector Threshold V DET (V) Detector Threshold V DET (V) Ta ( ) Ta ( ) VD=4.6V Detector Threshold V DET (V) Ta ( ) 15) D OUT Pin Voltage vs. SENSE Pin Input Voltage (D OUT pulled-up to 5V with 1kΩ) VD=1.6V VD=3.V Output Voltage DOUT (V) Output Voltage D OUT (V) Input Voltage V SENSE (V) Input Voltage V SENSE (V) 48

49 VD=4.6V 6 5 Output Voltage D OUT (V) Input Voltage V SENSE (V) 16) Release Output Delay Time vs. Input Voltage 17) Release Output Delay Time vs. Temperature Output Delay Time for Release t PLH (ms) C D =.22μF Output Delay Time for Reset tdelay (ms) 26 C D =.22μF Input Voltage V IN (V) Ta ( ) 18) Detect Output Delay Time vs. Temperature 19) Release Output Delay Time External Capacitor and Detect Delay Time vs. for C D Pin Output Delay Time for Release tdelay (μs) Ta ( ) Output Delay Time for Release [tdelay (ms)] Output Delay Time for Reset [tdelay (ms)] tdelay t PHL External Capacitance C D (nf) 49

50 2) WDT t WD / t OW / t CW / t IGN vs. Input Voltage Monitoring Time t WD / Open Window Time t OW / Closed Window Time t CW / Ignore Time t IGN (ms) t WD / t OW / t CW / t IGN Input Voltage V IN (V) C TW = 1nF 21) Reset Time vs. Input Voltage 22) Long Open Window Time vs. Input Voltage R511SxxxB/D Reset Time twr (ms) C TW = 1nF Input Voltage V IN (V) Long Term Open Window Time towl (ms) 82 C TW = 1nF Input Voltage V IN (V) 23) WDT t WD / t OW / t CW / t IGN vs. Temperature Monitoring Time twd / Open Window Time tow / Closed Window Time tcw / Ignore Time tign (ms) 2 C TW = 1nF 19 t WD / t OW / t CW / t IGN Ta ( ) 5

51 24) Reset Time vs. Temperature 25) Long Open Window Time vs. Temperature Reset Time twr (ms) 1.4 C 1.2 TW = 1nF Ta ( ) Long Term Open Window Time t OWL (ms) R511SxxxB/D 82 C TW = 1nF Ta ( ) 26) WDT t WD / t OW / t CW / t IGN /t OWL / t RST Vs. External Capacitor for C TW Pin 1 1 t OWL Window Time (ms) t WD / t OW / t CW / t IGN t RST External Capacitance C TW (nf) 27) Nch. Driver Output Current vs. V DS 28) Nch. Driver Output Current vs. Input Voltage Nch Driver Output Current (ma) ( I OUTRSTB / I OUTDOUT / I OUTWDO ) V IN =5., 6.V V DS (V) (V RESETB / V DOUT / V WDO ) VIN=3.5V VIN=4.V VIN=5.V VIN=6.V Nch Driver Output Current (ma) ( IOUTRSTB / IOUTDOUT / IOUTWDO ) V DS (V RESETB / V DOUT / V WDO ) =.1V Input Voltage V IN (V) -4 C 25 C 15 C 125 C 51

52 ESR vs. Output Current The IC is recommended to use a ceramic type capacitor, but the IC can be used other capacitors of the lower ESR type. The relation between the output current (I OUT ) and the ESR of output capacitor is shown below. C1 V DD V OUT CE R511x GND C2 I OUT ESR C1 = Ceramic.1 μf, C2 = Ceramic.1 μf Measurement conditions: Frequency Band: 1 Hz to 2 MHz Measurement Temperature: 4 C to 125 C Hatched area: Noise level is 4 μv (average) or below Ceramic Capacitor: C1 = C2 = Ceramic.1 μf 1 VR=1.8V V IN = 3.5V to 36V 1 VR=3.3V V IN = 3.5V to 36V Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Output Current I OUT (ma) VR=5.V V IN = 5.V to 36V Output Current I OUT (ma) Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Output Current I OUT (ma) 52