36V System Power Supply with Watchdog Timer for Automotive Applications

Transcription

1 Series AEC-Q1 Grade 1 Compliant 36V System Power Supply with Watchdog Timer for Automotive Applications OUTLINE R5111S is the system power supply and supervisor IC based on the high-voltage CMOS process technology, and has high accuracy and ultra low supply current voltage. R5111S consists of a voltage regulator (VR), a voltage detector (VD), and a normal / window type of watchdog timer (WDT) in a chip, and can provide three functions of the system power supply, the supply voltage supervisor, and the supervision of system s misoperation. Voltage Regulator allows the output current of 3mA. And, VR has the inrush current protection circuit for rising pulse (Typ.25mA or less). Voltage Detector outputs a reset signal when a reduction of supply voltage (SENSE / VOUT) is detected, and the reset signal is used as system reset. The detection voltage is internally fixed in an IC. And, the delay time is adjustable with an external capacitor because VD has the built-in release delay circuit (the power-on reset circuit). When the supply voltage is higher than the release output voltage, VD maintains the reset state during the delay time. The output type of RESETB and DOUT are Nch open-drain. In addition, R5111Sxx2C and R5111Sxx2D (Detector with SENSE pin) have a manual reset (MR) pin. Watchdog Timer detects the microprocessor output pulse. In addition to the normal type of WDT (R5111Sxx1A / R5111Sxx2C) that outputs a reset signal when the detected pulse period is longer than normal, R5111S supports the window type of WDT (R5111Sxx1B / R5111Sxx2D) that outputs a reset signal when the detected pulse period is shorter or longer. RESETB outputs the reset signal when using R5111Sxx1A / R5111Sxx1B, and the WDO pin outputs L as the reset signal when using R5111Sxx2C / R5111Sxx2D. The output type of WDO is Nch open-drain. In addition, R5111Sxx2C and R5111Sxx2D have an inhibiting (INH) pin to stop the watchdog timer s monitoring function. The time out period of Watchdog Timer is also adjustable with an external capacitor. R5111S supports the packages of HSOP-8E and HSOP-18. FEATURES Operating Voltage Range (Maximum Rating) 3.5V to 36.V (5.V) Operating Temperature Range 4 C to 125 C Supply Current Typ. 25µA Supply Current (On standby) Typ..1µA <Voltage Regulator (VR)> Output Voltage Range 1.8V to 5.V Dropout Voltage Typ..3V (VOUT = 5.V, 3mA) Output Voltage Accuracy ±1.5% ( 4 C Ta 125 C) Output Voltage Temperature Coefficient Typ. ±1ppm/ C 1

2 Built-in Short Current Limit Circuit Typ. 11mA Built-in Overcurrent Protection Circuit Min. 3mA Built-in Thermal Shutdown Circuit Typ.165 C Recommended Ceramic Capacitor.1µF or more <Voltage Detector (VD)> Detector Threshold Range 1.6V ~ 5.5V Detector Threshold Accuracy ±1.8% ( 4 C Ta 125 C) Release Delay Accuracy ±2% ( 4 C Ta 125 C) Release Delay Time Typ. 242ms (CD =.22 µf) Delay Time is adjustable with an external capacitor. <Watchdog Timer (WDT)> Open Window Accuracy ±2% ( 4 C Ta 125 C) Open Window Time Typ.18ms (CTW = 1nF) Closed Window Time Typ.18ms (CTW = 1nF) Long Open Window Time Typ.72ms (CTW = 1nF) Ignoring Time Typ.18ms (CTW = 1nF) Monitoring Time Typ.18ms (CTW = 1nF) Reset Time Typ.9.5ms (CTW = 1nF) Each time is adjustable with an external capacitor. APPLICATIONS Power source for car accessories including car audio equipment, car navigation system, and ETC system. Power source for control units including EV inverter and charge control. 2

3 BLOCK DIAGRAMS R5111Sxx1A / R5111Sxx1B VDD CE Thermal shut down ON/OFF Circuit VOUT Internal Supply Voltage Current Limit GND VOUT CD RESETB SCK CLOCK DETECTOR WATCHDOG TIMER (R5111xx1A) WINDOW WATCHDOG TIMER (R5111xx1B) TW R5111Sxx2C / R5111Sxx2D VDD CE Thermal shut down ON/OFF Circuit VOUT Internal Supply Voltage Current Limit GND MR CD SENSE DOUT INH TW SCK CLOCK DETECTOR WATCHDOG TIMER (R5111Sxx2C) WINDOW WATCHDOG TIMER (R5111Sxx2D) WDO 3

4 SELECTION GUIDE R5111S user selectable options (Watchdog Timer type, Detector type, and additional functions with using MR / INH / WDO pins) are as follows: Product Name Package Quantity per Reel Pb Free Halogen Free R5111Sxx1 -E2-#E HSOP-8E 1, pcs Yes Yes R5111Sxx2 -E2-#E HSOP-18 1, pcs Yes Yes xx: Specify the set output voltage (VSET) and the set detector threshold (-VSET) by using serial numbers starting from 1. Refer to Mark Specification Table for details. : Detector Watchdog Timer MR / INH / RESETB/ Package Monitoring Voltage Type WDO pins D OUT pins A VOUT HSOP-8E Normal RESETB B VOUT HSOP-8E Window RESETB C SENSE HSOP-18 Normal Yes DOUT D SENSE HSOP-18 Window Yes DOUT #: Specify the automotive class code. Operating Guaranteed Specs Temperature Range Temperature Range Screening A -4 C to 125 C 25 C High temperature K -4 C to 125 C -4 C to 125 C High and low temperature 4

5 PIN DESCRIPTION Top View HSOP-8E Bottom View Top View HSOP-18 Bottom View * 1 * HSOP-8E (R5111Sxx1A / R5111Sxx1B) Pin No. Symbol Description 1 VDD Supply Voltage pin 2 CE Chip Enable pin (Active "H") 3 GND GND pin 4 CD VD Release Delay Time Set pin 5 TW WDT Monitoring Time Set pin 6 SCK WDT Pulse Input pin 7 RESETB *2 Reset Output pin (Active "L"), Nch Open Drain Output type 8 VOUT VD Output pin *1 The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left open. *2 RESETB pin is required to pull up to a suitable voltage with an external capacitor. 5

6 HSOP-18 (R5111Sxx2C / R5111Sxx2D) Pin No. Symbol Description 1 VDD Supply Voltage pin 2 CE Chip Enable pin (Active "H") 3 NC No Connection 4 NC No Connection 5 GND GND pin 6 NC No Connection 7 NC No Connection 8 CD VD Release Delay Time Set pin 9 MR Manual Reset pin (Active "L") 1 TW WDT Monitoring Time Set pin 11 INH Inhibition pin (Active "L") 12 SCK WDT Pulse Input pin 13 WDO *2 WDT Output pin, Nch Open Drain Output type 14 DOUT* 3 Reset Output pin (Active "L"), Nch Open Drain Output type 15 SENSE VD Voltage SENSE pin 16 NC No Connection 17 NC No Connection 18 VOUT VR Output pin *1 The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left open. *2 WDO pin is required to pull up to a suitable voltage with an external capacitor. *3 DOUT pin is required to pull up to a suitable voltage with an external capacitor. 6

7 PIN EQUIVALENT CIRCUIT DIAGRAMS <VOUT Pin> <CE Pin > Driver CE VOUT <CD Pin > Internal Supply Voltage <RESETB Pin (R5111Sxx1x)/DOUT Pin (R5111Sxx2x)> RESETB / D OUT Driver C D Driver <SENSE Pin ( R5111Sxx2x) > <MR Pin ( R5111Sxx2x) > SENSE Internal Supply Voltage MR <SCK Pin > <TW Pin > Internal SupplyVoltage Internal Supply Voltage SCK TW Driver <INH Pin ( R5111Sxx2x) > <WDO Pin ( R5111Sxx2x) > INH Internal Supply Voltage WDO Driver 7

8 ABSOLUTE MAXIMUM RATINGS Symbol Item Rating Unit VIN Input Voltage.3 to 5 V Peak Voltage *1 6 V VCE CE Pin Input Voltage.3 to 5 V VOUT Output Voltage.3 to VIN V VCD CD Pin Output Voltage -.3 to 7. V VTW TW Pin Output Voltage -.3 to 7. V VRESETB RESETB Pin Output Voltage -.3 to 7. V VDOUT DOUT Pin Output Voltage -.3 to 7. V VWDO WDO Pin Output Voltage -.3 to 7. V VSCK SCK Pin Input Voltage -.3 to 7. V VINH INH Pin Input Voltage -.3 to 7. V VMR MR Pin Input Voltage -.3 to 7. V VSENSE SENSE Pin Input Voltage -.3 to 7. V PD Power Dissipation (HSOP-8E) *2 Power Dissipation (HSOP-18) *2 Ultra High Wattage Land Pattern JEDEC STD.51-7 Test Land Pattern Tj Junction Temperature 4 to 15 C Tstg Storage Temperature 55 to 15 C *1 Within application time of 2ms *2 Refer to the section of Package Information for details. mw ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. 8

9 RECOMMENDED OPERATING CONDITIONS Symbol Item Rating Unit VIN Input Voltage 3.5 to 36. V VCE CE Pin Input Voltage to 36. V VSCK SCKINH Pin Input Voltage to 5.5 V VINH INH Pin Input Voltage to 5.5 V VMR MR Pin Input Voltage to 5.5 V VSENSE SENSE Pin Input Voltage to 5.5 V Ta Operating Temperature Range 4 to 125 C RECOMMENDED OPERATING CONDITONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such ratings by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. 9

10 ELECTRICAL CHARACTERISTICS CIN = COUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. R5111Sxxxx-AE ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit ISS Supply Current IOUT = ma µa Istandby Power Consumption (on standby) VIN = 36V, VCE = V.1 2. µa IPD CE Pull-downConstant Current VCE = 5V.2.6 µa VCE = 36V µa VCEH CE Input Voltage "H" V VCEL CE Input Voltage "L" 1. V VR Part ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit VOUT Output Voltage IOUT = 1mA V VOUT/ IOUT Load Regulation VIN = VSET + 2.V 1mA IOUT 3mA mv VDIF Dropout Voltage IOUT = 3mA VOUT/ VIN Line Regulation VSET = V VSET = V VSET = V VSET = V 3.5V VSET +.5V VIN 36V IOUT = 1mA.1.2 %/V ILIM Output Current Limit VIN = VSET + 3.V ma ISC Short current Limit VIN = 5V, VOUT = V ma TTSD TTSR RLOW Thermal Shutdown Temperature Thermal Shutdown Release Temperature VOUT Low Output Nch Tr.ON Resistance Junction Temperature C Junction Temperature C VCE = V, VOUT =.1V kω 1

11 CIN = COUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. VD Part ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit -VDET Detector Threshold VOUT Set Detector Threshold: 1.6V to 5.5V x.982 x1.18 V VHYS tdelay Detector Threshold Hysteresis Release Output Delay Time (Power-On Reset) (-VDET) x.1 (-VDET) x.2 (-VDET) x.3 CD =.22µF ms VRESETB RESETB Pull-up Voltage R5111Sxx1A / R5111Sxx1B 5.5 V VDOUT DOUT Pull-up Voltage R5111Sxx2C / R5111Sxx2D 5.5 V IOUTNRSTB Nch. Output Current R5111Sxx1A / R5111Sxx1B (RESETB Output Pin) VIN = 3.5V, VRESETB =.1V ma ILEAKRSTB Nch. Leakage Current R5111Sxx1A / R5111Sxx1B (RESETB Output Pin) VRESETB = 5.5V.3 µa IOUTDOUT Nch. Output Current R5111Sxx2C / R5111Sxx2D (DOUT Output Pin) VIN = 3.5V, VDOUT =.1V ma ILEAKDOUT Nch. Leakage Current R5111Sxx2C / R5111Sxx2D (DOUT Output Pin) VDOUT = 5.5V.3 µa VMRH MR Input H V VMRL MR Input L.6 V MRW MR Input Pulse Width 2 µs RMR MR Pull-up Resistance kω RLCD CD Pin Discharge Nch Tr.ON Resistance VCE = V, VCD =.1V kω V 11

12 CIN = COUT =.1µF, VIN = 14V, unless otherwise noted. The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. WDT Part ( Ta = 25 C) Symbol Item Conditions Min. Typ. Max. Unit tow Open Window Time ms tcw Closed Window Time R5111Sxx1B/ R5111Sxx2D CTW = 1nF ms towl Long Open Window Time ms tign Ignoring Time CTW = 1nF ms twd Monitoring Time R5111Sxx1A/ R5111Sxx2C CTW = 1nF ms twr Reset Time CTW = 1nF ms VSCKH SCK Input H V VSCKL SCK Input L.65 V VINHH INH Input H V VINHL INH Input L.6 V RINH INH Pull-up Resistance kω tsckwh tsckwl SCK Minimum Input Pulse Width H SCK Minimum Input Pulse Width L VSCKL =.5, VSCKH = ns VSCKL =.5, VSCKH = ns VWDO WDO Pull-up Voltage 5.5 V IOUTNWDO ILEAKWDO RLTW Nch. Output Current (WDO Output Pin) Nch. Leakage Current (WDO Output Pin) CTW Discharge Nch Tr.ON Resistance R5111Sxx2C / R5111Sxx2D VIN = 3.5V, VDS =.1V R5111Sxx2C / R5111Sxx2D VWDO = 5.5V ma.3 µa VCE = V, VCTW =.1V kω All test items listed under Electrical Characteristics are done under the pulse load condition (Tj Ta = 25 C). 12

13 Product-specific Electrical Characteristics The specification in is checked and guaranteed by design engineering at 4 C Ta 125 C. VR Part ( Ta = 25 C) Product Name V OUT [V] V DIF [V] Min. Typ. Max. Typ. Max. R5111S1xx R5111S2xx R5111S3xx R5111S4xx R5111S5xx R5111S6xx R5111S7xx R5111S8xx R5111S9xx R5111S1xx R5111S11xx R5111S12xx R5111S13xx VD Part ( Ta = 25 C) Product Name -V DET [V] V HYS [V] Min. Typ. Max. Min. Typ. Max. R5111S1xx R5111S2xx R5111S3xx R5111S4xx R5111S5xx R5111S6xx R5111S7xx R5111S8xx R5111S9xx R5111S1xx R5111S11xx R5111S12xx R5111S13xx

14 R5111Sxxxx-KE ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit ISS Supply Current IOUT = ma µa Istandby IPD Power Consumption (on standby) CE Pull-down Constant Current VIN = 36V,VCE = V.1 2. µa VCE = 5V.2.6 µa VCE = 36V µa VCEH CE Input Voltage "H" V VCEL CE Input Voltage "L" 1. V VR Part ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit VOUT Output Voltage IOUT =1mA V VOUT/ IOUT Load Regulation VIN = VSET + 2.V 1mA IOUT 3mA mv VDIF Dropout Voltage IOUT = 3mA VOUT/ VIN Line Regulation 3.5V VSET +.5V VIN 36V IOUT = 1mA VSET = V VSET = V VSET = V VSET = V.1.2 %/V ILIM Output Current Limit VIN = VSET + 3.V ma ISC Short current Limit VIN = 5V, VOUT = V ma TTSD TTSR RLOW Thermal Shutdown Temperature Thermal Shutdown Release Temperature VOUT Low Output Nch Tr.ON Resistance Junction Temperature C Junction Temperature C VCE = V, VOUT =.1V kω 14

15 VD Part R5111S ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit -VDET VHYS tdelay Detector Threshold Detector Threshold Hysteresis Release Output Delay Time (Power-On Reset) VOUT Set Detector Threshold: 1.6V to 5.5V x.982 x1.18 V (-VDET) x.1 (-VDET) x.2 (-VDET) x.3 CD =.22µF ms VRESETB RESETB Pull-up Voltage R5111Sxx1A / R5111Sxx1B 5.5 V VDOUT DOUT Pull-up Voltage R5111Sxx2C / R5111Sxx2D 5.5 V IOUTNRSTB ILEAKRSTB IOUTDOUT ILEAKDOUT Output Current (RESETB Output Pin) Nch Leakage Current (RESETB Output Pin) Output Current (DOUT Output Pin) Nch Leakage Current (DOUT Output Pin) R5111Sxx1A / R5111Sxx1B Nch, VDD = 3.5V, VDS =.1V R5111Sxx1A / R5111Sxx1B VRESETB = 5.5V R5111Sxx2C / R5111Sxx2D Nch, VDD = 3.5V, VDS =.1V R5111Sxx2C / R5111Sxx2D VDOUT = 5.5V V ma.3 µa ma.3 µa VMRH MR Input H V VMRL MR Input L.6 V MRW MR Input Pulse Width 2 µs RMR MR Pull-up Resistance kω RLCD CD Pin Discharge VCE = V, VCD =.1V Nch Tr.ON Resistance kω 15

16 WDT Part ( 4 C Ta 125 C) Symbol Item Conditions Min. Typ. Max. Unit tow Open Window Time ms tcw Closed Window Time R5111Sxx1B/ R5111Sxx2D CTW = 1nF ms towl Long Open Window Time ms tign Ignoring Time CTW = 1nF ms twd Monitoring Time R5111Sxx1A/ R5111Sxx2C CTW = 1nF ms twr Reset Time CTW = 1nF ms VSCKH SCK Input H V VSCKL SCK Input L.65 V VINHH INH Input H V VINHL INH Input L.6 V RINH INH Pull-up Resistance kω tsckwh tsckwl SCK Minimum Input Pulse Width H SCK Minimum Input Pulse Width L VSCKL =.5, VSCKH =1.6 5 ns VSCKL =.5, VSCKH = ns VWDO WDO Pull-up Voltage 5.5 V IOUTNWDO ILEAKWDO RLTW Output Current (WDO Output Pin) Nch Leakage Current (WDO Output Pin) CTW Discharge Nch Tr.ON Resistance R5111Sxx2C / R5111Sxx2D VDD = 3.5V, VDS =.1V R5111Sxx2C / R5111Sxx2D VWDO = 5.5V ma.3 µa VCE = V, VCTW =.1V kω 16

17 Product-specific Electrical Characteristics VR Part ( 4 C Ta 125 C) Product Name V OUT [V] V DIF [V] Min. Typ. Max. Typ. Max. R5111S1xx R5111S2xx R5111S3xx R5111S4xx R5111S5xx R5111S6xx R5111S7xx R5111S8xx R5111S9xx R5111S1xx R5111S11xx R5111S12xx R5111S13xx VD Part ( 4 C Ta 125 C) Product Name -V DET [V] V HYS [V] Min. Typ. Max. Min. Typ. Max. R5111S1xx R5111S2xx R5111S3xx R5111S4xx R5111S5xx R5111S6xx R5111S7xx R5111S8xx R5111S9xx R5111S1xx R5111S11xx R5111S12xx R5111S13xx

18 TYPICAL APPLICATION CIRCUITS VIN Microprocessor VDD VOUT VCC C1 R5111Sxx1A/B CE C2 R1 GND RESETB RESET C D C D SCK I/O TW C TW R5111Sxx1A/B Typical Application VIN Microprocessor VDD VOUT VCC C1 R5111Sxx2C/D CE SENSE C2 R1 GND DOUT RESET WDO C D C D SCK I/O INH MR TW C TW R5111Sxx2C/D Typical Application 18

19 External Components Symbol C1 (CIN) C2 (COUT) CTW CD R1.1µF, Ceramic Capacitor.1µF, Ceramic Capacitor Description A capacitor corresponding to time setting for Watchdog Timer is required. Refer to Time Setting for WDT in Operation Description for details. A capacitor corresponding to setting for Release Output Delay Time is required. Refer to Delay Operation and Release Output Delay Time (tdelay) in Operation Description for details. A resistor is required to set with consideration of the output current and the leakage current. Refer to Electrical Characteristic for details. TECHNICAL NOTES Phase Compensation In the ICs, phase compensation is made for securing stable operation even if the load current is varied. For this purpose, use a capacitor C2 with.1 µf or more. If a tantalum capacitor is used, and its ESR (Equivalent Series Resistance) of C2 is large, the loop oscillation may result. Because of this, select C2 carefully considering its frequency characteristics. PCB Layout Make VDD and GND lines sufficient. If their impedance is too high, noise pickup or unstable operation may result. Connect.1 µf or more of the capacitor C1 between the VDD and GND, and as close as possible to the pins. In addition, connect the capacitor C2 between VOUT and GND, and as close as possible to the pins. 19

20 Prohibited Area for Fluctuations in Input Voltage Please take note that miss-detection or miss-release might be invited when changing an input voltage abruptly in the following prohibited area. 15. Input Voltage peak Vp-p (V) Prohibited Area V IN Vp-p tf Input Voltage Falling Time tf (μs) GND Prohibited Area of Fluctuation at Falling of V IN 15 Prohibited Area Input Voltage peak Vp-p (V) 1 5 V IN tr Vp-p Input Voltage Rising Time tr (μs) GND Prohibited Area of Fluctuation at Rising of V IN 2

21 TYPICAL APPLICATION FOR IC CHIP BREAKDOWN PREVENTION VIN Microprocessor C1 VDD VOUT R5111Sxx1A/B CE C2 D1 R1 VCC GND RESETB RESET CD CD SCK I/O TW CTW C1 = Ceramic.1μF C2 = Ceramic.1μF R5111Sxxxx Typical Application When a sudden surge of electrical current travels along the VOUT pin and GND due to a short-circuit, electrical resonance of a circuit involving an output capacitor (C2) and a short circuit inductor generates a negative voltage and may damage the device or the load devices. Connecting a schottky diode (D1) between the VOUT pin and GND has the effect of preventing damage to them. 21

22 OPERATION DESCRIPTION Timing Chart R5111Sxx1A / R5111Sxx1B Voltage Detector V IN V DDL +V DET V OUT -V DET V CD V TCD tdelay (2) tdelay V RESETB Undefine (1) (3) (4) (3) Undefine R5111Sxx1A / R5111Sxx1B VD Timing Chart (1) When the VOUT pin voltage (VOUT) becomes more than the release voltage (+VDET), the RESETB pin voltage (VRESETB) becomes H after the release output delay time (tdelay). (2) When the detect output delay time is less than 3 µs (Typ.) even if VOUT becomes lower than the detector threshold (-VDET), the voltage detector (VD) does not go into the detecting state. (3) When VOUT becomes lower than -VDET, VRESETB becomes "L" after the detect output delay time (Typ.3µs) and the VD goes into the detecting state. (4) When VOUT becomes more than +VDET. VRESETB becomes "H" after the release output delay time. (VTCD = Typ.1V) 22

23 R5111Sxx2C / R5111Sxx2D Voltage Detector V IN V DDL +V DET V SENSE -V DET (2) V MR V CD V TCD tdelay tdelay tdelay V DOUT Undefine (1) (3) (4) (5) (6) (3) Undefine R5111Sxx2C / R5111Sxx2D VD Timing Chart (1) When the SENSE pin voltage (VSENSE) becomes more than the release voltage (+VDET), the DOUT pin voltage (VDOUT) becomes H after the release output delay time (tdelay). (2) When the detect output delay time is 3µs (Typ.) or less even if VSENSE becomes lower than the detector threshold (-VDET), the voltage detector (VD) does not go into the detecting state. (3) When VSENSE becomes lower than -VDET, VDOUT becomes "L" after the detect output delay time (Typ. 3µs) and the VD goes into the detecting state. (4) When VSENSE becomes more than +VDET, VDOUT becomes H after the release output delay time. (VTCD = Typ.1V) (5) When the MR pin voltage (VMR) becomes L, VDOUT is fixed to "L". (6) When VMR becomes L to H, VDOUT becomes H after the release output delay time. 23

24 R5111Sxx1A Watchdog Timer (Normal Type) V IN V DDL V OUT +V DET -V DET V RESETB V TW Undefined tdelay TWVREFH t IGN t WD t W t IGN <t WD t WD t WR t IGN Undefined TWVREFL IGN WD RST IGN WD WD RST IGN WD (1) (3) (4) (5) V SCK (2) (6) R5111Sxx1A WDT Timing Chart (1) When the VOUT pin voltage (VOUT) becomes more than the release voltage (+VDET), the RESETB pin voltage (VRESETB) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (VTW) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has three states: Ignoring, Reset, and Monitoring. In each state, the TW pin is charged from V or TWFREFL (Typ..8V). (2) After the WDT starts, the WDT is in an ignoring state until VTW is charged up to TWVREFH (Typ.2V). So, a pulse to the SCK pin is ignored during the ignoring state. (3) When charging VTW up to TWVREFH has completed, the TW pin starts discharging and the WDT goes into a monitoring state. (4) When a pulse is not sent to the SCK pin before VTW reaches TWVREFH during the monitoring state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, VRESETB becomes L. (5) When VTW is charged up to TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into the ignoring state. (6) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the monitoring state, the TW pin start discharging and the WDT goes into the next open window state. 24

25 R5111Sxx1B Watchdog Timer (Window Type) V IN V DDL V OUT +V DET -V DET V RESETB V TW Undefine tdelay TWVREF t IGN <t OW <t CW t WR t IGN <t OW t CW t OW t WR t IGN Undefine TWVREFL IGN LOW CW RST IGN LOW CW OW RST IGN LOW (1) (3) (6) (7) (8) V SCK (2) (4) (5) R5111Sxx1B WDT Timing Chart (1) When the VOUT pin voltage (VOUT) becomes more than the release voltage (+VDET), the RESETB pin voltage (VRESETB) becomes H after the release output delay time (tdelaly) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (VTW) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has four states: Ignoring, Reset, Open Window, and Closed Window. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). (2) After WDT starts, the WDT is in an ignoring state until VTW is charged up to TWVREFH (Typ.2V). So, a pulse to the SCK pin is ignored during the ignoring state. (3) When VTW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into an open window state. This open window state is four times longer than the normal open window state. (4) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a closed window state. (5) When a pulse is sent to the SCK pin before VTW reaches TWVREF during the closed window state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, VRESETB becomes L. 25

26 (6) When VTW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into the ignoring state. (7) When a pulse is not sent to the SCK pin before VTW reaches TWVREFH during the closed window state, the TW pin starts discharging and the WDT goes into the open window state. (8) When a pulse is not sent to the SCK pin before VTW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into the reset state. R5111Sxx2C Watchdog Timer (Normal Type) V IN V DDL +V DET V SENSE -V DET V INH V DOUT Undefine Undefine V WDO Undefine Undefine V TW TWVREF tdelay t IGN t WD t WR t IGN <t WD t WD t IGN TWVREFL IGN WD RST IGN WD WD RST IGN WD (1) (3) (4) (5) (7) (8) V SCK (2) (6) R5111Sxx2C WDT Timing Chart 26

27 (1) When the SENSE pin voltage (VSENSE) becomes more than the release voltage (+VDET), the DOUT pin voltage (VDOUT) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (VTW) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has three states: Ignoring, Reset, and Monitoring. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). (2) After the WDT starts, the WDT is in an ignoring state until VTW is charged up to TWVREFH. So, a pulse to the SCK pin is ignored during the ignoring state. (3) When VTW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into a monitoring state. (4) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the monitoring state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, the WDO pin voltage (VWDO) becomes L. (5) When VTW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into an ignoring state. (6) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the monitoring, the TW pin starts discharging and the WDT goes into the next monitoring state. (7) The WDT stops monitoring by setting the INH pin voltage (VINH) to L. Then, VWDO is fixed to H and VTW is fixed to L. (8) When changed VINH from L to H, the WDT goes into the ignoring state and restarts monitoring. 27

28 R5111Sxx2D Watchdog Timer (Window Type) V IN V DDL V SENSE +V DET -V DET V INH V DOUT Undefine Undefine V WDO TWVREF Undefine tdelay t IGN <t OW <t CW t WR t IGN <t OW t CW t OW t IGN Undefine V TW TWVREFL IGN LOW CW RST IGN LOW CW OW RST IGN LOW (1) (3) (6) (7) (8)(9) (1) V SCK (2) (4) (5) R5111Sxx2D WDT Timing Chart (1) When the VOUT pin voltage (VOUT) becomes more than the release voltage (+VDET), the DOUT pin voltage (VDOUT) becomes H after the release output delay time (tdelay) and the watchdog timer (WDT) starts monitoring a pulse. After that, the TW pin voltage (VTW) repeats charge and discharge. As a result, a sawtooth wave is generated. The WDT has four states: Ignoring, Reset, Open Window, and Closed Window. In each state, the TW pin is charged from V or TWVREFL (Typ..8V). 28

29 (2) After WDT starts, the WDT is in an ignoring state until VTW is charged up to TWVREFH. So, a pulse to the SCK pin is ignored during the ignoring state. (3) When VTW is charged up to TWVREFH during the ignoring state, the TW pin starts discharging and the WDT goes into an open window state. This open window state is four times longer than the normal open window state. (4) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a closed window state. (5) When a pulse is sent to the SCK pin before VTW reaches TWVREFH during the close window state, the TW pin starts discharging and the WDT goes into a reset state. During the reset state, VDOUT becomes L. (6) When VTW reaches TWVREFH during the reset state, the TW pin starts discharging and the WDT goes into an ignoring state. (7) When a pulse is not sent to the SCK pin before VTW reaches TWVREFH during a closed window state, the TW pin starts discharging and the WDT goes into an open window state. (8) When a pulse is not sent to the SCK pin before VTW reaches TWVREFH during the open window state, the TW pin starts discharging and the WDT goes into a reset state. (9) The WDT stops monitoring by setting the INH pin voltage (VINH) to L. Then, VWDO is fixed to H and VTW is fixed to L. (1) When changed VINH from L to H. the WDT goes into the ignoring state and restarts monitoring. Delay Operation and Released Output Delay Time (tdelay) V OUT / SENSE Pin Released Voltage (+V DET ) Detector Voltage (-V DET ) C D Pin Voltage C D Pin Threshold Voltage (V TCD ) GND RESETB / D OUT Pin Release Output Delay Time (tdelay) GND Detect Output Delay Time (t PHL ) Released Output Delay Timing Diagram 29

30 When the operating voltage higher than the released voltage is applied to VOUT pin (R5111Sxx1A/R5111Sxx1B) or SENSE pin (R5111Sxx2C/R5111Sxx2D), charge to an external capacitor starts, then CD pin voltage (VCD) increases. RESETB pin (R5111Sxx1A/R5111Sxx1B) or DOUT pin (R5111Sxx2C/R5111Sxx2D) maintains the released output until VCD reaches the threshold voltage of the release output delay pin (VTCD). And when VCD is over VTCD, RESETB pin or DOUT pin is inverted from L to H. That is, the charged external capacitor starts discharging. When the operating voltage lower than the detector threshold is applied to VDD pin, the detect output delay time, which is the time until the output voltage is inverted from H to L, remains constant independent of the external capacitor. V OUT / SENSE -V DET +2.V RESETB / D OUT 1.5V GND 5.V 2.5V GND t PHL Released Output Delay Time tdelay Released Output Delay Time (tdelay) indicates the time between the instance when VOUT pin (R5111Sxx1A / R5111Sxx1B) or SENSE pin (R5111Sxx2C / R5111Sxx2D) shifts from 1.5 V to VDET + 2. V by the application of a pulse voltage and the instance when the output voltage reaches 2.5 V after pulled up RESETB pin (R5111Sxx1A / R5111Sxx1B) or DOUT pin (R5111Sxx2C/ R5111Sxx2D) to 5. V with a resistor of 1 kω. This is given by the expression tdelay (s) = 1.1 CD (F) / ( ), where CD (F) represents capacitance of the external capacitor. If VOUT / SENSE pin goes up at a mild pace of.1v/s or less, connect a capacitor of 1 pf or more to CD pin. 3

31 WDT State Transition Diagram Input Clock Time Out (1)R5111SxxxA/C V OUT <Detector Threshold(R5111Sxx1A) SENSE<Detector hreshold(r5111sxx2c) or INH=Low(R5111Sxx2C) V OUT >Released Output Voltage(R5111Sxx1A) SENSE>Released Output Voltage(R5111Sxx2C) and INH=High or OPEN(R5111Sxx2C) (2)R5111SxxxB/D V OUT <Detector Threshold(R5111Sxx1B) SENSE<Detector Threshold(R5111Sxx2D) or INH=Low(R5111Sxx2D) V OUT >Released Output Voltage(R5111Sxx1B) SENSE>Released Output Voltage(R5111Sxx2D) and INH=High or OPEN(R5111Sxx2D) Ignoring Ignoring Monitoring Long Open Window Reset Open Window Closed Window Reset Time Setting for Watchdog Timer The following time of WDT is dependent on a capacitor connecting to the TW pin. Relationship between the value of capacitor and time can be expressed by the following equations. tow (s) = 1.8 x C(F) / (1. x 1-6 ) tcw (s) = 1.8 x C(F) / (1. x 1-6 ) towl (s) = 1.8 x C(F) / (.25 x 1-6 ) tgn (s) = 1.8 x C(F) / (1. x 1-6 ) twd (s) = 1.8 x C(F) / (1. x 1-6 ) twr (s) = 1.9 x C(F) / (2. x 1-6 ) 31

32 Inrush Current Prevention at Rising Characteristics R5111S has the inrush current preventing circuit to control the inrush current within about 25mA limited. This circuit works during the rising periods. Therefore, the load current must be increased after rising up the output voltage (at typ.1µs after being out of the inrush current limited condition) by the sequence control. When the load current is increased during the rising periods, the inrush current must be controlled within 15mA. VSET VOUT 25mA (TYP) 1us (TYP) IOUT IRUSH IOUT<15mA 15mA<IOUT Likewise, on the thermal shutdown and the foldback characteristic, the inrush current preventing circuit works when the output voltage re-rises after the output voltage fall down to a guideline (VSET x.4) or less. VOUT VSET.4 IOUT 32

33 Voltage Setting (R5111Sxx1A / R5111Sxx1B) VD detects the drop of the VR output voltage (VOUT). When the VD release voltage (+VDET) is set to a voltage above the VR output voltage, the reset signal of VD is not released even if VD monitors the VR output voltage returns to the normal value after detecting the drop of VR. To prevent this issue, the following condition is required between VOUT and +VDET. (VR Set Output Voltage) x.985-3mv > (VD Set Detector Threshold) x 1.18 x 1.3 When using a device with the above conditions of VOUT and +VDET, careful consideration must be given to the system operation before use. Manual Reset (MR) Function (R5111Sxx2C, R5111Sxx2D) Setting the MR pin to L forcefully sets DOUT to L. The maximum value of the delay time (tmr), which is until DOUT outputs L, is 1µs as an index of the performance. The MR pin is pulled-up by an internal resistor (Typ.11kΩ). Current is passed to the MR pin when the voltage of MR > VDD. But, this current has no effect to the operation because the current is limited with a pull-up resistor. When setting the MR pin from L to H, DOUT is changed from L to H after the released output delay time and the WDT starts from the ignoring state. When the MR pin is L, the WDO pin outputs H. SENSE Function (R5111Sxx2C, R5111Sxx2D) The internal voltage detector monitors the input voltage to the SENSE pin. To measure the proper detector threshold, setting of VIN 3.5V is required. Inhibition (INH) Function (R5111Sxx2C, R5111Sxx2D) Setting the INH pin to L stops the WDT pulse monitoring function and the WDO pin is fixed to H. The INH pin is pulled up with an internal resistor (Typ.11kΩ). 33

34 PACKAGE INFORMATION POWER DISSIPATION (HSOP-8E) Power Dissipation (PD) depends on conditions of mounting on board. This specification is based on the measurement at the condition below: Measurement conditions Environment Board Material Board Dimensions Copper Ratio Through - hole Ultra High Wattage Land Pattern Mounting on board (Wind velocity m/s) Glass cloth epoxy plastic (4 layers) 76.2mm x 114.3mm x.8mm Top side, Back side : 5mm square, Approx.95% 2nd, 3rd Layer: 5mm square, Approx. 1% φ.4mm x 21pcs Measurement Results Power Dissipation Thermal Resistance (Ta = 25 C, Tjmax = 15 C) Ultra High Wattage land pattern 36mW θja = (15-25 C)/3.6W = 35 C/W θjc = 1 C/W Power Dissipation PD (W) (Ultra High Wattage On Board Land Pattern) Ambient Temperature ( ) Power Dissipation Measurent Board Pattern IC Mount Area Unit : mm 34

35 PACKAGE DIMENSION (HSOP-8E) 8 5 (.3) 2.9±.5 S 1.5±.1 4.4±.2 6.2±.3 2.7±.5 ~1 (.3) TYP 5.2±.3.1 S ±.2.4±.1 DETAIL A M *) The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating. DETAIL A.5±.5.8±.5 (Unit : mm) HSOP-8E Package Dimensions MARK SPECIFICATION (HSOP-8E) : Product Code Refer to MARK SPECIFICATION TABLE (HSOP-8E) 789: Lot Number Alphanumeric Serial Number HSOP-8E Markings 35

36 MARK SPECIFICATION TABLE (HSOP-8E) R5111Sxx1A/B Product Name Product Name V SET / -V SET VR VD R5111S11A R S 111A R5111S11B RS111N 5.V 4.6V R5111S21A R S 111B R5111S21B RS111P 1.8V 1.6V R5111S31A R S 111C R5111S31B RS111R 5.V 4.5V R5111S41A R S 111D R5111S41B RS111S 5.V 4.4V R5111S51A R S 111E R5111S51B RS111T 5.V 4.3V R5111S61A R S 111F R5111S61B RS111U 5.V 4.2V R5111S71A R S 111G R5111S71B RS111V 5.V 3.7V R5111S81A R S 111H R5111S81B RS111W 3.3V 3.V R5111S91A R S 111J R5111S91B RS111X 3.3V 2.9V R5111S11A R S 111K R5111S11B RS111Y 3.3V 2.8V R5111S111A R S 111L R5111S111B RS111Z 3.3V 2.7V R5111S121A RS111M R5111S121B RS112A 5.V 4.1V R5111S131A R S 112B R5111S131B RS112C 3.4V 3.1V 36

37 POWER DISSIPATION (HSOP-18) Power Dissipation (PD) depends on conditions of mounting on board. This specification is based on the measurement at the condition below: Measurement Conditions Environment Board Material Board Dimensions Copper Ratio Through-holes JEDEC STD.51-7 Test Land Pattern Mounting on Board (Wind velocity=m/s) Glass cloth epoxy plastic (4 layers) 76.2 mm mm 1.6 mm Top side, Back side : 6mm square, Approx.1% 2nd, 3 rd Layer: 74.2mm square, Approx. 1% φ.85mm x 44pcs Measurement Result: Power Dissipation Thermal Resistance (Ta = 25 C, Tjmax = 15 C) JEDEC STD.51-7 Test Land Pattern 3125 mw Θja = (15 25 C) / W = 4 C/W Θjc = 9 C/W Power Dissipation PD (mw) (JEDEC STD.51-7 Test Land Pattern) Ambient Temperature ( C) Power Dissipation Measurement Board Pattern IC Mount Area (Unit : mm) 37

38 PACKAGE DIMENSIONS (HSOP-18) 18 1 (.3) 2.9±.5 4.4±.2 6.2±.3 (.3) 2.7±.5 S 1 9.6TYP 5.2±.3.1 S 1.5±.1 ~1.5.4±.2.2±.1 DETAIL A.12 M *) The tab on the bottom of the package enhances thermal performance and is electrically connected to GND (substrate level). It is recommended that the tab be connected to the ground plane on the board, or otherwise be left floating. DETAIL A.5±.5.8±.5 (Unit : mm) HSOP-18 Package Dimensions MARK SPECIFICATION (HSOP-18) :Product Code Refer to MARK SPECIFICATION TABLE (HSOP-18) 789:Lot Number Alphanumeric Serial Number HSOP-18 Markings

39 MARK SPECIFICATION TABLE (HSOP-18) R5111Sxx2C/D Product Name Product Name V SET / -V SET VR VD R5111S12C R S 114A R5111S12D R S 114N 5.V 4.6V R5111S22C R S 114B R5111S22D R S 114P 1.8V 1.6V R5111S32C R S 114C R5111S32D R S 114R 5.V 4.5V R5111S42C R S 114D R5111S42D R S 114S 5.V 4.4V R5111S52C R S 114E R5111S52D R S 114T 5.V 4.3V R5111S62C R S 114F R5111S62D R S 114U 5.V 4.2V R5111S72C R S 114G R5111S72D R S 114V 5.V 3.7V R5111S82C R S 114H R5111S82D RS114W 3.3V 3.V R5111S92C R S J R5111S92D R S 114X 3.3V 2.9V R5111S12C R S 114K R5111S12D R S 114Y 3.3V 2.8V R5111S112C R S 114L R5111S112D R S 114Z 3.3V 2.7V R5111S122C R S M R5111S122D R S 115A 5.V 4.1V R5111S132C R S 115B R5111S132D R S 115C 3.4V 3.1V 39

40 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) Power Consumption vs. Input Voltage (Ta = 25 C) VR=1.8V VR=3.3V Supply Current IIN (μa) Input Voltage V IN (V) Supply Current IIN (μa) Input Voltage V IN (V) Supply Current IIN (μa) VR=5.V Input Voltage V IN (V) 2) CE Pin Current vs. CE Pin Voltage (Ta = 25 C, V IN=14V) VR=5.V CE Crrent ICE (μa) CE Input Voltage V CE (V) 4

41 3) GND Pin Current vs. Output Current (Ta = 25 C) I GND (μa) Output Current I OUT (ma) 4) Output Voltage vs. Output Current (Ta = 25 C) VR=1.8V VR=3.3V Output Voltage V OUT (V) Output Current I OUT (ma) VIN=3.5V VIN=4.V VIN=4.8V Output Voltage V OUT (V) Output Current I OUT (ma) VIN=3.8V VIN=4.3V VIN=6.3V VR=5.V 6. Output Voltage VOUT(V) Output Current I OUT (ma) VIN=5.5V VIN=6.V VIN=8.V 41

42 5) Output Voltage vs. Input Voltage (Ta = 25 C) VR=1.8V VR=3.3V Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Input Voltage V IN (V) Input Voltage V IN (V) VR=5.V Output Voltage VOUT (V) Iout=1mA Iout=3mA Iout=15mA Input Voltage V IN (V) 6) Output Voltage vs. Temperature (V IN=14V, I OUT=1mA) VR=1.8V VR=3.3V Output Voltage V OUT (V) Output Voltage V OUT (V) Ta ( ) Ta ( ) 42

43 VR=5.V 5.1 Output Voltage V OUT (V) Ta ( ) 7) Dropout Voltage vs. Output Current VR=1.8V VR=3.3V VR=5.V 43

44 8) Dropout Voltage vs. Output Voltage (Ta=25 ) 9) Ripple Rejection vs. Input Voltage (Ta=25, Ripple =.2 Vpp) VR=1.8V, I OUT=1mA VR=1.8V, I OUT=3mA 1 1Hz 9 1kHz I OUT = 1mA 8 1kHz 7 1kHz Input Voltage VIN (V) Ripple Rejection RR (db) Ripple Rejection RR (db) VR=3.3V, I OUT=1mA 1Hz 1kHz 1kHz 1kHz I OUT = 1mA Input Voltage VIN (V) Ripple Rejection RR (db) Ripple Rejection RR (db) Hz 1kHz 1kHz 1kHz Input Voltage VIN (V) VR=3.3V, I OUT=3mA 1Hz 1kHz 1kHz 1kHz I OUT = 3mA I OUT = 3mA Input Voltage VIN (V) 44

45 VR=5.V, I OUT=1mA 1 1Hz 9 1kHz I OUT = 1mA 8 1kHz 7 1kHz Input Voltage VIN (V) Ripple Rejection RR (db) Ripple Rejection RR (db) VR=5.V, I OUT=3mA 1Hz 1kHz 1kHz 1kHz I OUT = 3mA Input Voltage VIN (V) 1) Ripple Rejection vs. Frequency (Ta=25, Ripple=.2 Vpp) VR=1.8V 1 V IN = 4.V VR=3.3V V IN = 5.3V 8 8 Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Frequency [khz] Frequency [khz] 1 9 VR=5.V V IN = 7.V Ripple Rejection RR(dB) IOUT=1mA IOUT=3mA IOUT=15mA Frequency [khz] 45

46 11) Input Transient Respon (Ta=25 C) VR=1.8V, C OUT=.1μF VR=1.8V, C OUT=1μF C OUT =.1μF 5. C OUT = 1μF 5. Output Voltage VOUT (V) Input Voltage 3.5 <=> 4.5V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 3.5 <=> 4.5V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) VR=3.3V, C OUT=.1μF VR=3.3V, C OUT=1μF C OUT =.1μF 5.8 C OUT = 1μF 5.8 Output Voltage VOUT (V) Input Voltage 4.3 <=> 5.3V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 4.3 <=> 5.3V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) VR=5.V, C OUT=.1μF VR=5.V, C OUT=1μF C OUT =.1μF 7.5 C OUT = 1μF 7.5 Output Voltage VOUT (V) Input Voltage 6. <=> 7.V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Output Voltage VOUT (V) Input Voltage 6. <=> 7.V (tr=tf=5usec) Outut Voltage Input Voltage VIN (V) Time (μs) Time (μs) 46

47 12) Load Transient Response (Ta=25 C) VR=1.8V, C OUT=.1μF VR=1.8V, C OUT=1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage.8 Output Voltage Time (μs) Time (ms) VR=3.3V, C OUT=.1μF VR=3.3V, C OUT=1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage 2.3 Output Voltage Time (μs) Time (ms) VR=5.V, C OUT=.1μF VR=5.V, C OUT=1μF 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) 3 15 Output Current 1mA <=>15mA (tr=tf=.5usec) Output Current IOUT (ma) Output Voltage VOUT (V) Output Current IOUT (ma) Output Voltage VOUT (V) Output Voltage 4. Output Voltage Time (μs) Time (ms) 47

48 13) CE Transient Response (Ta=25, V IN=14V, I OUT=1mA, C OUT=.1μ~47μF) CE Input Voltage V CE (V) Output Voltage V OUT (V) VR=1.8V, CE at rising CE.1µF 1.µF 4.7µF 1µF 47µF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) VR=1.8V, CE at falling CE Input Voltage Output Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Time (ms) Time (ms) VR=3.3V, CE at rising VR=3.3V, CE at falling CE Input Voltage V CE (V) Output Voltage V OUT (V) CE.1µF 1.µF 4.7µF 1µF 47µF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) CE Input Voltage Output Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Time (ms) Time (ms) VR=5.V, CE at rising VR=5.V, CE at falling CE Input Voltage V CE (V) Output Voltage V OUT (V) CE.1µF 1.µF 4.7µF 1µF 47µF Inrush Current (ma) CE Input Voltage V CE (V) Output Voltage V OUT (V) CE Input Voltage Output Voltage VCE.1uF 1.uF 4.7uF 1uF 47uF Time (ms) Time (ms) 48

49 14) Detector Threshold vs. Temperature VD=1.6V VD=3.V Detector Threshold V DET (V) Detector Threshold V DET (V) Ta ( ) Ta ( ) VD=4.6V Detector Threshold V DET (V) Ta ( ) 15) D OUT Pin Voltage vs. SENSE Pin Input Voltage (D OUT pulled-up to 5V with 1kΩ) VD=1.6V VD=3.V Output Voltage DOUT (V) Output Voltage D OUT (V) Input Voltage V SENSE (V) Input Voltage V SENSE (V) 49

50 VD=4.6V 6 5 Output Voltage D OUT (V) Input Voltage V SENSE (V) 16) Release Output Delay Time vs. Input Voltage 17) Release Output Delay Time vs. Temperature Output Delay Time for Release t PLH (ms) C D =.22μF Input Voltage V IN (V) Output Delay Time for Reset tdelay (ms) 26 C D =.22μF Ta ( ) 18) Detect Output Delay Time vs. Temperature 19) Release/ Detect Delay Time vs. External Capacitor for C D Pin 6 1 Output Delay Time for Release tdelay (μs) Output Delay Time for Release [tdelay (ms)] Output Delay Time for Reset [tdelay (ms)] 1 1 tdelay 1 t PHL Ta ( ) External Capacitance C D (nf) 5

51 2) WDT t WD / t OW / t CW / t IGN vs. Input Voltage Monitoring Time t WD / Open Window Time t OW / Closed Window Time t CW / Ignore Time t IGN (ms) t WD / t OW / t CW / t IGN C TW = 1nF Input Voltage V IN (V) 21) Reset Time vs. Input Voltage 22) Long Open Window Time vs. Input Voltage R5111SxxxB/D Reset Time twr (ms) C TW = 1nF Input Voltage V IN (V) Long Term Open Window Time towl (ms) 82 C TW = 1nF Input Voltage V IN (V) 23) WDT t WD / t OW / t CW / t IGN vs. Temperature Monitoring Time twd / Open Window Time tow / Closed Window Time t CW / Ignore Time tign (ms) 2 C TW = 1nF 19 t WD / t OW / t CW / t IGN Ta ( ) 51

52 24) Reset Time vs. Temperature 25) Long Open Window Time vs. Temperature Reset Time twr (ms) 1.4 C 1.2 TW = 1nF Ta ( ) Long Term Open Window Time t OWL (ms) R5111SxxxB/D 82 C TW = 1nF Ta ( ) 26) WDT t WD / t OW / t CW / t IGN /t OWL / t RST Vs. External Capacitor for C TW Pin 1 1 t OWL Window Time (ms) t WD / t OW / t CW / t IGN t RST External Capacitance C TW (nf) 27) Nch. Driver Output Current vs. V DS 28) Nch. Driver Output Current vs. Input Voltage Nch Driver Output Current (ma) ( I OUTRSTB / I OUTDOUT / I OUTWDO ) V IN =5., 6.V VIN=3.5V VIN=4.V VIN=5.V VIN=6.V V DS (V) (V RESETB / V DOUT / V WDO ) Nch Driver Output Current (ma) ( IOUTRSTB / IOUTDOUT / IOUTWDO ) V DS (V RESETB / V DOUT / V WDO ) =.1V -4 C 25 C 15 C 125 C Input Voltage V IN (V) 52

53 ESR vs. Output Current The IC is recommended to use a ceramic type capacitor, but the IC can be used other capacitors of the lower ESR type. The relation between the output current (IOUT) and the ESR of output capacitor is shown below. C1 VDD VOUT CE R5111x GND C2 IOUT ESR C1 = Ceramic.1 μf, C2 = Ceramic.1 μf Measurement Conditions: Frequency Band: 1 Hz to 2 MHz Measurement Temperature: 4 C to 125 C Hatched area: Noise level is 4 μv (average) or below Ceramic Capacitor: C1 = C2 = Ceramic.1 μf 1 VR=1.8V V IN = 3.5V to 36V 1 VR=3.3V V IN = 3.5V to 36V Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Output Current I OUT (ma) VR=5.V V IN = 5.V to 36V Output Current I OUT (ma) Equivalent Series Resistance ESR (Ω) Ta=-4 C 125 C Output Current I OUT (ma) 53