Low Power 10 PAM Transmitter Using Mixed Signal Design Approach

Transcription

1 International Journal of Research in Computer and Communication Technology, Vol 2, Issue 12, December ISSN (Online) ISSN (Print) Low Power 10 PAM Transmitter Using Mixed Signal Design Approach Jenifer Hepzibah.S.K 1, Vignesh Raja.B 2, Arun Kumar.N 3, Anjo.C.A 4 1 PG Scholar, 2,3,4 Assistant Professor at Veltech Multitech Dr.Rangarajan Dr.Sakunthala Engineering College, Avadi, Chennai 1 jeni.hepzi7@gmail.com 2 vigneshraja.b@gmail.com 3 arundevnkumar@gmail.com 4 anjo_ca141@yahoo.com Abstract The mixed signal design approach for 10- level pulse amplitude modulation (10-PAM) transmitter which transmit 4-bit per symbol. The frequency is reduced thereby the power dissipation is greatly reduced. The data rate is increased by the use of clock divider and hence the speed is enhanced. In this paper the mixed signal design approach uses both the analog and digital domain in order to get the efficient design. This can be achieved by the use of AMS tool in CADENCE. Since it uses serial link transceiver the parallel inputs from pseudo random bit sequence (PRBS) generator is serialized by the multiplexer which is encoded by the encoder, and then it is driven by the output driver. This is transmitted from the output driver to receiver by pulse amplitude modulation. Index Terms CMOS, Pulse amplitude modulation (PAM) I. INTRODUCTION Nowadays the mixed signal approach is the most emerging technique that is implemented to obtain less area and power. In any vlsi chip design some module can be effectively designed with the analog design whereas with the digital it is difficult to be implemented say output driver in this transmitter design. On the other side some modules can be designed in an effective way by digital domain by VHDL or verilog coding say the design of encoder or 4x1 multiplexor each carrying 4 bit is a tedious task to be implemented with the schematic analog design more over it consumes lot of power and area. By analyzing the different modules in the design some modules with the analog and other with the digital domain are designed. These modules in analog and digital flow are combined to form the full block of transmitter. In order to obtain complete design analog mixed signal (AMS) tool is used in CADENCE. With this AMS tool both the analog and digital domain are combined whereas this is not available with the SPICE or tanner EDA tools. The transmitter design for 10 level pulse amplitude modulator includes a pseudo random bit sequence (PRBS) generator, clock divider, multiplexers, an encoder, and an output driver. The modules that are PRBS, encoder, multiplexer are designed with the verilog coding in digital domain. The design of the output driver and the current source for the output driver is implemented with the schematic analog domain. II. POWER DISSIPATION OF 10 LEVEL PAM The power dissipation in 10 level PAM depends on the type of logic used that may be CMOS or other logic. The CMOS logic is efficient than any other logic due to the its low power and high speed. The short circuit and leakage is less. The power dissipation of the transmitter is also proportional to the N level. The voltage difference between the adjacent level is the ratio of full scale voltage to the N-1 level. The power dissipation in 10-PAM also depends on the symbol rate. The power dissipation is directly propotional to the number of logic gates used. A. Eye Diagram An open eye pattern corresponds to minimal signal distortion. Distortion of the signal waveform due to intersymbol interference and noise appears as closure of the eye pattern. The eye diagram is used to visualize the waveforms that transmits multiple bits of data can potentially lead to errors in the interpretation of those bits. This is the problem of intersymbol interference. Certain pulse shapes are Page 1490

2 used specifically to alleviate this. The maximum eye openings in the common-mode levels help to ensure a reliable data transmission using both common-mode and differential-mode. Fig. 1. Dual-mode 10-PAM (a) 6-differential-mode levels at VC3, (b) 4-differential-mode levels at VC2, and (c) 6 -differential-mode levels at VC1. B.10 LEVEL PAM The number of possible pulse amplitudes can be infinite in the case of analog PAM, but it is usually some power of two so that the resulting output signal can be digital. For example, in 4-level PAM there are 22 possible discrete pulse amplitudes; in 8-level PAM there are 23 possible discrete pulse amplitudes; and in 16-level PAM there are 24 possible discrete pulse amplitudes. Since there is small difference the use of 10Pam is effective and hence the very high data rate is achieved transmitting 4 bits/symbol. The dual-mode 10-PAM transceiver has strong immunity against common-mode noise, so it will not degrade BER by common-mode noise unless common-mode noise is two times larger than the differential-mode ones. Implementing the optimal detection methods for multi-gb/s rates demands high complexity and large area. Instead, square pulses, which can be generated and detected with modest complexity, are here as the basis communication symbols. At rates well above the channel bandwidth, however, square pulses result in severe inter symbol interference (ISI), which reduces the data-eye openings. In order to achieve the target data rate, the 10- PAM scheme reduces the symbol rate to half compared to a conventional 8-PAM system. This symbol rate reduction lowers not only the ISI in the channel but also the maximum required on-chip clock frequency. The eye diagrams for a 10-PAM system with different slew rates the eye diagram has sharper transition results in a larger eye opening. 6-differential-mode levels, 4-differential-mode levels and 6-differential-mode levels to distinguish 4-bit data, the common-mode voltages is represented in each case as VC1,VC2 and VC3. The 3-level common-mode voltages were measured from the average of the two outputs. The common-mode which is a single-ended signal has less stable eye-diagram than the differential-mode. This is due to the presence common-mode noise which cannot be rejected. But common mode voltage has the higher voltage margin than the differentialmode. To increase the channel-efficiency, a dualmode PAM technique can be utilized. The standard 16-PAM technique using 16 levels, the dual-mode 10-PAM technique used here employs only 10 levels to transmit 4-bit per symbol. 10-PAM transmitter can reduce the symbol-rate compared with binary signaling transceivers. This symbol-rate reduction lowers not only the intersymbol interference (ISI) of the signal in the channel, but also the maximum operating frequency in the internal circuits. III. TRANSMITTER MODULE The dual-mode 10-PAM transmitter employs a 16- bit parallel pseudo random bit sequence (PRBS) generator for built-in self-test (BIST), 2 -to-1 multiplexers, an encoder, clock dividers, and an output driver. CK is an external clock for generating data sequences to transmit. 16-bit parallel PRBS sequences, generated in the PRBS generator by length, are serialized to 4-bit parallel data by 4-to-1 multiplexers. The serialized 4-bit data are encoded into 5-bit control signals by encoding logics and transmitted through OUT1 and OUT2 terminals of the output driver. The 10-PAM transmitter achieved 4 bit/symbol with 10 differential-mode levels and 3 commonmode levels. The symbol-rate is measured from the difference of the two outputs. The minimum eye opening of the differential-mode for the maximum output voltage swing. The horizontal eye opening by the timing margin of the eye-diagram depends on both timing jitter and signal slope (bandwidth). C.Dual mode The dual-mode 10-PAM technique employs both differential mode and common-mode PAMs. It uses Page 1492

3 Fig 2. Block Diagram of proposed 10 PAM Transmitter The clock divider is designed to divide the external clock frequency into half and then again into half the clock to obtain ¼ clock. Hence the period of the ½ clock is less than the original clock period. This ½ clock and ¼ clock are given as the selection line to the 4X 1 multiplexer. This clock divider output helps to select the output from the pseudo random generator. The counter is used to divide the clock at ½ and ¼ clock frequency. The clock divider is designed with the verilog coding and the simulation is done with the test bench program. With the RC compiler the program is compiled. A. Pseudo Random Binary Generator The 16-bit parallel PRBS generator is used to generate the random binary sequence for the transmitter. It is used for an efficient method of test by Built In Self Test (BIST). The eye-diagram of the 10 level PAM transmitter can be analyzed without any external random data input. 16-bit parallel PRBSs can be produced with shifting operations and XOR gates. To implement 16 bit PRBS 16flip-flops are used. The 16-bit parallel scheme is chosen to get a high data-rate. The data-rate of the PRBS generator depends on the propagation delays of flip-flop and XOR gate. The external high speed clock is used for generating data sequences to transmit. The 16-bit parallel PRBS sequences are generated in the PRBS generator by length , are serialized to 4-bit parallel data by 4-to-1 multiplexer. The modified pseudorandom sequence generator is designed for high-speed data communications produces a set of sequences are used for the systems with spread spectrum or code division multiple access (CDMA) techniques. T hese systems are used in communication device, such as cellular phones, GPS devices, and very small aperture satellite terminals (VSATS). The algorithm used for efficient implementation of PRBS is C. Multiplexer The 4:1 multiplexer is designed with the verilog coding and the simulation is done with the test bench program. With the RC compiler, RTL diagram is generated by using the constraint file. The netlist and sdc file are written. The module should operate in a correct time without any slack. This slack is reduced and hence it becomes less. This can be reduced by adjusting the uncertainty in the constraint file. The skew rate is also calculated during the synthesis of the program. P(n+N;I) =L N.P(n;I) Where L is the matrix with r rows and N is the non negative integer. Two mask stacks are used in this 16 bit parallel binary sequence generator of N=16 bit outputs are generated from 16 XOR gates. The inputs are clk, reset, datain, seed, dataout. The datain is splitted into 4 seeds and the verilog coding is used to select each one inorder to perform shifting and XOR operations. The seed regulates the selection of seed. The several looping operations are used to generate the 16 bit random sequence at the high rate with the maximum length. Fig. 3. RTL diagram of 4 X 1multiplexor. The detailed timing report for the worst path is generated. The area and power report is generated. TABLE I. ANALYSIS OF MULTIPLEXOR AT DIFFERENT SWITCHNG MODES B. Clock Divider Page 1493

4 Slow Typical Fast Number of cells Area Slack Rise slew Fall skew Leakage power Dynami c power Nw Power The 4-bit data are encoded into 5-bit control signals by encoding logics and transmitted to the output driver. For high security applications, encryption methods are usually implemented in the electronic device to protect the information that is stored in or transmitted to and from the device. Encoder is designed with the verilog coding and the simulation is done with the test bench program. With the RC compiler, RTL diagram is generated by using the constraint file. The detailed timing report for the worst path is generated. The area and power report is generated. TABLE II. ANALYSIS OF ENCODER CLOCK FREQUENCY, SLACK AND POWER Period Clock frequency Slack (ps) Power () 0.75ns 1.3 GHz ,134 1ns 1 GHz ,545 2ns 0.5 GHz ,482 The existing encoder verilog code is written and simulated for the period of 0.75ns. The RTL synthesis is made with the rc compiler then power and the area report is found. The existing system consumes more power. Fig. 4 Slack Estimation of 4 X 1multiplexor Then the standard cells are placed. Special routing is made with the help of metal 6 and metal 1 for standard cell pins and stripes. Timing report for pre- CTS at setup and then hold s done. The area density should not exceed the maximum of 70% for the perfect design. The slack is checked. The slack should not be negative so it is checked at each time in the timing report. The clock tree synthesis is performed. Then the post-cts is reported for setup and for the hold. The density of the area is increased once after the CTS is performed. Mostly in the hold, the slack is negative. In order to get it as positive optimization is done. Then the nano route is performed and the post route is done for setup and hold if the slack is negative optimization is done. Make sure that the density of the chip should not overflow. Then the geometry is verified and the GDSII file is saved. D. Encoder Fig. 5. RTL Diagram of Existing Encoder TABLE III. ANALYSIS OF ENCODER AREA, SLACK AND POWER FOR EXISTING ENCODER Library Area Slack Power () (ps) Typical , Fast , Slow , Page 1494

5 At various clock frequency the slack is checked. There exists a tradeoff between the power and slack. The slack should not be negative and it should be positive and of less value so at 0.75ns of 1.3 GHz it is achieved. The slack of 48ps is achieved with the power of 388,134. Fig. 6. RTL Diagram of Proposed Encoder Fig. 7. Simulation Output of Proposed Encoder TABLE IV. ANALYSIS OF ENCODER AREA, SLACK AND POWER FOR PROPOSED ENCODER Library Area Slack(ps) Power() Typical , Fast , Slow ,134 There are different switching modes on which the analog design is analyzed are typical, fast, slow. Then the area, slack and power dissipation in each case can be analyzed in order to get the area and power efficient system. In the proposed encoder system though there is trade off with the power, the strong security is enhanced by the addition of gates for encryption. The slack is checked. The slack should not be negative so it is checked at each time in the timing report. The clock tree synthesis is performed. Then the post-cts is reported for setup and for the hold. The density of the area is increased once after the CTS is performed. For the negative slack optimization is done. Make sure that the density of the chip should not overflow. Then the geometry is verified and the GDSII file is saved. The nano route is performed and the post route is done for setup and hold if the slack is negative optimization is done. Then the geometry is verified and the GDSII file is saved. E. Output Driver and Current Source The current source cannot be used directly as the symbol. It should be replaced by the circuit, since with current source the layout is not performed. The current source has to be effectively designed such that it should source the current to the high speed transmitter. The output driver is used to drive the encoder which is in the form of the binary values to the out1 and out2. Any circuit which is designed in CMOS 180nm technology cannot be applied for the CMOS 90 nm technology. This is due to the short channel effect. The supply voltage is same but the channel length is decreased and this causes hot carrier effects. Though different libraries are available, it faces many challenges in the design. So the output driver circuit is separate for 180nm and 90nm technology. Whereas with the digital domain, the modules designed in 180nm can be used in 90nm also the same coding and this is the advantage of digital over analog design. The area cannot be estimated in the schematic level and it can be estimated only after the layout is done but this is not the case of digital domain. The optimization of area is possible and the simulation of the layout should match the logic in which the circuit is designed. The voltage margin of the 10-PAM output driver signals depends on mismatches and output impedances of the current sources. Due to the channel-length modulation, the gate-source voltage of the switching pair increases, hence the drainsource voltage of the current source decreases such that tail current decreases. In order to overcome this Page 1495

6 the mismatches are reduced so the layout for the current source is obtained. IV. CONCLUSION By employing dual mode 10 PAM transmitting 4 bits/symbol the power dissipation is reduced. In addition compared to the 180nm technology the area is much reduced in 90nm technology. The area is calculated for the each module in the digital domain and hence the minimum area layout is obtained since the channel length is reduced. The supply voltage for the transistors are reduced in the 90nm technology hence the power dissipation also reduced by adjusting the delay in the mixed signal design. Since the transmitted output is serialized the power also greatly reduced. REFERENCES [1] Bongsub Song, Kyunghoon Kim, Junan Lee and Jinwook Burm, A m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver, IEEE Transactions On Circuits And Systems Regular Papers, Vol. 60, No. 2, February 2013 [2] Jun-Yong Song, and Oh-Kyong Kwon Low-Power 10- Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-μm CMOS Technology, IEEE Transactions On Circuits And Systems: Express Briefs, Vol. 58, No. 12, Dec [3] H. Cheng, F. A. Musa, and A. C. Carusone, A 32/16- Gb/s dual-mode pulsewidth modulation pre-emphasis (PWM-PE) transmitter with30-db loss compensation using a high-speed CML design methodology, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp , Aug [4] Digital communication by Simon Hykins. [5] Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, and Jae-Yoon Sim, A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. IEEE Transactions On Circuits And Systems, Express Briefs, Vol. 60, No. 2, Feb [6] Jun-Yong Song, and Oh-Kyong Kwon Low-Power 10- Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-μm CMOS Technology, IEEE Transactions On Circuits And Systems: Express Briefs, Vol. 58, No. 12, Dec [7] G. Boselli, J. Rodriguez, C. Duvvury, and J. Smith, Analysis of ESD protection components in 65 nm CMOS technology: Scaling perspective and impact on ESD design window, in Proc. EOS/ESD Symp., 2005,pp [8] Designing analog chips by Hans Camenzind. [9] John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V.Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, A 10- Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology IEEE Journal Of Solid-State Circuits, Vol. 41, No. 12, Dec 2006 [10] Goran S. Miljković, Ivana S. Stojković, Dragan B. Denić, Generation And Application Of Pseudorandom Binary Sequences Using Virtual Instrumentation Facta Universitatis Series: Automatic Control and Robotics Vol. 10, No 1, 2011, pp [11] Kaiyu Wangaa, Zhenan Tang, Hualong Li, Yun Zhao, Xi Song, Jiandong Su, Design and Simulation of a CMOS Current Source Cell Procedia Environmental Sciences 10 ( 2011 ) [12] Varghese, G.T, Mahapatra, K.K. A high speed low power encoder for a 5 bit flash ADC IEEE Journal Of Solid- State Circuits, Vol. 32, No. 8, Dec 2012 [13] B. Razavi, Design of Analog CMOS Integrated Circuits. NewYork:McGraw-Hill, [14] S. M. Shajedul Hasan and Steven W. Ellingson Integration of Simple Antennas to Multiband Receivers Using a Novel Multiplexer Design Methodology IEEE Transactions On Antennas And Propagation, Vol. 60, No. 3, March Page 1496