Design of Sub-mW RF CMOS Low-Noise Amplifiers

Transcription

1 Design of Sub-mW RF CMOS Low-Noise Amplifiers by DEREK HO B. A. Sc., The University of British Columbia, 005 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA March 007 Derek Ho, 007

2 Abstract The quest for low power, low cost, and highly integrated transceivers has gained substantial momentum due to the explosion of wireless applications such as personal area networks and wireless sensor networks. This dissertation presents a comprehensive study and a design methodology for power-efficient CMOS radio-frequency (RF) low-noise amplifiers (LNAs). To demonstrate the design methodology, a sub-mw fully integrated narrow-band source degenerated cascode RF LNA is designed and simulated in a standard 90nm CMOS process to operate in the.4ghz band. The LNA achieves a voltage gain of.7db, noise figure (NF) of.8db, 3 rd -order intercept point (IIP3) of +5.14dBm, and 1dB compression point (P1dB) of 10dBm, while consuming 943μW from a 1V supply. The main contributions of this work include: i) the introduction of a design methodology for power-efficient sub-mw source degenerated LNAs; ii) the collection of design graphs to facilitate the exploration of tradeoffs between LNA performance and power consumption; and iii) the use of an alternative analysis to find the dependency of gain, noise, and linearity on biasing conditions. ii

3 Table of Contents ABSTRACT... II TABLE OF CONTENTS...III LIST OF FIGURES...V LIST OF TABLES... VI ACKNOWLEDGMENT... VII CHAPTER 1. INTRODUCTION... 1 MOTIVATION... 1 RESEARCH OBJECTIVE... THESIS ORGANIZATION... 3 CHAPTER. BACKGROUND... 5 TWO-PORT NETWORKS... 5 IMPEDANCE MATCHING... 6 SCATTERING PARAMETERS... 7 LINEARITY... 9 Harmonic Distortion... 9 Intermodulation db Compression Point rd Order Intercept Point STABILITY NOISE IN TWO-PORT SYSTEMS CHAPTER 3. CMOS LNA FUNDAMENTALS NOISE SOURCES IN CMOS Thermal Noise Induced Gate Noise... 0 Distributed Gate Noise... INTRINSIC MOSFET TWO-PORT NOISE PARAMETERS... 3 INDUCTIVE SOURCE DEGENERATION... 4 Input Impedance Match... 5 Circuit Transconductance... 6 CIRCUIT TOPOLOGIES... 7 PERFORMANCE OF THE CASCODE AMPLIFIER... 9 Voltage and Power Gain Noise Linearity INDUCTOR DESIGN Physical Dimensions Inductor Figures of Merit Inductor Modeling CHAPTER 4. DESIGNING FOR POWER-EFFICIENT OPERATION DEVICE BIASING Terminal I-V Characteristics Gain and Transconductance TRANSISTOR SIZING STEP-BY-STEP LNA DESIGN METHODOLOGY iii

4 CHAPTER 5. DESIGN OF A POWER-EFFICIENT LNA AND SIMULATION RESULTS... 5 CIRCUIT TOPOLOGY AND IMPEDANCE MATCHING... 5 POWER-EFFICIENT LNA DESIGN Gain Noise Linearity SIMULATION RESULTS PERFORMANCE SUMMARY... 6 CHAPTER 6. CONCLUSIONS AND FUTURE WORKS CONCLUSION FUTURE WORK REFERENCES iv

5 List of Figures Chapter Figure.1 Two-port network diagram....5 Figure. A system with a source driving a load...6 Figure.3 S parameter representation of a two-port network....7 Figure.5 Frequency locations of distortion terms...1 Figure.4 Noise modeling. (a) Noisy two-port, (b) Input-referred noise model...15 Chapter 3 Figure 3.1 MOSFET small-signal model with thermal noise Figure 3. Induced gate noise model. (a) Frequency dependent, (b) Frequency independent...1 Figure 3.3 Inductive source degeneration...5 Figure 3.4 Narrow-band topologies. (a) Common-source, (b) Cascode...7 Figure 3.5 VIP3 of a 40nm nfet vs. V GS for different V DS (V TH = 0.3V) []...3 Figure 3.6 The layout of a square spiral inductor Figure 3.7 Pi-model of inductor...36 Chapter 4 Figure 4.1 I D vs. V GS for a 90nm nfet (V DS = 1V)...38 Figure 4. I D vs. V DS for a 90nm nfet (W/L = 0 μm/0.1μm, V DS = 1V)...39 Figure 4.3 f T vs. V GS for a 90nm nfet (V DS = 1V) Figure 4.4 g m vs. V GS for a 90nm nfet (V DS = 1V)...41 Figure 4.5 g m /I D vs. V GS for a 90nm nfet (V DS = 1V)...4 Figure 4.6 r o (=1/g ds ) vs. V DS for a 90nm nfet (V DS = 1V) Figure 4.7 Intrinsic gain g m r o (= g m /g ds ) vs. V GS for a 90nm nfet (V DS = 1V)...44 Figure 4.8 NF vs. W of cascode and common-source amplifiers...45 Figure 4.9 Cascode amplifier. (a) Schematic, (b) Simplified small-signal model for input matching analysis Chapter 5 Figure 5.1 Schematic of a cascode amplifier...5 Figure 5. I D of a cascode LNA. (a) I D vs. V GS (W 1 =W =5μm), (b) I D vs. W (V GS =0.4V)...54 Figure 5.3 Voltage gain of a cascode LNA. (a) A v vs. V GS, (b) A v. vs. W Figure 5.4 NF of a cascode LNA. (a) NF vs. V GS, and (b) NF vs. W Figure 5.5 Noise contribution of the signal source and LNA components...57 Figure 5.6 IIP3 vs. V GS of the cascode LNA...58 Figure 5.7 P1dB vs. V GS of the cascode LNA Figure 5.8 π-model of a 5nH spiral inductor...59 Figure 5.9 Gain and NF of the proposed LNA...60 Figure 5.10 S 11 of the proposed LNA...61 Figure 5.11 Graphical illustration comparing recently published LNAs and this work...6 v

6 List of Tables Table 1 Summary of LNA component values...59 Table Summary of LNA performance...61 Table 3 Comparison of CMOS low-power LNAs...6 vi

7 Acknowledgment This work 1 could not have been completed without the help of many people and I would like to take this opportunity to express my appreciation to them. I would like to start by thanking my graduate advisor, Professor Shahriar Mirabbasi for his guidance and for always making decisions based on what is best for my education. This has led to not only a productive but also an enjoyable experience. I would like to thank Dr. Andre Ivanov for supervising my undergraduate research in the System-on- Chip lab, where I cultivated my early interest in VLSI circuits. I would also like to thank Professor Resve Saleh and Professor Steve Wilton for reading this dissertation and serving as committee members in my thesis defense. I could not imagine where I would be without the help of Roberto Rosales and Karim Allidina. They deserve special recognition for having the patience to explain to me any question that I threw at them. I probably would have gone insane without the companions at the SOC lab to listen to all my problems and give me advice (even though some advice was insane too). You know who you are: Usman Ahmed, Shirley Au, Nathalie Chan, Melody Chang, Scott Chin, 1 This research is funded by Natural Science and Engineering Research Council of Canada (NSERC). CAD tools are provided by Canadian Microelectronics Corporation (CMC) Microsystems. vii

8 David Chiu, Rod Foist, Amit Kedia, Sohaib Majzoub, Xiongfei Meng, Dipanjan Sengupta, and Howard Yang. I am sure I would be a different person without the influence of Wilson Fung and Jennifer Li. Being friends for more than a decade, Wilson and I grew up together. His commitment to doing good work has become my role model. Having a technical discussion with him is nothing less than inspiring. Jennifer and I have gone through both ups and downs. Her love is indispensable to my general well-being. Last but not least, I would like to thank my sister for putting up with me for as long as she has existed. I d also like to express my deepest gratitude to my parents for their unconditional love. They have made tremendous sacrifices to give me the best upbringing a child can possibly receive. Derek Ho Vancouver, BC viii

9 Chapter 1 Introduction Motivation The design of low-power wireless transceivers has gained substantial significance due to the explosion of wireless applications such as personal area networks and wireless sensor networks. These applications demand for small, low-cost, and low-power wireless transceivers which require a high level of integration with a minimal amount of off-chip components. The first active block in most wireless receivers is the low-noise amplifier (LNA). The LNA needs to amplify the signal without adding a large amount of noise and distortion while consuming minimal power. RF circuits have traditionally been implemented in compound semiconductor technologies such as Gallium Arsenide (GaAs) or Silicon Germanium (SiGe). Since the CMOS technology is employed for the digital transceiver back-end, it is attractive to implement the RF front-end also in CMOS, with the goal to integrate all parts of the receiver on a single chip to reduce cost and time to market. In the recent past, numerous CMOS RF circuits have been presented and have demonstrated good performance [1]-[4]. 1

10 The design of a power-efficient LNA in CMOS is particularly challenging due to a number of reasons: 1) The performance such as gain and bandwidth of a metal-oxide-semiconductor field-effect transistor (MOSFET) is poor when biased at the small drain current necessary for power-efficient operation. ) The choice of circuit topologies is limited due to the reduction of MOSFET output resistance and supply voltage as CMOS technology scales. 3) On-chip passive elements have poor quality factor, limited range of values, and large area consumption. 4) Conventional power-constrained noise optimization techniques [5] often lead to subthreshold operation when power consumption is restricted to 1mW or below. Research Objective The objective of this thesis is to develop a narrow-band RF CMOS LNA design technique suitable for the prevalent inductively degenerated LNA architecture. This work aims to achieve the following targets: 1) Devise a methodology that leads to a power-efficient LNA design. ) Explore the tradeoffs between LNA performance and power consumption. 3) Find a circuit topology capable of low-voltage low-power operation. 4) Demonstrate a high performance design with on-chip low-q passive components in a deep submicron technology.

11 In devising the design methodology, a major goal is to review, coordinate, and exploit several device-level properties proposed in the recent literature: 1) Device transit frequency f T and unity power gain frequency f MAX depend strongly on drain current density, which is mainly controlled by the gate-source voltage [6]. ) The MOSFET has a large transconductance per unit drain current g m /I D in weak inversion and progressively degrades towards strong inversion [7]. 3) The MOSFET minimum noise figure improves as gate length decreases [6], [8]. 4) MOSFET linearity improves as drain current density increases with a significant peaking in the moderate inversion region [9], [10]. As part of the overall objective, a.4ghz LNA is designed and simulated in a 90nm CMOS technology with sub-mw power consumption using the proposed design methodology. The simulation results demonstrate the applicability of the methodology to the design of narrow-band RF front-ends needed for many low-power applications. Thesis Organization In this thesis, an LNA design methodology is devised and documented. Chapter presents background information about two-port networks that is fundamental to the design of LNAs and other RF circuits. Chapter 3 focuses on the design of CMOS LNAs. Chapter 4 discusses the design of transistor biasing conditions for power-efficient amplifiers. This chapter concludes with a step-by-step design procedure. Chapter 5 3

12 details the application of the proposed methodology to the design of a sub-mw LNA. Simulation results are presented at the end of this chapter. Finally, Chapter 6 draws some conclusions and suggests future works. 4

13 Chapter Background To simplify the design and analysis of analog circuits, it is useful to abstract circuit blocks into two-port networks. This chapter begins with a discussion of parameters that are used to characterize two-port networks. Then, performance measures of the two-port network such as gain, noise, linearity, and stability that are important in the design of LNAs are presented. Two-Port Networks A two-port network is shown in Fig..1. There are usually two quantities, namely, voltage and current associated to each port. At low frequencies, two common representations that characterizes the network are the impedance matrix (Z parameters) and the admittance matrix (Y parameters) [11], [1]. Figure.1 Two-port network diagram. 5

14 The impedance and admittance matrices are defined by (.1) and (.), respectively. v v 1 Z Z 11 1 Z Z 1 i i 1 (.1) i i 1 Y Y 11 1 Y Y 1 v v 1 (.) Z parameters and Y parameters are particularly useful at low frequencies because they can be readily measured by applying either a test current or voltage to the input port and connecting the output port either as a short or open circuit. For example, from (.1) ν 1 can be expressed as v 1 Z11i1 Z1i. (.3) If the output port is open circuited, i becomes zero, and Z 11 can be calculated to be ν 1 /i 1. Impedance Matching A system with a signal source driving a load is depicted in Fig.. where Z S and Z L are the source and load impedances, respectively. Figure. A system with a source driving a load. 6

15 There are two types of impedance matching [13]. The first type of impedance matching concerns with minimizing signal reflection from the load back to the source. When Z S = Z L, there is no reflection. This is important for the design of the receiver front-end as the frequency response of the antenna filter that precedes the LNA deviates from its normal operation if there are reflections from the LNA back to the filter. The second type of matching concerns with maximum power transfer from the source to the load. Hence it is often referred to as power matching. Power matching occurs when the load impedance is the complex conjugate of the source impedance. When the source and load impedances are real as in a typical 50Ω RF system, the conditions for power matching and impedance matching are equal. Scattering Parameters At RF and microwave frequencies, Z and Y parameters become very difficult to measure due to the need for broadband short and open circuits [14]. As a result, a different representation of the two-port network is needed at these frequencies. A popular representation is the scattering, or S, parameters. Instead of relying on ports being open and short circuited, S parameters have the advantage that they can be measured by matching the source and load impedances to a reference impedance Z o. An S parameter representation of a two-port network is shown in Fig..3. Figure.3 S parameter representation of a two-port network. 7

16 The notion of the S parameter representation is to measure the normalized incident voltage wave a i entering the system at port i, as well as the corresponding reflected voltage wave b i leaving port i. The normalized incident and reflected voltage waves a i and b i are related to the terminal voltage and current at port i by the following equations: a i v Z i i o i (.4) Z o b i v Z i i o i (.5) Z o where Z o is assumed real as it is usually equal to 50Ω. The network of Fig..3 can be express, in matrix form, as (.6). b b 1 S S 11 1 S S 1 a a 1 (.6) where S 11, S 1, S 1, S are the scattering parameters. By expanding the scattering matrix, the following equations can be written: b 1 S 11 (.7) a1 a 0 b 1 S 1 (.8) a a1 0 b S 1 (.9) a1 a 0 b S (.10) a a1 0 where S 11 is interpreted as the ratio of the reflected voltage wave to the incident voltage wave at port 1 with the output port properly terminated. The condition for a port being 8

17 properly terminated is that the impedance looking into the port must match the characteristic impedance of the transmission line attached to it. Definitions for the rest of the S parameters can be interpreted analogously. Linearity Linearity is a key requirement in the design of an LNA because the LNA must be able to maintain linear operation in the presence of a large interfering signal and when the input is driven by a large signal [14]. Intermodulation linearity, characterized by the inputreferred 3 rd -order intermodulation intercept point (IIP3), is crucial to prevent the intermodulation tones created by a large interfering signal from corrupting the signal of interest. Large-signal linearity, characterized by the input-referred 1dB voltage compression point (P1dB), is important as it determines the maximum input level that can be amplified linearly, i.e. the upper bound of the dynamic range of the LNA. Harmonic Distortion The input V i and output V o of a two-port network can be related by a power series [15]: 3 V a V a V a V... (.11) o 1 i i 3 i where a 1, a, a 3 are constants. If the input is driven by a sinusoidal signal as follows, t V t V i 1 cos 1 (.1) where V 1 and ω 1 are the amplitude and frequency, respectively, then the output is equal to V o a V cos t a V t cos t V1 a 4 cos3 t 3cos t (.13) 9

18 The first term in (.13) is the linear term, and is the ideal output if the two-port network is completely linear. Other terms in (.13) are due to non-linearities, and they cause a DC shift as well as distortion at frequencies ω 1, 3ω 1, and higher harmonics, which result in either gain compression or gain expansion. It can also be observed from equation (.13) that distortion is present in any signal level. To quantify the amount of harmonic distortion, the following definitions are used: Amplitude 1 HD (.14) Amplitude 1 Amplitude3 1 HD3 (.15) Amplitude 1 where (.14) represents the fractional second harmonic distortion, and (.15) represents the third fractional harmonic distortion. Higher order fractional harmonic distortion definitions can be written in the same fashion. The above definitions for the second and third order fractional harmonic distortion can be written in terms of the coefficients of the power series and the input signal by examining (.13). a HD V1 (.16) a1 a 3 HD3 V1 (.17) 4a1 10

19 Intermodulation Harmonic distortion, introduced previously, is the result of non-linearities due to a single sinusoidal input. It is quite possible in practice that two or more sinusoidal signals are applied to the input of a two-port, for example, the first signal representing the input and others representing large in-band interferences at the input of an LNA. When this occurs, another non-linearity called intermodulation results. To see the effects of both harmonic distortion and intermodulation, assume that the input signal is now equal to t V cos t V t V i 1 1 cos (.18) The output can be expanded in a power series and (.18) can be substituted into (.11). The linear first term can be expressed as t V t a 1 V i a 1 V 1 cos 1 cos (.19) The second term is given by av1 a V a V i 1 av1v cos1 t cos 1 t cos t 1 cos t 1 (.0) Expanding the third term gives 3 3 a3v1 a3v i cos3 1 t 3cos 1 t 4 3 a3v cos3 t 3cos t 4 3 V1V cos 1t cos 1 t cos 4 3 V1 Vcos t cos 1 t cos 4 t a3 1 t a3 1 (.1) 11

20 It can be observed from (.0) and (.1) that harmonic distortion terms are produced as if each sine wave is applied separately. However, second order intermodulation terms are also produced at (ω 1 + ω ) and (ω 1 ω ), and third order intermodulation terms are produced at (ω 1 ± ω ), and (ω ± ω 1 ). Fig..5 shows the distortion terms in the frequency spectrum [1]. Figure.5 Frequency locations of distortion terms. The following two equations define fractional intermodulation: IM Amplitude 1 (.) Amplitude 1, IM 3 Amplitude, 1 1 (.3) Amplitude 1, Using the definitions in (.) and (.3), the fractional intermodulation terms are a IM (.4) V1 a1 3a 3 IM 3 V1 (.5) 4a1 1

21 where it is assumed that V 1 = V. From Fig..5, it is apparent that the 3 rd -order intermodulation distortion IM 3 signals are close to the signal of interest F, which makes the filtering out of IM 3 signals difficult when recovering the signal of interest. Therefore minimizing intermodulation distortion is a key objective in many RF circuit designs. 1 db Compression Point It is mentioned previously that the 3 rd -order term in the power series can either cause gain compression or gain expansion. If we assume that the sign between a 1 and a 3 are different, then gain compression occurs. P1dB is a measure of the power of the input signal such that it causes the 3 rd -order non-linearity to reduce gain by 1 db from the ideal value. It can be expressed as: 3a3 0 log 1 V1 1dB 4a (.6) 1 Solving for V 1 in (.6) gives: 4 a (.7) 3 a P db 3 3 rd Order Intercept Point Another measure for the 3 rd -order non-linearity in a two-port network is the 3 rd -order intercept point. Since the 3 rd -order non-linearity is proportional to the input signal cubed, while the fundamental is increasing only linearly with the input signal, there is a point at which the amplitudes of the fundamental and that of the 3 rd -order intermodulation product meet. The input signal at which this occurs is defined as the input-referred 3 rd - 13

22 order intercept point (IIP3), and is equal to when IM 3 equals 1. Solving for V 1 using (.5), the following equation for IIP3 is obtained. 4 a 3 a 1 IIP3 (.8) 3 Stability A critical requirement of a two-port network is that it must not produce an output with oscillatory behavior. The stability of a two-port network can be determined from its S- parameters and the load and source impedances. The Rollet stability factor, K, is often used for verifying stability [16]. Unconditional stability is satisfied under the following two conditions: K 1 (.9) 1 (.30) where K 1 S11 S (.31) S S 1 1 S (.3) 11S S1S 1 However, K alone is usually good enough to test for stability since most transistors are either unconditionally stable, satisfying (.9) and (.30), or conditionally stable with K < 1 and Δ < 1 [14]. 14

23 Noise in Two-Port Systems In order to design a circuit for low noise, it is useful to determine the condition under which noise can be minimized. This condition is then used in Chapter 3 to relate noise performance to CMOS design parameters. For the analysis of noise in two-port systems, consider a noisy two-port network driven by a noisy source as shown in Fig..5(a). (a) (b) Figure.4 Noise modeling. (a) Noisy two-port, (b) Input-referred noise model. The noise factor of a two-port network is defined as F SNR SNR IN n, output (.33) OUT P P n, source where P n,output is the noise power outputted by the two-port and P n,source is the noise presented at the input of the two-port. An ideal noiseless two-port network contributes no noise; hence the noise factor is equal to one. Noise figure NF, which is noise factor 15

24 expressed in decibel, often used to specify noise performance and has an ideally value of 0dB. To simplify analysis, the noise of a two-port network can be modeled as a noise voltage and a noise current at the input as shown in Fig..5(b). The signal source is represented by a current source i s in parallel with and an admittance Y s to simplify derivation. In this case, the noise factor can be expressed as [13]: F s in Ysvn i (.34) i s In the derivation of (.34), the assumption has been made that the noise from the source is not correlated to the noise from the two-port. However, since the exact nature of the source of the two-port is not known, the above assumption about correlation may not be reasonable. Therefore, the following definition for i n is needed: i n i i (.35) c u where i c is the portion of i n that is correlated with v n, while i u is the part of i n that is uncorrelated with v n. The current i c is equal to Y c v n, where Y c is known as the correlation admittance and is given by i c Yc (.36) vn 16

25 Equation (.34) contains independent noise sources, each of which may be treated as thermal noise produced by an equivalent resistance or conductance: R G G n u s vn 4 ktf iu 4 ktf is 4 ktf (.37) (.38) (.39) where k is Boltzmann s constant (about J/K), T is the absolute temperature in kelvins, and Δf is the noise bandwidth in hertz. Using (.36) (.39), the noise factor can be expressed purely in terms of impedances and admittances: F s Gu Gc Gs Bc Bs Rn 1 (.40) G To optimize for noise in a circuit, the minimum noise factor can be solved for by first taking the derivative of (.40) with respect to the source conductance and susceptance and setting them to zero. The results for the optimal source conductance and susceptance are stated below. B B s, opt c (.41) G G (.4) u s, opt Gc Rn Substituting (.41) and (.4) into (.40) gives the following results for the minimum noise factor. F min Rn Gs, opt c 1 G (.43) 17

26 The noise factor can then be expressed in terms of F min and the source admittances by F Rn Fmin Gs Gs B, opt s Bs, opt (.44) Gs The above analysis shows that a source impedance optimized for a minimum noise factor exists, but this source impedance is often not the same as the impedance that achieves maximum power transfer. In (.44), the ratio R n /G s appears as a multiplier in front of the second term. For a fixed source conductance, R n represents the sensitivity of the noise factor as G s and B s departs from their optimal values. A large R n implies a high sensitivity, which obligates the design to stay close to optimal noise matching. As discussed subsequently, operation at low bias currents is associated with large R n, mainly due to small device transconductance g m. This is an example of the difficulty in achieving high performance at low power consumption. 18

27 Chapter 3 CMOS LNA Fundamentals This chapter describes the theories and considerations useful to the implementation of an LNA in the CMOS technology. Noise Sources in CMOS Before beginning an analysis of how to design for low noise, the origins of the noise should be identified and understood. This section discusses several important noise sources in CMOS transistors. Thermal Noise Figure 3.1 MOSFET small-signal model with thermal noise. Thermal noise is due to the random thermal motion of the carriers in the channel [17]. It is commonly referred to as a white noise source because its power spectral density holds a constant value up to very high frequencies (over 1 THz) [13]. Thermal noise can be 19

28 modeled as a current source across the drain and source of a transistor, as depicted in Fig. 3.1 [1], and has a power spectral density of i d f 4kTg ds0 (3.1) where k is Boltzmann s constant, T is the absolute temperature, γ is a bias dependent process parameter, and g ds0 is the zero-v DS drain-source conductance, and has the following definition: g m (3.) g ds0 where g m is the transconductance and α is typically in the range between 0 and 1. Equation (3.1) is a general equation that can be used in both the linear and saturation regions of operation simply by using different values for γ. For long channel transistors, γ = /3 in the saturation region, and γ = 1 in the linear region. For short channel transistors, hot carrier effects may cause γ to be as high as or 3 [18]. Induced Gate Noise Induced gate noise is a high frequency noise source that is caused by the non-quasi static effects influencing the power spectral density of the drain current [17]. Thermal noise in the channel couples through the oxide capacitance to the gate terminal, causing a gate noise current to flow. This noise source is normally not included in standard noise analysis because at low frequencies it is negligible. However, it can dominate at RF 0

29 frequencies [13]. Induced gate noise, with its circuit model shown in Fig. 3.(a), has a power spectral density given by i g f C 4kT 5g gs ds0 (3.3) where ω is the frequency, C gs is the gate-source capacitance, and δ is a process parameter equal to 4/3 in long channel devices [17]. Since the thermal channel noise and induced gate noise stem from the same physical phenomenon, it can be assumed that the relation δ = γ continues to hold for short channel devices [13]. (a) (b) Figure 3. Induced gate noise model. (a) Frequency dependent, (b) Frequency independent. The power spectral density of (3.3) is frequency dependent. An equivalent frequency independent noise model is to express the induced gate noise as a voltage in series with the gate capacitance, as shown in Fig. 3.(b). If a high quality factor Q is assumed, then 1

30 the models shown in Fig. 3.(a) and (b) are equivalent, and (3.4) gives the power spectral density. v g f 4kTr g (3.4) Equation (3.4) shows the interesting result that the gate noise is equal to the noise of r g, a resistor placed at the gate, scaled with the constant δ. As discussed previously, gate noise and drain noise are partially correlated due to the fact that they are from the same source. The correlation coefficient c can be expressed as in (3.5): igid * c (3.5) i g id The theoretical value for c is 0.395j for long channel devices [17]. Precise measurements of c are difficult to carry out, but the best published measurements reveal that its magnitude stays within a factor of of this theoretical value, even for devices with drawn channel lengths as small as 0.13μm [13]. Distributed Gate Noise The distributed gate resistance of the CMOS transistor also contributes to the noise figure of an LNA. This noise source is modeled as a resistor at the gate and has a noise power spectral density equal to v g f 4kTR g (3.6)

31 where Rg is the gate resistance, and is given by R RsqW (3.7) 3n L g In (3.7), R sq is the sheet resistance of the gate material, n is the number of fingers, and the factor 1/3 results from the assumption that each finger is only contacted at only one end. If both ends are contacted, then the factor reduces to 1/1. Intrinsic MOSFET Two-port Noise Parameters In chapter, the expression for the noise factor is derived, herein reproduced as (3.8) for convenience. F Rn Fmin Gs Gs B, opt s Bs, opt (3.8) Gs Viewing the MOSFET as a two-port network, with the gate and source forming a port and the drain and source forming another, it is useful to express F min, R n, G s,opt, and B s,opt in terms of MOSFET device parameters [13]: F min 1 (1 c 5 T ) (3.9) R n g (3.10) g d 0 m G C gs (1 ) (3.11) 5 s, opt c B s, opt C gs 1 c (3.1) 5 3

32 This completes the noise analysis that relates the noise factor with design variables g m, ω, C gs, and g d0. Examining (3.9) (3.1), W can also be related to the four noise parameters, which permits noise consideration in transistor sizing. F min no width dependence (3.13) R n 1/W (3.14) G opt W (3.15) B opt W (3.16) Aside from the classical noise matching (CNM) presented above, a number of CMOS LNA design optimization techniques are also well established such as simultaneous noise and input matching (SNIM), power-constrained simultaneous noise and input matching (PCSNIM), and power-constrained noise optimization (PCNO). A good overview of these techniques is presented in [5]. Inductive Source Degeneration An LNA must provide an input matching to a typically 50Ω element such as a bandselect filter or an antenna. In a fully integrated receiver, LNA output matching is often not required as it is connected to the next on-chip stage in the receive chain. To minimize the number of off-chip components, an LNA should implement the elements required for input matching on chip. One popular approach is to use inductive degeneration. 4

33 Input Impedance Match Input impedance matching by inductive source degeneration is popular as matching to the signal source does not introduce additional noise (as in the case of using a shunt input resistor) and does not restrict the value of g m (as in the case of the common-gate configuration). Figure 3.3 Inductive source degeneration. The circuit shown in Fig. 3.3 has an input impedance equal to Z in jl L s g 1 jc gs g ml C gs s (3.17) where ideal inductors and capacitors have been assumed. From (3.17), in order to achieve an input impedance match, the following condition must be satisfied: R s g L m s T Ls (3.18) C gs where ω T g m /C gs is the transit frequency of the transistor. Once L s is chosen based on gain, linearity and input matching requirements, L g can then be chosen such that L g, L s, and C gs resonate at ω 0. In other words, the following condition for L g must hold: 1 0 (3.19) (L L ) C g s gs 5

34 Circuit Transconductance Transconductance is important for gain. To find the transconductance G m of the circuit shown in Fig. 3.3, first note that the input matching network forms a series RLC tank. The Q of the tank is Q in 0 R s 1 g m L C gs s C gs (3.0) where ω 0 is the resonant frequency defined in (3.19). At resonance, the voltage across the capacitor is equal to v Q v (3.1) gs in s and the short circuit output current is equal to i g v (3.) out m gs where g m is the transconductance of the device. Using (3.0) (3.), the overall circuit transconductance can be solved for, and is given by the following equations: G m 0 R s g m g m L C gs s C gs (3.3) T 0 R s 1 L T s (3.4) It can be observed from (3.4) that G m is dependent on CMOS process technology through the transit frequency. 6

35 Circuit Topologies The key specifications for characterizing the performance of an integrated LNA are gain, noise, linearity, power consumption, stability, and input matching. These specifications depend on the circuit topology. Topologies such as common-source, common-gate, cascode, and distributed amplifiers have been used for different performance requirements. Compared to the common-source configuration, common-gate is more suitable for wide-band operation, but suffers from relatively high NF [19]. Distributed amplifiers are also capable of wide-band operation, but they suffer from relatively high power consumption [0]. (a) (b) Figure 3.4 Narrow-band topologies. (a) Common-source, (b) Cascode. For narrow-band operation, which is the focus of this work, the common-source and cascode amplifiers are the most suitable. In the common-source configuration, as shown in Fig. 3.4(a), the signal is applied to the gate and the output is taken from the drain. The cascode amplifier is a common-gate amplifier stacked on top of a common-source 7

36 amplifier, as shown in Fig. 3.4(b). The cascode amplifier consists of an input transistor M 1 and a cascode transistor M with a gate bias voltage V B. Compared to the cascode amplifier, the common-source amplifier suffers from the following shortcomings: 1) Poor isolation between input and output, due to the gate-to-drain parasitic capacitance C gd, increases the chance of instability significantly. ) As CMOS technology scales, the MOSFET output resistance r o decreases, causing noticeable performance degradation. For a common-source amplifier, r o appears in parallel with the load impedance in small-signal operation, which reduces the output impedance, and lowers the gain of the LNA. A possible solution is to increase the gate length L, which results in a degradation of NF. To alleviate the shortcomings of the common-source topology, the cascode topology is often used. The addition of the cascode device reduces the effect of the C gd of M 1 by presenting a low impedance node at the drain of M 1, improving stability. The cascode device also performs impedance transformation so that the output impedance of the amplifier is improved by a factor approximately equal to the intrinsic gain of the cascode device. The load inductor, L d, is designed to resonate at the operating frequency with the output node capacitance. The input and output tanks can be aligned to provide a narrowband gain, but can also be offset from each other to provide a broader and flatter frequency 8

37 response. One shortcoming of the cascode topology is that the extra transistor consumes voltage headroom. As a result, the load should not consume a large voltage headroom. An inductive load L d, as opposed to a resistive load, is preferred. An inductive load has the added benefit of increasing the gain by resonating with the capacitances associated with the output node and also improving frequency selectivity. Since on-chip inductors have a limited range of values, the capacitor C m of Fig. 3.4(b) can be added between the gate and source terminals of M 1 so that the values of L g and L s are reduced to permit on-chip implementation. Reducing the inductor value also improves Q, which reduces input losses and improves LNA noise figure. Adding C m has another advantage of providing an extra degree of freedom for choosing the gate width W of M 1, which decouples impedance matching requirements from power consumption. A drawback of adding extra gate-to-source capacitance is the degradation of f T of M 1. However, as discussed subsequently, at operating frequencies well below f T, this trade-off is reasonable. It is also interesting to note that adding C m does not degrade distortion performance [10]. Performance of the Cascode Amplifier Since the cascode amplifier depicted in Fig. 3.4(a) is a robust topology for narrow-band applications, a detailed study of its gain, noise, and linearity performance is provided in this section. 9

38 30 Voltage and Power Gain Assuming the LNA is input matched, the voltage gain and power gain can be expressed as (3.5) and (3.6), respectively [17]. s L T v R R A 0 (3.5) s L T avs L T R R P P G 0 (3.6) where R L is the resistance at the output due to the finite Q of L d and the finite output resistance of the transistor, and R s is the impedance of the signal source. Noise The noise factor F of the LNA can be expressed as [1] 0 1 T s m s g R g R R F (3.7) F can be expressed in a more intuitive form if power/impedance matching is assumed at the input (which is often the case). The derivation is done in [1], and the result is repeated below: s m s m T R g c R g F (3.8) where the portion of the gate noise that is correlated with the drain noise has been neglected. In (3.8), the second term is the contribution from the channel drain noise, and the last term is the contribution from the uncorrelated portion of the gate noise. It can be

39 observed that as ω T increases (for example with improving technology), the drain noise contribution becomes less significant if the operating frequency is kept constant. Linearity A purely sinusoidal input signal can produce a distorted output signal with higher-order harmonics due to the nonlinearity of the MOSFET. These harmonics are mainly induced by higher-order derivatives of the current-voltage (I D -V GS ) characteristics. An important figure of merit for linearity is the 3 rd -order harmonic intercept voltage VIP3, which is the extrapolated input voltage amplitude at which the 1 st - and 3 rd -order output amplitudes are equal. The input-referred VIP3 can be expressed as [9]: g m VIIP3 4 (3.9) g m3 For linearity, VIP3 is used as a key design parameter and its value is representative of the input signal amplitude that the system can process with reasonably low distortion. It can be obtained by taking the third derivative of the I D -V GS characteristics in respect to V GS. Figure 3.5 gives the VIP3 as a function of gate bias V GS under different values of drain bias V DS []. A sharp peak is observed near the threshold voltage as gate bias is varied, which reflects the so called sweet spot of gate biases for high MOSFET linearity [9]. This is because, during the transition from subthreshold to strong inversion, the increase of g m with V GS is at its highest, and the nd -order nonlinearity coefficient g m reaches its peak, while the 3 rd -order nonlinearity coefficient g m3 becomes zero. 31

40 Figure 3.5 VIP3 of a 40nm nfet vs. V GS for different V DS (V TH = 0.3V) []. At the system level, the input 3 rd -order intermodulation point (IIP3) of the cascode amplifier can be written as [] IIP3[ dbm] IIP3 [ dbm] 0 log 1 in 10 (3.30) 0C gs Rs The first term in (3.30) is the intrinsic IIP3 of the device, and arises from the fact that short channel CMOS transistors exhibit velocity saturation, which gradually linearizes the ideal quadratic relationship of the long channel drain current equation. The second term results from the extra voltage boost across the C gs due to the series resonance tank, which increases gain but degrades IIP3. This outlines a tradeoff between gain and linearity. 3

41 Inductor Design Inductors are widely used in RF circuitry to resonate with capacitors and to provide impedance transformations. The design of on-chip inductors is important as the inductor may dominate the frequency selectivity of a RF circuit and consumes a large area. The frequency selectivity of an inductor, characterized by the quality factor Q, is a major design parameter to be optimized. As evident in the following subsections, there is a tradeoff between Q, practical inductance values, and inductor area. Physical Dimensions On-chip inductors can be implemented in different shapes such as squares, octagons, and circles. The layout of a square spiral inductor is depicted in Fig Figure 3.6 The layout of a square spiral inductor. 33

42 Although it may seem counterintuitive, the Q depends very little on the shape [13]. Instead, it mainly depends on the following parameters: N D W S T The number of turns in the spiral The inductor s inner radius (For a square spiral, D is the shortest distance between the center and the inner side of the spiral) The width of the wire The spacing between two wires The thickness of the wire. Once the metal layer is chosen, T is fixed. Inductor Figures of Merit In this section, three common figures of merit used to describe the characteristics of an inductor are discussed: inductance, quality factor, and self-resonant frequency. A. Inductance The calculation of the inductance of a structure is based upon the self-inductance of a conductor, and the mutual inductance between two conductors [3]. The total inductance of a spiral structure is equal to the sum of all of the self-inductances of the wire segments and the positive and negative mutual inductances between the wire segments. Two segments have a positive mutual inductance if the direction of current flow in them is the same and a negative mutual inductance if the direction of current flow in them opposes each other. Inductance calculation is often complicated and is best performed by a computer simulation program such as ASITIC [4]. 34

43 B. Quality Factor The quality factor Q is a measure of the amount of energy loss in a circuit component or network and has implications on their frequency selectivity. It is defined as Energy _ stored 0 Q (3.31) Energy _ dissipated BW where ω 0 and BW are the resonant frequency and bandwidth, respectively, of the component or network. An ideal inductor has a Q of infinity. When the loss is significant (caused by for example interconnect resistance, substrate loss, and the skin effect), the peaking of a signal at resonance degrades, which in turn lowers the amplifier gain. The degradation of the frequency selectivity, which results in a large BW may be undesirable as, for example, an LNA should ideally reject out-of-band signals while only amplifying the signal of interest. The quality factor can be improved by adding a patterned ground shield between the inductor and the substrate to reduce capacitive coupling [5]. C. Self-Resonant Frequency The self-resonant frequency is the frequency at which the inductor resonates with its own parasitic capacitance. Below the self-resonant frequency, the inductor behaves like an inductor, at the self-resonant frequency the inductor behaves like a resistor, and above the self-resonant frequency, the inductor behaves like a capacitor. In general, a physically larger inductor tends to have a lower self-resonant frequency [13]. Therefore, the requirement that the inductor operates at most at half its self-resonant frequency places a limit to the size of the inductor. 35

44 Inductor Modeling Inductors can be modeled with an electromagnetic field solver tool such as ASITIC. A frequency-dependent π model as shown in Fig. 3.7 can be used for narrow-band applications. R models the resistance of the interconnect, L models the inductance, C s and R s respectively model the capacitance and resistance from the inductor metal to the substrate. Figure 3.7 Pi-model of inductor. 36

45 Chapter 4 Designing for Power-Efficient Operation The main objective of this work is to create a design methodology for power-efficient LNAs that can operate at sub-mw power consumption levels. This chapter describes device biasing and sizing, the two fundamental design steps, and presents a step-by-step design procedure. The following discussion is illustrated with a collection of graphs that relate device characteristics such as transconductance and power consumption to circuit design parameters such as gate voltage V GS and gate width W. These graphs offer perspectives to explore the design space particularly useful for selecting the biasing condition for the amplifier, which is the first step of the proposed design procedure. Data from the graphs has been obtained from SpectreRF simulations using a commercial 90nm process design kit. Device Biasing Since circuit performance is strongly tied to device biasing and that proper biasing involves knowledge of device characteristics, it is important to incorporate the knowledge of the device from the beginning of the design cycle to minimize parameter tuning at the end. 37

46 Terminal I-V Characteristics /0.1 40/0.1 40/0. 0 ID [ma] VGS (V) Figure 4.1 I D vs. V GS for a 90nm nfet (V DS = 1V). Figure 4.1 shows the drain current of a 90nm nmosfet as a function of its gate voltage for three transistor sizes, specified in units of micrometers. In this process, the threshold voltage V TH is around 0.35V. All results thereafter are based on such an nmosfet. It is apparent that deep submicron effects such as velocity saturation occur at V GS > 0.6V, rendering the I D -V GS curve more linear as opposed to quadratic. This suggests that linearity of a circuit can be improved with a strong gate bias voltage. Also evident from Fig. 4.1 is that I D is proportional to the transistor width W for a given length L. However, according to the square law, transistor sizes 0/0.1 and 40/0. should have the same current, which is not the case for this 90nm nfet. With the aid of this graph, the designer can evaluate the extent of the deviation of the I-V relationship from the classical model. 38

47 6 V GS = 0.7V 5 ID [ma] 4 3 V GS = 0.6V V GS = 0.5V V GS = 0.4V 1 V GS = 0.3V V DS [V] Figure 4. I D vs. V DS for a 90nm nfet (W/L = 0 μm/0.1μm, V DS = 1V). The ability for a transistor to function as a robust current source is crucial to amplifier design. Fig. 4. shows the drain current characteristics of a 90nm nfet. For a given V GS, I D is plotted as a function of V DS. This plot explicitly reveals channel length modulation, evident by the dependency of I D on V DS when the transistor operates in saturation. Channel length modulation manifests itself as non-linearity and gain reduction at the circuit level. If the power consumption of a MOSFET is indicated by the product of I D and V DS, then a set of constant power contours, which is also depicted in Fig. 4., can be plotted in the I D - V DS design space. The plot shows three power levels at 0.1, 0.5, and 1mW, with the lower left corner representing a region of lower power consumption. The intersection of power contours and I D -V DS curves provides different combinations of V GS, V DS, and I D, which in turn facilitates the choice of power-constrained bias selection. 39

48 Gain and Transconductance Transit Freq. (GHz) /0.1 40/0.1 40/ VGS [V] Figure 4.3 f T vs. V GS for a 90nm nfet (V DS = 1V). The cut-off frequency f T, also called transit frequency, has been widely used as a measure of operating frequency of the device. It is defined as the frequency at which the current gain of the device is equal to unity and is given by f T g m (4.1) ( C C ) gs gd Figure 4.3 illustrates f T as a function of V GS for different transistor sizes. The curves for transistor sizes 0/0.1 and 40/0.1 overlap, indicating that f T for a fixed L is not a function of W. It can be inferred from (4.1) that the increase in transconductance g m that results from increasing W is offset by the increase in parasitic capacitances. Also evident from Fig. 4.3 is that f T is relatively low at a low V GS, which is necessary for power-efficient operation, and since a high f T is necessary for a low noise figure, a tradeoff is needed between noise and power. Also, f T is degraded when the device operates in the subthreshold region and when non-minimum L is used. 40

49 /0.1 40/0.1 40/0. gm [ms] VGS [V] Figure 4.4 g m vs. V GS for a 90nm nfet (V DS = 1V). The transconductance g m of a device is important to amplifier design as the gain of an amplifier is the product of its transconductance and output resistance. Fig. 4.4 depicts g m as a function of V GS. g m is obtained by differentiating the DC drain current I D with respect to V GS. g m increases rapidly with V GS until it saturates at a V GS well above V TH. To relate device performance with power consumption, it is useful to define transconductance efficiency g m /I D [7]. Fig. 4.5 shows g m /I D as a function of V GS. 41

50 /0.1 40/0.1 40/0. gm/id [1/V] VGS (V) Figure 4.5 g m /I D vs. V GS for a 90nm nfet (V DS = 1V). As can be seen, g m /I D is, to the first order, invariant across transistor sizes, indicated by the overlapping of the curves for the L=0.1um cases and that g m /I D is insensitive to W when the device is turned on. The fact that g m /I D is independent from transistor size is significant as this removes transistor size from the power efficiency optimization equation, leaving V GS as the primary variable to be considered. This means that circuit design that optimizes transconductance efficiency can be broken down into two sequential steps: first determining bias condition for maximum efficiency, then sizing transistors based on the absolute power requirement. As shown in Fig. 4.5, to exploit the high g m /I D, it is ideal to bias the transistor in the subthreshold region. However, as previously shown in Fig. 4.3, f T in this region may be insufficient. A good compromise is to operate in moderate inversion. 4