Advanced CMOS Technology Scaling Can Space Parts Catch Up?

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1 Advanced CMOS Technology Scaling Can Space Parts Catch Up? Dr. Douglas Sheldon All rights reserved.

2 Space parts ~0.01% of Total IC Market

3 Semiconductor manufacturers 62% of TSMC s wafer revenue from 65nm processes and below

4 Space vs. Modern COTS Space COTS Standards Based Screening Post manufacture testing Vendor certification Design rule and tool improvement Continuous Defect reduction Vendor audit Acceptance sampling Six sigma quality

5 1,584 Satellites 1990 to 2008 Failure => results in retirement of the satellite Reliability continues to decrease there is no flat region and the reliability never gets better Large satellites (>2,500 kg) have the worst reliability

6 Significant Spacecraft Anomalies Mars Reconnaissance Orbiter Space grade parts still represent ~20% failures There is requirement for additional improvement Bayer 2009

7 CMOS Scaling

8 One node = more than one option

9 CPU vs. SoC process SoC process has more interconnect layers with different design rules => additional reliability concerns

10 Speed vs. Distance Packaging Must Evolve Radius of circle = distance single clock cycle can effectively propagate

11 Need for Wide I/O

12 More than Moore Scaling Diversification vs. Miniaturization Moore s Law addresses increases in digital content in devices Higher value, complex systems also must address analog, RF, passives, power, and sensors New packaging technologies are the means to accomplish this

13 Evolution of chip/ic packaging Space Parts

14 Overall packaging trends Space must continue to adopt new packing technologies or risk obsolescence/unavailability

15 3D Package Integration High I/O count

16 Progression of 3D Technology

17 3D vs 2D Shorter lines = Better Performance

18 Through Silicon Vias (TSV) Complexity that is coming quickly 3D stacking is way to integrate together chips of dissimilar process technology that may be impractical to implement on a single piece of silicon.

19 RF Benefits from Scaling Inductor Q factor vs frequency: Integrated SIP Wire bond

20 Heterogeneous Package/Device Structures

21 Evolution of Device/Packaging Scaling

22 Details of Packaging Quad core ARM 9 Cortex processor chip; face to face with it is a Samsung 1-Gb wide I/O SDRAM; and the top three dies comprise two Samsung 2-Gb mobile DDR2 SDRAMs, separated by a spacer die, and conventionally wire-bonded. The base die is ~250 µm thick, and the others ~ µm

23 Generic Specification vs. Mission Specific testing Bigger die and bigger packages have less capability in terms of total number of temp cycles

24 New packaging structures failures do not scale linearly Cycles to failure - 40C to 125C Elimination of leaded devices => Lower RC and higher package densities => Reduces # of temp cycles to failure More silicon, less plastic => Increases mismatch in coefficient of thermal expansion (CTE)

25 New Qualification Issues Different vendors = different processes. Many materials interfaces = new physics of failure COTS success criteria Space criteria

26 BGA Materials Interactions Scott Poplar - Aeroflex

27 TID is limited concern for modern COTS N.S. Saks

28 COTS emphasis on neutron radiation Decrease in SRAM cell Qcrit with process shrinks balanced by decrease in cell area, leading to flat soft error rate trend. Dramatic increase in SRAM bit density/part causes trend to go up slightly DRAM cell upset soft error rate trending downwards because Qcrit flat but cell area shrinking Upset of control logic in DRAM becoming more significant

29 Multiple Bit Errors

30 Failure types in SRAMs Hard fails are being reduced as processes have reduced defect densities Soft (voltage sensitive) failures increase due to reduced margins Failure to write the cell Signal margin fails which are driven primarily by slow bits that are otherwise stable and have write margin Read stability fails for cells in the read or half-selected state Retention fails. Manufacturers have to add new read and write assist circuit designs and innovative redundancy schemes to address performance issues.

31 Electrical Testing Must Increase in Sophistication

32 Shmoo plots to understand device performance.vs. Both parts pass normal test conditions (100nsec/Vdd_min/nom/max) RHS fails very low voltage screen

33 Technology Obsolescence 3% of global pool of electronic components become obsolete every month 50 product discontinuances every day. Legacy parts and technology planning become a much more critical concern Heritage/legacy design success can no longer be easily assumed to be implementable Sanborn 2010

34 34 National Aeronautics and MSL - Curiosity

35 Under the Hood Avionics Environmental Design Challenges, HARSH2013 J. Donaldson, R. Manning, D. Sheldon 35

36 FPGA Use on Curiosity 93 FPGAs in use on MSL (both rover and cruise/descent stages) o Includes redundant design implementation and re-use RTAX2000, RTSX72U, and XQR2V3000 o First use of a reprogrammable FPGA in mission critical radar and radio applications Used in all aspects of operation o Avionics Command and Data Handling Communication Power management and control Motor Control o Science Instruments Hardware acceleration

37 Interfaces to: o o o o o o Ten science instruments Sample FPGA Use in MSL Avionics Attitude Control Systems: IMUs, Star Scanners, Sun Sensors 4 different radios (2 UHF radios and 2 X-band radios) that support uplink commands and downlink data Two separate fully redundant 1553B buses to support commanding and collecting sensor data from Radios, MCAs, and Power/Analog Modules on the S/C Motor and thruster actuators Engineering Cameras Manage volatile/non-volatile memory allocations that support flight software images and data products Power regulation, control and switching Sleep & wakeup functionality along with dream mode Battery charge and discharge control Pyro firing capability Analog telemetry (voltage and temperature measurement) sampling and collection 37

38 Terminal Descent Sensor/Radar Antenna Design on Mars Landing Radar, M. Guler, IEEE AESS/GRSS

39 Terminal Descent Sensor/Radar FPGAs Antenna Design on Mars Landing Radar, M. Guler, IEEE AESS/GRSS Ka-Band/Pulse Doppler Radar: Primary Navigation Sensor from the Point of Heat Shield Separation o o o o Provides exact Altitude and Velocity Data Capable of measuring Terrain Relative Velocity 6 independent Radar Beams: 3 beams canted 20 deg. 2W peak power, 20Hz update rate, 4ns-16usec pulse width XQR2V3000 provides a digital interface to/from the RF electronics and implements radar processing algorithms. RTSX-72SU provide low-level control functions: clocks generation/distribution, internal resets generation/distribution, 1553 interface, and XQR2V3000 configuration and scrub.

40 How This Relates to CMOS Scaling MSL represents that state of the art in interplanetary rovers Significant complexity of operation required almost nm node o SWaP remains a key design issue for next generation Could a 10X reduction in SWaP be possible with highly scaled CMOS (>65nm) devices and packages? o Resulting fault-containment architecture may/may not become more complex and more difficult to design, analyze, and verify than either a single-string or fully redundant designs o Highly scaled devices imply many functions are integrated into one FPGA/SoC Historical test methods are serial, not parallel as now required for highly integrated devices. o Functional Coverage vs. Code Coverage vs. Functional Simulation How and who determines when testing is complete and what the definition is

41 Summary Commercial scaling technologies offer improvements in size, power, performance that will be required for next generation missions Demands for increased scientific data product quantity and quality require use of COTS parts Space architectures are different than telecom or consumer architectures. Graceful degradation and fault tolerant system solutions will be increasingly required over the entire spacecraft New materials, interfaces and physics will challenge historical part qualification schemes. Mission specific/custom qualification trends will increase