M27C K (64K x 8) UV EPROM and OTP EPROM

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Corey Malone
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(PRSTO IIB ALGORITHM) 28 FDIP28W (F) 28 PDIP28 (B) DSCRIPTION The M27C52 is a high speed 524,288 bit UV erasable and electrically programmable PROM ideally suited for applications where fast

1 52K (64K x 8) UV PROM and OTP PROM FAST ACCSS TIM: 45ns LOW POWR CMOS CONSUMPTION: Active Current 30mA Standby Current 00µA PROGRAMMING VOLTAG: 2.75V LCTRONIC SIGNATUR for AUTOMATD PROGRAMMING PROGRAMMING TIMS of AROUND 6sec. (PRSTO IIB ALGORITHM) 28 FDIP28W (F) 28 PDIP28 (B) DSCRIPTION The M27C52 is a high speed 524,288 bit UV erasable and electrically programmable PROM ideally suited for applications where fast turnaround and pattern experimentation are important requirements. Its is organized as 65,536 by 8 bits. The Window Ceramic Frit-Seal Dual-in-Line package has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C52 is offered in Plastic Dual-in-Line, Plastic Thin Small Outline and Plastic Leaded Chip Carrier packages. PLCC32 (C) Figure. Logic Diagram VCC 6 A0-A5 TSOP28 (N) 8 x 3.4mm 8 Q0-Q7 Table. Signal Names GVPP M27C52 A0 - A5 Address Inputs Q0 - Q7 Data Outputs Chip nable GVPP V CC Output nable / Program Supply Supply Voltage VSS AI0076B VSS Ground June 996 /5

2 Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections A5 A2 A7 A6 A5 A4 A3 A2 A A0 Q0 Q Q2 VSS M27C AI00762 VCC A4 A3 A8 A9 A GV PP A0 Q7 Q6 Q5 Q4 Q3 A6 A5 A4 A3 A2 A A0 NC Q0 9 A7 A2 A5 DU VCC A4 A3 Q Q M27C52 VSS DU Q3 Q4 Q5 25 A8 A9 A NC GVPP A0 Q7 Q6 AI00763 Warning: NC = Not Connected, DU = Don t Use Figure 2C. TSOP Pin Connections GVPP A A9 A8 A3 A4 VCC A5 A2 A7 A6 A5 A4 A M27C AI00764B A0 Q7 Q6 Q5 Q4 Q3 VSS Q2 Q Q0 A0 A A2 DVIC OPRATION The modes of operations of the M27C52 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GV PP and 2V on A9 for lectronic Signature. Read Mode The M27C52 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip nable () is the power control and should be used for device selection. Output nable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (t AVQV ) is equalto the delay from to output (t LQV ). Data is available at the output after a delay of tglqv from the falling edge of G, assuming that has been low and the addresses have been stable for at least tavqv-tglqv. Standby Mode The M27C52 has a standby mode which reduces the active current from 30mA to 00µA The M27C52 is placed in the standby mode by applying a CMOS high signal to the input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input. 2/5

3 Table 2. Absolute Maximum Ratings () Symbol Parameter Value Unit TA Ambient Operating Temperature 40 to 25 C TBIAS Temperature Under Bias 50 to 25 C TSTG Storage Temperature 65 to 50 C V IO (2) Input or Output Voltages (except A9) 2 to 7 V VCC Supply Voltage 2 to 7 V V A9 (2) A9 Voltage 2 to 3.5 V V PP Program Supply Voltage 2 to 4 V Notes:. xcept for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. xposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SUR Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC voltage on Output is V CC +0.5V with possible overshoot to V CC +2V for a period less than 20ns. Table 3. Operating Modes Mode GVPP A9 Q0 - Q7 Read VIL VIL X Data Out Output Disable VIL VIH X Hi-Z Program V IL Pulse V PP X Data In Program Inhibit VIH VPP X Hi-Z Standby V IH X X Hi-Z lectronic Signature V IL V IL V ID Codes Note: X=V IH or V IL, V ID = 2V ± 0.5V Table 4. lectronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q Q0 Hex Data Manufacturer s Code VIL h Device Code V IH Dh Two Line Output Control Because PROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the RAD line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 3/5

4 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times 0ns 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages.5V 0.8V and 2V Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit High Speed 3V.3V N94.5V 0V 3.3kΩ Standard 2.4V 2.0V DVIC UNDR TST OUT C L = 30pF or 00pF 0.4V 0.8V AI0822 C L = 30pF for High Speed C L = 00pF for Standard C L includes JIG capacitance AI0823 Table 6. Capacitance () (TA =25 C, f = MHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance VIN = 0V 6 pf C OUT Output Capacitance V OUT =0V 2 pf Note.. Sampled only, not 00% tested. System Considerations The power switching characteristics of Advanced CMOS PROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.µF ceramic capacitor be used on every device between VCC and V SS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supplyconnection point.the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 4/5

5 Table 7. Read Mode DC Characteristics () (T A = 0 to 70 C, 40 to 85 C or 40 to 25 C; V CC =5V±5% or 5V ± 0%; V PP =V CC ) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC ±0 µa I LO Output Leakage Current 0V V OUT V CC ±0 µa ICC Supply Current =V IL,G=V IL, I OUT = 0mA, f = 5MHz 30 ma ICC Supply Current (Standby) TTL = VIH ma I CC2 Supply Current (Standby) CMOS > V CC 0.2V 00 µa I PP Program Current V PP =V CC 0 µa V IL Input Low Voltage V V IH (2) Input High Voltage 2 V CC + V VOL Output Low Voltage IOL = 2.mA 0.4 V V OH Output High Voltage TTL I OH = ma 3.6 V Output High Voltage CMOS IOH = 00µA VCC 0.7V V Notes:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is V CC +0.5V. Table 8A. Read Mode AC Characteristics () (TA = 0 to 70 C, 40 to 85 C or 40 to 25 C; VCC =5V±5% or 5V ± 0%; VPP =VCC) Symbol Alt Parameter Test Condition t AVQV t ACC Address Valid to Output Valid tlqv tglqv t HQZ (2) t GHQZ (2) tc to t DF t DF Chip nable Low to Output Valid Output nable Low to Output Valid Chip nable High to Output Hi-Z Output nable High to Output Hi-Z t AXQX t OH Transition to Address Output Transition M27C52-45 (3) Min Max Min Max Min Max Min Max =V IL,G=V IL ns G=VIL ns =VIL ns G=V IL ns =V IL ns =V IL,G=V IL ns Notes.. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 00% tested. 3. In case of 45ns speed see High Speed AC measurement conditions. Unit 5/5

6 Table 8B. Read Mode AC Characteristics () (T A = 0 to 70 C, 40 to 85 C or 40 to 25 C; V CC =5V±5% or 5V ± 0%; V PP =V CC ) Symbol Alt Parameter Test Condition Address Valid to t AVQV t ACC Output Valid Chip nable Low to tlqv tc Output Valid Output nable Low t GLQV t O to Output Valid thqz (2) t GHQZ (2) tdf t DF Chip nable High to Output Hi-Z Output nable High to Output Hi-Z t AXQX t OH to Address Transition Output Transition M27C /-20/-25 Min Max Min Max Min Max Min Max =V IL,G=V IL ns G=VIL ns =V IL ns G=VIL ns =V IL ns =V IL,G=V IL ns Notes.. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 00% tested. Unit Figure 5. Read Mode AC Waveforms A0-A5 VALID tavqv taxqx tglqv thqz G Q0-Q7 tlqv DATA OUT tghqz Hi-Z AI00735 Programming When delivered (and after each erasure for UV PROM), all bits of the M27C52 are in the state. Data is introduced by selectively programming 0 s into the desired bit locations. Although only 0 s will be programmed, both s and 0 s can be present in the data word. The only way to change a 0 to a is by die exposure to ultraviolet light (UV PROM). The M27C52 is in the programming mode when VPP input is at 2.75V and is pulsed to V IL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. V CC is specified to be 6.25V ± 0.25V. The M27C52 can use PRSTO IIB Programming Algorithm that drastically reduces the programming time (typically less than 6 seconds). Nevertheless to achieve compatibility with all programming equipments, PRSTO Programming Algorithm can be used as well. 6/5

7 Table 9. Programming Mode DC Characteristics () (T A =25 C; V CC = 6.25V ± 0.25V; V PP = 2.75V ± 0.25V) Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current VIL VIN VIH ±0 µa I CC Supply Current 50 ma I PP Program Current = V IL 50 ma VIL Input Low Voltage V V IH Input High Voltage 2 V CC V VOL Output Low Voltage IOL = 2.mA 0.4 V VOH Output High Voltage TTL IOH = ma 3.6 V Note: V ID A9 Voltage V. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 0. MARGIN MOD AC Characteristics () (T A =25 C; V CC = 6.25V ± 0.25V; V PP = 2.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max Unit ta9hvph tas9 VA9 High to VPP High 2 µs tvphl tvps VPP High to Chip nable Low 2 µs t A0HH t AS0 VA0 High to Chip nable High (Set) µs t A0LH t AS0 VA0 Low to Chip nable High (Reset) µs txa0x tah0 Chip nable Transition to VA0 Transition µs t XVPX t VPH Chip nable Transition to V PP Transition 2 µs t VPXA9X t AH9 V PP Transition to VA9 Transition 2 µs Note:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. Table. Programming Mode AC Characteristics () (TA =25 C; VCC = 6.25V ± 0.25V; VPP = 2.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max Unit tavl tas Address Valid to Chip nable Low 2 µs t QVL t DS Input Valid to Chip nable Low 2 µs tvchl tvcs VCC High to Chip nable Low 2 µs t VPHL t OS V PP High to Chip nable Low 2 µs t VPLVPH t PRT V PP Rise Time 50 ns tlh tpw Chip nable Program Pulse Width (Initial) µs thqx tdh Chip nable High to Input Transition 2 µs thvpx toh Chip nable High to VPP Transition 2 µs t VPLL t VR V PP Low to Chip nable Low 2 µs tlqv tdv Chip nable Low to Output Valid µs t HQZ (2) t DFP Chip nable High to Output Hi-Z 0 30 ns t HAX t AH Chip nable High to Address Transition 0 ns Notes:. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Sampled only, not 00% tested. 7/5

8 Figure 6. MARGIN MOD AC Waveforms V CC A8 A9 ta9hvph tvpxa9x GV PP tvphl txvpx ta0hh txa0x A0 Set A0 Reset ta0lh AI00736B Note: A8 High level = 5V; A9 High level = 2V. Figure 7. Programming and Verify Modes AC Waveforms A0-A5 VALID tavl thax Q0-Q7 DATA IN DATA OUT tqvl thqx thqz V CC tlqv tvchl thvpx GV PP tvphl tvpll tlh PROGRAM VRIFY AI /5

9 Figure 8. Programming Flowchart NO YS V CC = 6.25V, V PP = 2.75V n=0 = 00µs Pulse ++n NO = 25 VRIFY ++ Addr FAIL ST MARGIN MOD Last Addr YS YS NO RST MARGIN MOD CHCK ALL BYTS st: V CC =6V 2nd: V CC = 4.2V AI00738B programmed. The verify is accomplished with G at V IL. Data should be verified with t LQV after the falling edge of. On-Board Programming The M27C52 can be directly programmed in the application circuit. See the relevant Application Note AN620. lectronic Signature The lectronic Signature (S) mode allows the reading out of a binary code from an PROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its correspondingprogramming algorithm. The S mode is functional in the 25 C ± 5 C ambient temperature range that is required when programming the M27C52. To activate the S mode, the programming equipment must force.5v to 2.5V on address line A9 of the M27C52. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V IL to V IH. All other address lines must be held at VIL during lectronic Signature mode. Byte 0 (A0=V IL ) represents the manufacturer code and byte (A0=VIH) the device identifier code. For the SGS-THOMSON M27C52, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. PRSTO IIB Programming Algorithm PRSTO IIB Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. This can be achieved with SGS-THOMSON M27C52 due to several design innovations described in the M27C52 datasheet to improve programming efficiency and to provide adequate margin for reliability. Before starting the programming the internal MARGIN MOD circuit is set in order to guarantee that each cell is programmed with enough margin. Then a sequence of 00µs program pulses are applied to each byte until a correct verify occurs. No overprogram pulses are applied since the verify in MARGIN MOD provides the necessary margin. Program Inhibit Programming of multiple M27C52s in parallel with different data is also easily accomplished. xcept for, all like inputs including GVPP of the parallel M27C52 may be common. A TTL low level pulse applied to a M27C52 s input, with V PP at 2.75V, will program that M27C52. A high level input inhibits the other M27C52s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly RASUR OPRATION (applies for UV PROM) The erasurecharacteristicsof the M27C52 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27C52 in about 3 years, while it would take approximately week to cause erasure when exposed to direct sunlight. If the M27C52 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C52 window to prevent unintentional erasure. The recommended erasure procedure for the M27C52 is exposure to short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 5W-sec/cm 2. The erasure time withthis dosage is approximately 5 to 20 minutes using an ultraviolet lamp with 2000 µw/cm 2 power rating. The M27C52 should be placed within 2.5 cm ( inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/5

10 ORDRING INFORMATION SCHM xample: M27C52-70 X C TR Speed V CC Tolerance Package Temperature Range Option -45 () 45 ns ns ns ns ns X ± 5% blank ± 0% F B C N FDIP28W PDIP28 PLCC32 TSOP28 8 x 3.4mm 0 to 70 C 6 40 to 85 C 3 40 to 25 C X TR Additional Burn-in Tape & Reel Packing ns ns ns ns ns Note:. High Speed, see AC Characteristics section for further information For a list of available options(speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 0/5

11 FDIP28W - 28 pin Ceramic Frit-seal DIP, with window Symb mm inches Typ Min Max Typ Min Max A A A B B C D e e ea L S α N FDIP28W A2 A A L B B e e3 α ea C S D N FDIPW-a Drawing is not to scale /5

12 PDIP28-28 pin Plastic DIP, 600 mils width Symb mm inches Typ Min Max Typ Min Max A A A B B C D e ea L S α N PDIP28 A2 A A L B B e α ea C S D N PDIP Drawing is not to scale 2/5

13 PLCC32-32 lead Plastic Leaded Chip Carrier, rectangular Symb mm inches Typ Min Max Typ Min Max A A B B D D D e N Nd 7 7 Ne 9 9 CP PLCC32 D D A N B Ne D2/2 B e Nd A PLCC CP Drawing is not to scale 3/5

14 TSOP28-28 lead Plastic Thin Small Outline, 8 x 3.4mm Symb mm inches Typ Min Max Typ Min Max A A A B C D D e L α N CP TSOP28 A e 28 B 7 8 D D A CP DI C TSOP-c A α L Drawing is not to scale 4/5

M27C Mbit (1Mb x 8) UV EPROM and OTP EPROM

M27C Mbit (1Mb x 8) UV EPROM and OTP EPROM 8 Mbit (1Mb x 8) UV PROM and OTP PROM 5V ± 10% SUPPLY VOLTAG in RAD OPRATION ACCSS TIM: 45ns LOW POWR CONSUMPTION: Active Current 35mA at 5MHz Standby Current 100µA PROGRAMMING VOLTAG: 12.75V ± 0.25V 32