M28F Megabit (64K x 16, Chip Erase) FLASH MEMORY

Transcription

1 1 Megabit (64K x 16, Chip rase) FLASH MMORY FAST ACCSS TIM: 90ns LOW POWR CONSUMPTION Standby Current: 100µA Max 10,000 RAS/PRORAM CYCLS 12V PRORAMMIN VOLTA TYPICAL BYT PRORAMMIN TIM 10µs (PRSTO F ALORITHM) LCTRICAL CHIP RAS in 1s RAN INTRATD RAS/PRORAM-STOP TIMR OTP COMPATIBL PACKAS and PINOUTS for PLCC44 and TSOP40 XTNDD TMPRATUR RANS PLCC44 (K) Figure 1. Logic Diagram TSOP40 (N) 10 x 14mm DSCRIPTION The M28F102 FLASH MMORY is a non-volatile memory which may be erased electrically at the chip level and programmed word-by-word. It is organised as 64K words of 16 bits. It uses a command register architecture to select the operating modes and thus provides a simple microprocessor interface. The M28F102 FLASH MMORY is suitable for applications where the memory has to be reprogrammed in the equipment. The access time of 100ns makes the device suitable for use in high speed microprocessor systems. A0-A15 W 16 VCC VPP M28F DQ0-DQ15 Table 1. Signal Names A0 - A15 Address Inputs DQ0 - DQ15 Data Inputs / Outputs Chip nable Output nable VSS AI00627B W Write nable VPP Program Supply V CC Supply Voltage VSS round September /20

2 Figure 2A. LCC Pin Connections Figure 2B. TSOP Pin Connections DQ12 DQ11 DQ10 DQ9 DQ8 VSS NC DQ7 DQ6 DQ5 DQ4 DQ13 DQ14 DQ15 VPP NC V CC W NC A15 A14 12 DQ3 DQ2 DQ1 DQ NC 44 M28F102 A0 A1 A2 A3 A4 34 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5 AI00629D A9 A10 A11 A12 A13 A14 A15 NC W VCC V PP DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ M28F102 (Normal) V SS A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 V SS AI01263 Warning: NC = Not Connected Warning: NC = Not Connected Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit TA Ambient Operating Temperature grade 1 grade 3 grade 6 0to70 40 to to 85 C T ST Storage Temperature 65 to 150 C V IO Input or Output Voltages 0.6 to 7 V V CC Supply Voltage 0.6 to 7 V V A9 A9 Voltage 0.6 to 13.5 V VPP Program Supply Voltage, during rase or Programming 0.6 to 14 V Note: xcept for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. xposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SS-THOMSON SUR Program and other relevant quality documents. DVIC OPRATION The M28F102 FLASH MMORY employs a technology similar to a 1 Megabit PROM but adds to the device functionality by providing electrical erasure and programming. These functions are managed by a command register. The functionsthat are addressed via the command register depend on the voltage applied to the V PP, program voltage, input. When V PP is less than or equal to 6.5V, the command register is disabled and M28F102 functions as a read only memory providing operating modes similar to an PROM (Read, Output Disable, lectronic Signature Read and Standby). When VPP is raised to 12V the command register is enabled and this provides, in addition, rase and Program operations. 2/20

3 RAD ONLY MODS, V PP 6.5V For all Read Only Modes, except Standby Mode, the Write nable input W should be High. In the Standby Mode this input is don t care. Read Mode. The M28F102 has two enable inputs, and, both of which must be Low in order to output data from the memory. The Chip nable () is the power control and should be used for device selection. Output nable () is the output control and should be used to gate data on to the output, independant of the device selection. Standby Mode. In the Standby Mode the maximum supply current is reduced. The device is placed in the Standby Mode by applying a High to the Chip nable () input. When in the Standby Mode the outputs are in a high impedance state, independant of the Output nable () input. Output Disable Mode. When the Output nable () is High the outputs are in a high impedance state. lectronic Signature Mode. This mode allows the read out of two binary codes from the device which identify the manufacturer and device type. This mode is intended for use by programming equipment to automatically select the correct erase and programming algorithms. The lectronic Signature Mode is active when a high voltage (11.5V to 13V) is appliedto address line A9 with and Low. With A0 Low the output data is the manufacturer code, when A0 is High the output is the devicetype code. All other address lines should be maintained Low while reading the codes. The electronic signature may also be accessed in Read/Write modes. RAD/WRIT MODS, 11.4V V PP 12.6V When V PP is High both read and write operations may be performed. These are defined by the contents of an internal command register. Commands may be written to this register to set-up and execute, rase, rase Verify, Program, Program Verify and Reset modes. ach of these modes needs 2 cycles. very mode starts with a write operation to set-up the command, this is followed by either read or write operations. The device expects the first cycle to be a write operation and does not corrupt data at any location in memory. Read mode is set-up with one cycle only and may be followed by any number of read operations to output data. lectronic Signature Read mode is set-up with one cycle and followed by a read cycle to output the manufacturer or device codes. Awrite to the command registeris made by bringing W Low while is Low.The falling edge of W latches Addresses, while the rising edge latches Data, which are used for those commands that require address inputs, command input or provide data output. The supply voltage VCC and the program voltage VPP can be applied in any order. When the device is powered up or when V PP is 6.5V the contents of the command register default to 00h, thus automatically setting-up Read operations. In addition a specific command may be used to set the command register to 00h for reading the memory. The system designer may chose to provide a constant high VPP and use the register commands for all operations, or to switch the V PP from low to high only when needing to erase or program the memory. All command register access is inhibited when Table 3. Operations V PP Operation W A9 DQ0 - DQ15 Read Only V PPL Read V IL V IL V IH A9 Data Output Output Disable VIL VIH VIH X Hi-Z Standby VIH X X X Hi-Z lectronic Signature VIL VIL VIH VID Codes Read/Write (2) V PPH Read V IL V IL V IH A9 Data Output Notes: 1. X = VIL or VIH 2. Refer also to the Command Table Write VIL VIH VIL Pulse A9 Data Input Output Disable VIL VIH VIH X Hi-Z Standby VIH X X X Hi-Z 3/20

4 Table 4. lectronic Signature Identifier A0 DQ15-DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex Data Manufacturer s Code VIL h Device Code VIH h Table 5. Commands Command Cycles 1st Cycle 2nd Cycle Operation A0-A15 DQ0-DQ15 (2) Operation A0-A15 DQ0-DQ15 (2) Read 1 Write X xx00h lectronic Signature 2 Write X xx90h Read 0000h 0020h Read 0001h 0050h Setup rase/ Write X xx20h 2 rase Write X xx20h rase Verify 2 Write A0-A15 xxa0h Read X Data Output Setup Program/ Write X xx40h 2 Program Write A0-A15 Data Input Program Verify 2 Write X xxc0h Read X Data Output Reset 2 Write X 0FFFFh Write X 0FFFFh Notes: 1. X = V IL or V IH 2. x = Don t Care. RAD/WRIT MODS (cont d) VCC falls below the rase/write Lockout Voltage (V LKO ) of 2.5V. If the device is deselected during rasure, Programming or Verification it will draw active supply currents until the operations are terminated. The device is protected against stress caused by long erase or program times. If the end of rase or Programming operations are not terminated by a Verify cycle within a maximum time permitted, an internal stop timer automatically stops the operation. The device remains in an inactive state, ready to start a Verify or Reset Mode operation. Read Mode. The Read Mode is the default at power up or may be set-up by writing xx00h to the command register. Subsequent read operations output data from the memory. The memory remains in the Read Mode until a new command is written to the command register. lectronic Signature Mode. In order to select the correct erase and programming algorithms for onboard programming, the manufacturer and devices code may be read directly. It is not neccessary to apply a high voltage to A9 when using the command register. The lectronic Signature Mode is set-up by writing xx90h to the command register. The following read cycle, with address inputs 0000h or 0001h, output the manufacturer or device type codes. The command is terminated by writing another valid command to the command register (for example Reset). rase and rase Verify Modes. The memory is erased by first Programming all words to 0000h, the rase command then erases them to 0FFFFh. The rase Verify command is then used to read the memory word-by-word for a content of 0FFFFh. The rase Mode is set-up by writing xx20h to the command register. The write cycle is then repeated to start the erase operation. rasure starts on the rising edge of W during this second cycle. 4/20

5 rase is followed by an rase Verify which reads an addressed byte. rase Verify Mode is set-up by writing xxa0h to the command register and at the same time supplying the address of the word to be verified. The rising edge of W during the set-up of the first rase Verify Mode stops the rase operation. The following read cycle is made with an internally generated margin voltage applied; reading 0FFFFh indicates that all bits of the addressed byte are fully erased. The whole contents of the memory are verified by repeating the rase Verify Operation, first writing the set-up code xxa0h with the address of the word to be verified and then reading the byte contents in a second read cycle. As the rase algorithm flow chart shows, when the data read during rase Verify is not 0FFFFh, another rase operation is performed and verification continues from the address of the last verified word. The command is terminated by writing another valid command to the command register(for example Program or Reset). Program and Program Verify Modes. The Program Mode is set-up by writing xx40h to the command register. This is followed by a second write cycle which latches the address and data of the word to be programmed. The rising edge of W during this secind cycle starts the programming operation. Programming is followed by a Program Verify of the data written. Program Verify Mode is set-up by writing xxc0h to the command register. The rising edge of W during the set-up of the Program Verify Mode stops the Programming operation. The following read cycle, of the address already latched during programming, is made with an internally generated margin voltage applied, reading valid data indicates that all bits have been programmed. Reset Mode. This command is used to safelyabort rase or Program Modes. The Reset Mode is set-up and performed by writing 0FFFFh two times to the command register. The command should be followed by writing a valid command to the the command register (for example Read). AC MASURMNT CONDITIONS Figure 4. AC Testing Load Circuit Input Rise and Fall Times 10ns Input Pulse Voltages 0.45V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2V Note that Output Hi-Z is defined as the point where data is no longer driven. 1.3V 1N kΩ Figure 3. AC Testing Input Output Waveforms 2.4V 2.0V DVIC UNDR TST C L = 100pF OUT 0.45V 0.8V AI00827 C L includes JI capacitance AI00828 Table 6. Capacitance (TA =25 C, f = 1 MHz ) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance VIN = 0V 6 pf COUT Output Capacitance VOUT = 0V 12 pf Note: 1. Sampled only, not 100% tested 5/20

6 Table 7. DC Characteristics (T A = 0 to 70 C, 40 to 85 C or 40 to 125 C; V CC =5V± 5% or 5V ± 10%) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0V V IN V CC ±1 µa ILO Output Leakage Current 0V VOUT VCC ±10 µa I CC Supply Current (Read) = V IL, f = 8MHz 50 ma I CC1 Supply Current (Standby) TTL = V IH 1 ma Supply Current (Standby) CMOS = VCC ± 0.2V 100 µa Note: I CC2 I CC3 Supply Current (Programming) During Programming 10 ma Supply Current (Program Verify) During Verify 30 ma ICC4 Supply Current (rase) During rasure 15 ma I CC5 I CC6 Supply Current (rase Verify) During rase Verify 30 ma Supply Current (lectronic Signature) A9 = V ID 30 ma I LPP Program Leakage Current V PP V CC ±10 µa I PP Program Current (Read or V PP >V CC 200 µa Standby) VPP VCC ±10 µa I PP1 I PP2 I PP3 I PP4 I PP5 Program Current (Programming) V PP =V PPH, During Programming 50 ma Program Current (Program Verify) V PP =V PPH, During Verify 5 ma Program Current (rase) V PP =V PPH, During rase 50 ma Program Current (rase Verify) V PP =V PPH, During rase Verify 5 ma Program Current (lectronic Signature) A9 = V ID 500 µa V IL Input Low Voltage V V IH Input High Voltage TTL 2 VCC V Input High Voltage CMOS 0.7 VCC VCC V V OL Output Low Voltage I OL = 5.8mA (grade 1) 0.45 V IOL = 2.1mA (grade 3&6) 0.45 V VOH Output High Voltage CMOS I OH = 100µA V CC 0.4 V I OH = 2.5mA 0.85 V CC V Output High Voltage TTL IOH = 2.5mA 2.4 V VPPL Program Voltage (Read Operations) V VPPH Program Voltage (Read/Write Operations) V V ID A9 Voltage (lectronic Signature) V I ID V LKO A9 Current (lectronic Signature) A9 = V ID 200 µa Supply Voltage, rase/program 2.5 V Lock-out 1. Not 100% tested. Characterisation Data available. 6/20

7 Table 8A. Read Only Mode AC Characteristics (T A = 0 to 70 C, 40 to 85 C or 40 to 125 C; V CC =5V± 5% or 5V ± 10%; 0V V PP 6.5V) Symbol Alt Parameter Test Condition Note: t WHL - Write nable High to Output nable Low M28F Min Max Min Max Min Max Unit µs tavav trc Read Cycle Time = VIL, = VIL ns Address Valid to t AVQV t ACC =V Output Valid IL,=V IL ns tlqx tlqv tlqx tlz tc Chip nable Low to Output Transition Chip nable Low to Output Valid Output nable Low to tolz Output Transition Output nable Low to t LQV t O Output Valid thqz t HQZ taxqx t DF toh Chip nable High to Output Hi-Z Output nable High to Output Hi-Z Address Transition to Output Transition 1. Sampled only, not 100% tested =VIL ns =VIL ns =VIL ns =V IL ns =VIL ns =V IL ns =VIL, =VIL ns Table 8B. Read Only Mode AC Characteristics ((T A = 0 to 70 C, 40 to 85 C or 40 to 125 C; V CC =5V± 5% or 5V ± 10%; 0V V PP 6.5V) Symbol Alt Parameter Test Condition M28F Min Max Min Max Unit twhl - Write nable High to Output nable Low 6 6 µs t AVAV t RC Read Cycle Time = V IL,=V IL ns t AVQV t ACC Address Valid to Output Valid = V IL,=V IL ns Chip nable Low to Output t LZ =V Transition IL 0 0 ns t LQV t C Chip nable Low to Output Valid = V IL ns t LQX t LQX t OLZ Output nable Low to Output Transition =V IL 0 0 ns tlqv to Output nable Low to Output Valid = VIL ns thqz Chip nable High to Output Hi-Z = VIL ns thqz tdf Output nable High to Output Hi-Z = VIL ns Note: taxqx toh 1. Sampled only, not 100% tested Address Transition to Output Transition =VIL, =VIL 0 0 ns 7/20

8 Figure 5. Read Mode AC Waveforms tavav A0-A15 tavqv taxqx tlqv thqz tlqx tlqv thqz tlqx DQ0-DQ15 DATA OUT AI00630 Figure 6. Read Command Waveforms V PP tvphl A0-A15 VALID tavqv taxqx tlwl twhh tlqv thqz thwl twhl thqz W twlwh tlqv tdvwh twhdx DQ0-DQ15 COMMAND DATA OUT RAD ST-UP RAD AI /20

9 Figure 7. lectronic Signature Command Waveforms V PP tvphl A0-A h-0001h tavqv taxqx tlwl twhh tlqv thqz thwl twhl thqz W twlwh tlqv tdvwh twhdx DQ0-DQ15 COMMAND DATA OUT RAD LCTRONIC SINATUR ST-UP RAD MANUFACTURR OR DVIC AI /20

10 Table 9A. Read/Write Mode AC Characteristics, W and Controlled (TA = 0 to 70 C, 40 to 85 C or 40 to 125 C; VCC =5V± 10% or 5V ± 5%) M28F102 Symbol Alt Parameter Unit Min Max Min Max Min Max tvphl VPP High to Chip nable Low µs t VPHWL V PP High to Write nable Low µs twhwh3 twc Write Cycle Time (W controlled) ns t HH3 t WC Write Cycle Time ( controlled) ns tavwl tas Address Valid to Write nable Low ns t AVL Address Valid to Chip nable Low ns twlax tah Write nable Low to Address Transition ns t LAX Chip nable Low to Address Transition ns tlwl tcs Chip nable Low to Write nable Low ns t WLL Write nable Low to Chip nable Low ns thwl Output nable High to Write nable Low µs t HL Output nable High to Chip nable Low µs tdvwh tds Input Valid to Write nable High ns t DVH Input Valid to Chip nable High ns Write nable Low to Write nable High t WLWH t WP (Write Pulse) ns t LH Chip nable Low to Chip nable High (Write Pulse) ns t WHDX t DH Write nable High to Input Transition ns t HDX Chip nable High to Input Transition ns twhwh1 Duration of Program Operation (W contr.) µs thh1 Duration of Program Operation ( contr.) µs t WHWH2 Duration of rase Operation (W contr.) ms thh2 Duration of rase Operation ( contr.) ms t WHH t CH Write nable High to Chip nable High ns thwh Chip nable High to Write nable High ns t WHWL t WPH Write nable High to Write nable Low ns thl Chip nable High to Chip nable Low ns t WHL Write nable High to Output nable Low µs thl Chip nable High to Output nable Low µs t AVQV t ACC Addess Valid to data Output ns tlqx tlz Chip nable Low to Output Transition ns t LQV t C Chip nable Low to Output Valid ns tlqx tolz Output nable Low to Output Transition ns t LQV t O Output nable Low to Output Valid ns thqz Chip nable High to Output Hi-Z ns t HQZ t DF Output nable High to Output Hi-Z ns taxqx toh Address Transition to Output Transition ns Note: 1. Sampled only, not 100% tested 10/20

11 Table 9B. Read/Write Mode AC Characteristics, W and Controlled (TA = 0 to 70 C, 40 to 85 C or 40 to 125 C; VCC =5V± 10% or 5V ± 5%) M28F102 Symbol Alt Parameter Unit Min Max Min Max tvphl VPP High to Chip nable Low 1 1 µs t VPHWL V PP High to Write nable Low 1 1 µs t WHWH3 t WC Write Cycle Time (W controlled) ns thh3 twc Write Cycle Time ( controlled) t AVWL t AS Address Valid to Write nable Low 0 0 ns t AVL Address Valid to Chip nable Low 0 0 ns twlax tah Write nable Low to Address Transition ns t LAX Chip nable Low to Address Transition ns tlwl tcs Chip nable Low to Write nable Low ns twll Write nable Low to Chip nable Low 0 0 ns thwl Output nable High to Write nable Low 0 0 µs thl Output nable High to Chip nable Low 0 0 µs t DVWH t DS Input Valid to Write nable High ns t DVH Input Valid to Chip nable High ns twlwh twp Write nable Low to Write nable High (Write Pulse) ns t LH Chip nable Low to Chip nable High (Write Pulse) ns t WHDX t DH Write nable High to Input Transition ns thdx Chip nable High to Input Transition ns t WHWH1 Duration of Program Operation (W controlled) µs t HH1 Duration of Program Operation ( controlled) µs twhwh2 Duration of rase Operation (W controlled) ms t HH2 Duration of rase Operation ( controlled) ms twhh tch Write nable High to Chip nable High 0 0 ns thwh Chip nable High to Write nable High 0 0 ns t WHWL t WPH Write nable High to Write nable Low ns thl Chip nable High to Chip nable Low ns t WHL Write nable High to Output nable Low 6 6 µs t HL Chip nable High to Output nable Low 6 6 µs tavqv tacc Addess Valid to data Output ns t LQX t LZ Chip nable Low to Output Transition 0 0 ns t LQV t C Chip nable Low to Output Valid ns tlqx tolz Output nable Low to Output Transition 0 0 ns t LQV t O Output nable Low to Output Valid ns Chip nable High to Output Hi-Z ns thqz tdf Output nable High to Output Hi-Z ns taxqx toh Address Transition to Output Transition 0 0 ns Note: 1. Sampled only, not 100% tested t HQZ 11/20

12 Figure 8. rase Set-up and rase Verify Commands Waveforms, W Controlled V PP tvphl A0-A15 twhwh3 tlwl twhh thwl twhwl W twlwh tdvwh twhdx DQ0-DQ15 COMMAND COMMAND RAS ST-UP RAS ST-UP (RPAT OF 1st CYCL) RAS OPRATION VALID tavwl twlax tlwl twhh tlqv thqz twhwh2 twhl thqz twlwh tlqv tdvwh twhdx COMMAND DATA OUT RAS VRIFY ST-UP VRIFY RAD AI /20

13 Figure 9. rase Set-up and rase Verify Commands Waveforms, Controlled V PP tvphwl A0-A15 thh3 W twll thwh thl thl tlh tdvh thdx DQ0-DQ15 COMMAND COMMAND RAS ST-UP RAS ST-UP (RPAT OF 1st CYCL) RAS OPRATION VALID tavl tlax twll thwh tlqv thh2 thl tlh tlqv tdvh thdx COMMAND RAS VRIFY ST-UP DATA OUT VRIFY RAD thqz thqz AI01312B 13/20

14 Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled V PP tvphl A0-A15 tlwl twhh thwl W twlwh tdvwh DQ0-DQ15 COMMAND PRORAM ST-UP PRORAM OPRATION VALID tavwl twhwh3 twlax twhh twhh tlqv thqz tlwl tlwl twhwl twhwh1 thqz twhl twlwh twlwh tlqv twhdx twhdx tdvwh twhdx tdvwh DATA IN COMMAND DATA OUT ADDRSS AND DATA LATCH PRORAM VRIFY ST-UP VRIFY RAD AI /20

15 Figure 11. Program Set-up and Program Verify Commands Waveforms, Controlled V PP tvphl A0-A15 W twll thwh thl tlh tdvh DQ0-DQ15 COMMAND PRORAM ST-UP PRORAM OPRATION VALID tavl thh3 tlax thwh thwh twll twll thl thh1 tlh tlh thdx thdx tdvh tdvh DATA IN COMMAND ADDRSS AND DATA LATCH PRORAM VRIFY ST-UP tlqv thl thqz tlqv thqz thdx DATA OUT VRIFY RAD AI00635B 15/20

16 Figure 12. rasing Flowchart Figure 13. Programming Flowchart V PP = 12V V PP = 12V PRORAM ALL BYTS TO 0000h n=0 n=0, Addr=0000h RAS ST-UP PRORAM ST-UP Latch Addr, Data Wait 10ms Wait 10µs YS V PP < 6.5V FAIL NO ++n LIMIT RAS VRIFY Latch Addr. Wait 6µs RAD DATA OUTPUT NO Data OK Addr++ YS V PP < 6.5V FAIL NO ++n =25 PRORAM VRIFY RAD DATA OUTPUT NO Wait 6µs Data OK YS Addr++ YS Last Addr NO Last Addr YS NO YS RAD COMMAND RAD COMMAND V PP < 6.5V, PASS AI00636 V PP < 6.5V, PASS AI00677 Limit: 1000 at grade 1; 6000 at grades 3 & 6. PRSTO F RAS ALORITHM The PRSTO F rase Algorithm guarantees that the device will be erased in a reliable way. The algorithm first programs all words to 0000h in order to ensure uniform erasure. The programming follows the Presto F Programming Algorithm (see below). rase is set-up by writing xx20h to the command register, the erasure is started by repeating this write cycle. rase Verify is set-up by writing xxa0h to the command register together with the address of the word to be verified. The subsequent read cycle reads the data which is compared to 0FFFFh. rase Verify beginsat address 0000h and continues to the last address or until the comparison of the data to 0FFFFh fails. If this occurs, the address of the last word checked is stored and a new rase operation performed. rase Verify then continues from the address of the stored location. PRSTO F PRORAM ALORITHM The PRSTO F Programming Algorithm applies a series of 10µs programming pulses to a word until a correct verify occurs. Up to 25 programming operations are allowed for one word. Program is set-up by writing xx40h to the command register, the programming is started after the next write cycle which also latches the address and data to be programmed.program Verify is set-up by writing xxc0h to the command register, followed by a read cycle and a compare of the data read to the data expected. During Program and Program Verify operations a MARIN MOD circuit is activated to guarantee that the cell is programmed with a safety margin. 16/20

17 ORDRIN INFORMATION SCHM xample: M28F X K 1 TR Speed V CC Tolerance Package Temp. Range Option ns ns ns blank ± 10% X ± 5% K N PLCC44 TSOP40 10 x 14mm 1 0 to 70 C 3 40 to 125 C 6 40 to 85 C TR Tape & Reel Packing ns ns For a list of available options(speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SS-THOMSON Sales Office nearest to you. 17/20

18 PLCC44-44 lead Plastic Leaded Chip Carrier, square Symb mm inches Typ Min Max Typ Min Max A A B B D D D e N CP PLCC44 D D1 A1 1 N B1 Ne 1 D2/2 B e Nd A PLCC CP Drawing is not to scale 18/20

19 TSOP40-40 lead Plastic Thin Small Outline, 10 x 14mm Symb mm inches Typ Min Max Typ Min Max A A A B C D D e L α N CP TSOP40 A2 1 N e B N/2 D1 D A CP DI C TSOP-a A1 α L Drawing is not to scale 19/20

20 Information furnished is believed to be accurate and reliable. However, SS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SS-THOMSON Microelectronics SS-THOMSON Microelectronics - All Rights Reserved SS-THOMSON Microelectronics ROUP OF COMPANIS Australia - China - Brazil - France - ermany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 20/20