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2 NMOS 64 Kbit (8Kb x 8) UV EPROM NOT FOR NEW DESIGN FAST ACCESS TIME: 180ns EXTENDED TEMPERATURE RANGE SINGLE 5V SUPPLY VOLTAGE LOW STANDBY CURRENT: 35mA max TTL COMPATIBLE DURING READ and PROGRAM FAST PROGRAMMING ALGORITHM ELECTRONIC SIGNATURE PROGRAMMING VOLTAGE: 12V DESCRIPTION The M2764A is a 65,536 bit UV erasable and electrically programmable memory EPROM. It is organized as 8,192 words by 8 bits. The M27C64A is housed in a 28 pin Window Ceramic Frit-Seal Dual-in-Line package. The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure FDIP28W (F) Figure 1. Logic Diagram V CC V PP A0-A Q0-Q7 P M2764A E G V SS AI00776B November 2000 This is information on a product still in production but not recommended for new designs. 1/10

3 Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit T A Ambient Operating Temperature grade 1 grade 6 T BIAS Temperature Under Bias grade 1 grade 6 0 to to to to 95 T STG Storage Temperature 65 to 125 C V IO Input or Output Voltages 0.6 to 6.5 V V CC Supply Voltage 0.6 to 6.5 V V A9 A9 Voltage 0.6 to 13.5 V V PP Program Supply 0.6 to 14 V Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. C C Figure 2. DIP Pin Connections V PP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 V SS M2764A Warning: NC = Not Connected AI00777 V CC P NC A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 DEVICE OPERATION The seven modes of operations of the M2764A are listed in the Operating Modes table. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M2764A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, address access time (tavqv) is equal to the delay from E to output (t ELQV). Data is available at the outputs after the falling edge of G, assuming that E has been low and the addresses have been stable for at least t AVQV-t GLQV. Standby Mode The M2764A has a standby mode which reduces the maximum active power current from 75mA to 35mA. The M2764A is placed in the standby mode by applying a TTL high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows : a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. 2/10

4 DEVICE OPERATION (cont d) For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. System Considerations The power switching characteristics of fast EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 1µF ceramic capacitor be used on every device between V CC and V SS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V CC and V SS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPROM), all bits of the M2764A are in the 1" state. Data is introduced by selectively programming 0s" into the desired bit locations. Although only 0s will be programmed, both 1s and 0s can be present in the data word. The only way to change a 0" to a 1" is by ultraviolet light erasure. The M2764A is in the programming mode when VPP input is at 12.5V and E and P are at TTL low. The data to be programmed is applied, 8 bits in parallel, to the data output pins. The levels required for the address and data inputs are TTL. Fast Programming Algorithm Fast Programming Algorithm rapidly programs M2764A EPROMs using an efficient and reliable method suited to the production programming environment. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has Table 3. Operating Modes Mode E G P A9 V PP Q0 - Q7 Read V IL V IL V IH X V CC Data Out Output Disable VIL VIH VIH X VCC Hi-Z Program VIL VIH VIL Pulse X VPP Data In Verify V IL V IL V IH X V PP Data Out Program Inhibit VIH X X X VPP Hi-Z Standby VIH X X X VCC Hi-Z Electronic Signature V IL V IL V IH V ID V CC Codes Out Note: X = V IH or V IL, V ID = 12V ± 0.5%. Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer s Code VIL h Device Code V IH h 3/10

5 AC MEASUREMENT CONDITIONS Figure 4. AC Testing Load Circuit Input Rise and Fall Times 20ns Input Pulse Voltages 0.45V to 2.4V Input and Output Timing Ref. Voltages 0.8V to 2.0V Note that Output Hi-Z is defined as the point where data is no longer driven. 1.3V 1N914 Figure 3. AC Testing Input Output Waveforms 3.3kΩ 2.4V 2.0V DEVICE UNDER TEST C L = 100pF OUT 0.45V 0.8V AI00827 C L includes JIG capacitance AI00828 Table 5. Capacitance (1) (T A = 25 C, f = 1 MHz ) Symbol Parameter Test Condition Min Max Unit C IN Input Capacitance V IN = 0V 6 pf Note: C OUT Output Capacitance V OUT = 0V 12 pf 1. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A12 VALID tavqv taxqx E tglqv tehqz G telqv tghqz Q0-Q7 DATA OUT Hi-Z AI /10

6 Table 6. Read Mode DC Characteristics (1) (T A = 0 to 70 C or 40 to 85 C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC) Symbol Parameter Test Condition Min Max Unit I LI Input Leakage Current 0 V IN V CC ±10 µa I LO Output Leakage Current V OUT = V CC ±10 µa I CC Supply Current E = V IL, G = V IL 75 ma I CC1 Supply Current (Standby) E = V IH 35 ma I PP Program Current V PP = V CC 5 ma V IL Input Low Voltage V V IH Input High Voltage 2 V CC + 1 V V OL Output Low Voltage I OL = 2.1mA 0.45 V V OH Output High Voltage I OH = 400µA 2.4 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 7A. Read Mode AC Characteristics (1) (T A = 0 to 70 C or 40 to 85 C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC) Symbol Alt Parameter Address Valid to t AVQV t ACC Output Valid Chip Enable Low t ELQV t CE to Output Valid Output Enable t GLQV t OE Low to Output Valid (2) Chip Enable High t EHQZ t DF to Output Hi-Z t (2) Output Enable GHQZ t DF High to Output Hi-Z Address Transition t AXQX t OH to Output Transition Test Condition E = V IL, G = VIL M2764A -1-2, -20 blank, -25 Min Max Min Max Min Max Unit ns G = V IL ns E = V IL ns G = V IL ns E = V IL ns E = V IL, G = V IL ns Table 7B. Read Mode AC Characteristics (1) (T A = 0 to 70 C or 40 to 85 C; V CC = 5V ± 5% or 5V ± 10%; V PP = V CC) Symbol Alt Parameter Address Valid to t AVQV t ACC Output Valid Chip Enable Low telqv tce to Output Valid Output Enable t GLQV t OE Low to Output Valid tehqz (2) Chip Enable High tdf to Output Hi-Z t (2) Output Enable GHQZ t DF High to Output Hi-Z Address Transition t AXQX t OH to Output Transition Test Condition E = V IL, G = VIL M2764A -3-4 Min Max Min Max Unit ns G = VIL ns E = V IL, ns G = VIL ns E = V IL ns E = V IL, G = VIL 0 0 ns Notes: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 5/10

7 Table 8. Programming Mode DC Characteristics (1) (T A = 25 C; V CC = 6V ± 0.25V; V PP = 12.5V ± 0.3V) Symbol Parameter Test Condition Min Max Units I LI Input Leakage Current V IL V IN V IH ±10 µa ICC Supply Current 75 ma IPP Program Current E = VIL 50 ma VIL Input Low Voltage V VIH Input High Voltage 2 VCC + 1 V V OL Output Low Voltage I OL = 2.1mA 0.45 V V OH Output High Voltage I OH = 400µA 2.4 V VA9 A9 Voltage V Note: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP. Table 9. Programming Mode AC Characteristics (1) (T A = 25 C; V CC = 6V ± 0.25V; V PP = 12.5V ± 0.3V) Symbol Alt Parameter Test Condition Min Max Units t AVPL t AS Address Valid to Program Low 2 µs t QVPL t DS Input Valid to Program Low 2 µs t VPHPL t VPS V PP High to Program Low 2 µs t VCHPL t VCS V CC High to Program Low 2 µs telpl tces Chip Enable Low to Program Low 2 µs t PLPH t PW Program Pulse Width (Initial) Note ms tplph topw Program Pulse Width (Overprogram) Note ms t PHQX t DH Program High to Input Transition t QXGL t OES Input Transition to Output Enable Low 2 µs 2 µs tglqv toe Output Enable Low to Output Valid 150 ns t GHQZ (4) t DFP Output Enable High to Output Hi-Z t GHAX t AH Output Enable High to Address Transition ns 0 n s Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. The Initial Program Pulse width tolerance is 1 ms ± 5%. 3. The length of the Over-program Pulse varies from 2.85 ms to ms, depending of the multiplication value of the iteration counter. 4. Sampled only, not 100% tested. 6/10

8 Figure 6. Programming and Verify Modes AC Waveforms A0-A12 VALID tavpl Q0-Q7 DATA IN DATA OUT tqvpl tphqx V PP tvphpl tglqv tghqz V CC tvchpl tghax E P telpl tplph tqxgl G PROGRAM VERIFY AI00779 Figure 7. Fast Programming Flowchart NO YES ++n > 25 FAIL V CC = 6V, V PP = 12.5V NO n = 1 P = 1ms Pulse VERIFY Last Addr YES P = 3ms Pulse by n YES NO CHECK ALL BYTES V CC = 5V, V PP 5V ++ Addr AI00775B DEVICE OPERATION (cont d) been successfully programmed. A flowchart of the M2764A Fast Programming Algorithm is shown on the last page. The Fast Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial P pulse(s) is 1ms, which will then be followed by a longer overprogram pulse of length 3ms by n (n is equal to the number of the initial one millisecond pulses applied to a particular M2764A location), before a correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied. The entire sequence of program pulses and byte verifications is performed at V CC = 6V and V PP = 12.5V. When the Fast Programming cycle has been completed, all bytes should be compared to the original data with V CC = 5V and V PP = 5V. Program Inhibit Programming of multiple M2764A in parallel with different data is also easily accomplished. Except for E, all like inputs (including G) of the parallel M2764A may be common. A TTL low pulse applied to a M2764A s E input, with V PP at 12.5V, will program that M2764A. A high level E input inhibits the other M2764As from being programmed. 7/10

9 Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G = V IL, E = V IL, P = V IH and V PP = 12.5V. Electronic Signature The Electronic Signature mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 C ± 5 C ambient temperature range that is required when programming the M2764A. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M2764A. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0 = V IL) represents the manufacturer code and byte 1 (A0 = V IH) the device identifier code. For the SGS-THOMSON M2764A, these two identifier bytes are given below. ERASURE OPERATION (applies to UV EPPROM) The erasure characteristic of the M2764A is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M2764A in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M2764A is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M2764A window to prevent unintentional erasure. The recommended erasure procedure for the M2764A is exposure to short wave ultraviolet light which has wavelength 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with µw/cm 2 power rating. The M2764A should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. ORDERING INFORMATION SCHEME Example: M2764A -1 F 1 Speed and V CC Tolerance ns, 5V ±5% ns, 5V ±5% blank 250 ns, 5V ±5% ns, 5V ±5% ns, 5V ±5% ns, 5V ±10% ns, 5V ±10% Package FDIP28W Temperature Range 1 0 to to 85 C F For a list of available options (Speed, V CC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact SGS-THOMSON Sales Office nearest to you. 8/10

10 FDIP28W - 28 pin Ceramic Frit-seal DIP, with window Symb mm inches Typ Min Max Typ Min Max A A A B B C D E E e e ea L S α N A2 A A1 L B1 B e1 e3 α ea C S D N E1 E 1 FDIPW-a Drawing is not to scale 9/10

11 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 10/10

M27128A. NMOS 128 Kbit (16Kb x 8) UV EPROM

M27128A. NMOS 128 Kbit (16Kb x 8) UV EPROM NMOS 128 Kbit (16Kb x 8) UV EPROM NOT FOR NEW DESIGN FAST ACCESS TIME: 200ns EXTENDED TEMPERATURE RANGE SINGLE 5 V SUPPLY VOLTAGE LOW STANDBY CURRENT: 40mA max TTL COMPATIBLE DURING READ and PROGRAM FAST