DIGITAL CONTROL OF A POWER INVERTER

Transcription

1 Proceedings of the IASTED International Conference Control and Applications (CA 2009) July 13-15, 2009 Cambridge, UK DIGITAL CONTROL OF A POWER INVERTER 1 Fabio Celani Dipartimento di Informatica e Sistemistica Antonio Ruberti Sapienza Università di Roma Roma, Italy celani@dis.uniroma1.it Michele Macellari, Alfiero Schiaratura and Luigi Schirone Dipartimento di Ingegneria Aerospaziale e Astronautica Sapienza Università di Roma Roma, Italy michele.macellari@uniroma1.it; aschiara@tiscalinet.it; luigi.schirone@uniroma1.it ABSTRACT This work reports on the design of a digital feedback control system for a power inverter. The proposed controller achieves asymptotic output tracking of reference sinusoidal voltages with known frequency and achieves asymptotic rejection of sudden load variations; moreover, the obtained control system is robust with respect to uncertainties in the DC input voltage. Thus, on one hand the compensator here presented represents an improvement with respect to existing sliding-mode designs since it does not show the undesirable chattering phenomenon; on the other hand, the obtained controller is less sensitive to variations of load and DC input voltage compared to previous digital dead-beat controllers for power inverters. The design was tested by means of a 400 Hz demonstrator, revealing quite interesting performance both in steady-state and transient operation. KEY WORDS power systems applications; digital control; linear control. 1 Introduction Static power inverters are required to deliver high-quality AC power from a DC source. Typical applications include Uninterruptible Power Supplies (UPS), photovoltaic systems as well as on-board power systems for terrestrial, maritime, and aerospace vehicles. They are designed to comply with rigorous specifications about low total harmonic distortion and low electromagnetic interference over a wide range of input voltages even in the presence of severe load variations. High efficiency, high reliability, and high power density are expected, too. In aerospace applications the quality assurance specifications also impact on the design approach, imposing to use simple architectures suitable to be carried out by means of consolidate techniques and qualified components. Several architectures have been proposed for inverters (see [1] and references therein). The development of inverter design reflects the technology developments and the evolution of trade-offs between performance, complexity, and system reliability. At present, the most common types of inverters [2, 3] convert an input DC voltage into a low-frequency sinewave by programming the duty-cycle of high-frequency voltage pulses and filtering the resulting output by means of a low-pass filter. Several pulse pattern generation techniques have been developed for different inverter topologies [4, 5]; however, the most widely used is sinusoidal pulse width modulation (PWM). Whichever duty-cycle generation technique is used, a relevant issue is given by controlling the output voltage level both under stationary load conditions and in the presence of transitions of the load and/or of the input DC voltage. Though analog control of inverters has been used for a long time, using digital controllers is nowadays widely accepted [6, 7, 8]. Several implementations based on different digital programmable platforms can be found in the literature; those implementations corresponds to different tradeoffs between switching frequency and processing time of the controller [9, 10, 11]. Sliding-mode control of power inverters can be used to provide high insensitivity to parametric uncertainty and to external disturbances, namely variations of the DC input voltage and/or of the load [12, 13, 14, 15]. However, because of the sliding mode control principles, the resulting designs operate at a variable switching frequency which leads to an undesirable chattering phenomenon that hinders the design of the inverter filter elements. In digital control systems of inverters, very good performance, especially for the dynamic response, has been obtained by using dead-beat controllers [7, 16] where feedback is applied so that all poles of the closed loop transfer function are at the origin of the z-plane. Unfortunately, the main limitation of these controllers is that they exhibit great sensitivity to parametric variations of the controlled system. In this work we present a digital controller that achieves asymptotic tracking of sinusoidal reference volt

2 ages with fixed frequency and asymptotic rejection of sudden load variations. In additon, the obtained closed-loop system is robust with respect to uncertanties in the DC input voltage. Thus, the compensator here presented represents an improvement with respect to existing sliding-mode designs since it does not show the undesirable chattering phenomen; in addition, the obtained controller performs better than previous digital dead-beat controller in terms of sensitivity to load and DC input voltage variations. The design was tested by means of a 400 Hz demonstrator which includes a DSP in the control loop in order to afford the computational complexity involved in the control algorithm while providing flexibility in the design and easy optimisation. Tests were carried out in both steady-state and transient conditions. The rest of the paper is organized as follows. In the next section a linear model of a PWM power inverter is described; in Section 3 the design of the digital controller is illustrated; experimental tests are reported in Section 4. 2 Modeling Consider the circuit in Fig. 1 where the switch S represents an H-bridge connecting the inductor L either to the DC input voltage V cc or to ground. Resistor R rep- as V in = d V cc. In the Laplace domain, the relation between duty-cycle d and output voltage V o is described by means of the transfer function V cc G(s) where G(s) is equal to G(s) = V o(s) V in (s) = 1 LCs 2 L R s 1. In this work a digital control system of the type described in Fig. 2 is designed. V r (t) r (k) e (k) w(t) R d (k) d(t) V o (t) (z) ZOH V cc G(s) o (k) Figure 2. Digital control system. The duty-cycle d applied to the controlled system is generated from the sampled voltage error e (k) by means of a digital compensator R (z) that drives the zero-order hold ZOH. Disturbances are modelled by means of a step function w(t) corresponding to sudden load variations. In the case of an inverter, the reference voltage assumes the following form 3 Control design V r (t) = V dc V ac cos(2πf 0 t). (1) Figure 1. Schematic diagram of the inverter. resents the load. The power stage is a second-order circuit where the LC filter extracts the fundamental frequency from the pulsed voltage generated by the continuous commutation ON-OFF of the switch S. The switch duty cycle is d = T ON /T OF F where, in the case of PWM modulation, T ON T OF F = T S with T S constant. V r (t) denotes the external sinusoidal reference voltage and the block Controller that drives the duty cycle d must be designed so that V o (t) V r (t). The behavior of the circuit over time scales much longer than the switching period T S can be investigated by means of the average switch modeling technique described in [17]. Such technique allows to obtain a continuous model of the circuit where the electrical variables are described as a function of the duty-cycle d considered as a continuous variable; specifically, under continuous conduction mode operation, the input voltage can be expressed The objective is designing the compensator transfer function R (z) so as to achieve that V o (t) asymptotically tracks V r (t) and asymptotically rejects w(t) in spite of large uncertainties on V cc. The control system in Fig. 2, considered only at the sampling times kt S, is equivalent to the discrete-time control system in Fig. 3 where G (z) denotes the zero-order hold equivalent of G(s) (see [18]). r (k) e (k) R (z) d (k) V cc G (z) w (k) o (k) Figure 3. Equivalent discrete-time control system. Note that r (k) = V r (kt S ) = V dc V ac cos(θk) with θ = 2πf 0 T S ; moreover, w (k) = w(kt ) is a discrete-time step function. 196

3 Let ˆR (z) = z 2 (z 1)(z e jθ )(z e jθ ). Then, the goal is reached by setting R (z) = ˆR (z) R (z) where R (z) is a transfer function that makes the loop in Fig. 4 robustly asymptotically stable i.e. asymptotically stable for all V cc in the considered voltage range. R (z) V cc G (z) ˆR (z) Figure 4. Discete-time loop. The poles of ˆR (z) in 1, e jθ, and e jθ make Vo asymptotically convergence to the reference signal Vr ; in addition, the pole in 1 guarantees that step disturbance w is asymptotically rejected. The factor z 2 in the numerator of ˆR (z) is introduced to reduce the latency time of the control system in Fig. 3; furthermore, since ˆR (z) is strictly proper, designing a proper R (z) implies that also the resulting R (z) will be strictly proper, and consequently computational delays of the controller need not to be taken into account in the design process. Corresponding to f 0 = 400 Hz, T S = 20 µs, L = 20 µh, C = 50 µf, and R = 4 Ω, the zero-order hold equivalent of G(s) is given by G (z) = (z ) z z Moreover, here we consider that the DC input voltage V cc has a nominal value equal to Vcc 0 = 50 V but can vary in the ±30% range i.e. 35 V cc 65. Note that the transfer function V cc G (z) ˆR (z) in Fig. 4 is critically stable and posseses a positive high-frequency gain; consequently, robust asymptotic stability can be obtained by designing an asymptotically stable R (z) that has a sufficiently low positive high-frequency gain and that makes the following property satisfied; the branches of the positive root locus of G (z) ˆR (z) R (z) that start from the poles on the unit circle point toward the interior of the circle. To obtain an R (z) that satifies the latter requirements, it is convenient to transform the stabilization problem formulated in the z-domain into an equivalent problem in the s-domain. Thus, let G (z) = G (z) ˆR (z) and use the inverse of the bilinear transformation z = 1 s 1 s so to obtain ( ) G(s) = G 1 s = 1 s (s 59.21)(s 1) 2 (s 1) 2 s(s )(s s 0.107). Now consider the positive root locus of G(s); it is easy to check that the branch that start from the pole at s = 0 lies on the negative real axis, but the branches that leave from the poles at s = ±j ω with ω = point toward the right-half of the complex plane. Then, seek for an asymptotically stable compensator R 0 (s) that makes the following condition fullfilled; the branches of the positive root locus of G(s) R 0 (s) that start from the poles with zero real part point toward the open left-half plane. Setting G(s) = N G(s) D G(s) and using the results in Appendix A it follows that the latter property is satisfied if ( ) arg N G(j ω) D G(j ω) R 0 (j ω) < π 2. (2) where D G(s) denotes the derivative of D G(s). It can be shown that 1 R 0 (s) = (1 τs) 2 with τ makes condition (2) fulfilled. Fix τ = 50 and set k R(s) = (1 50s) 2. Then, picking k positive and sufficiently small, the loop in Fig. 5 will be asymptotically stable for all 35 V cc 65. R(s) V cc G(s) Figure 5. Continuous-time loop It can be verified that an appropriate value of k is given by k = Then, using the bilinear tranformation, obtain ( ) R (z) = R z 1 = (z 1) 2 z 1 (z ) 2. Thus, the sought digital regulator in Fig. 2 is given by R (z) = ˆR (z) R (z) = z z z 2 z z z z z

4 4 Experimental results The design was tested by means of a 400 Hz demonstrator, where a DSP was included in the control loop in order to afford the computational complexity involved in the control algorithm while providing flexibility in the design and easy optimisation. In steady-state the sinewave is reproduced with a good accuracy, as it is shown by the waveform and the spectrum reported in Figs. 6 and 7 respectively. The plots in the figures are obtained with nominal load R = 4 Ω, nominal DC input voltage V cc = Vcc 0 = 50 V, and the values V dc = 25 V and V ac = 22 V for the parameters of V r (t) (see (1)). Figure 8. Nonlinear load (R = 390 Ω, R L = 4 Ω, C = 30 µf ). Figure 9. Output voltage V o and output current I o of the inverter with the nonlinear load. Figure 6. Output voltage V o in steady-state. almost negligible traces of diode switching though current spikes can be approximately two orders of magnitude larger than the current in the linear load. The behavior of the control system was also tested in presence of variations of the DC input voltage. The waveforms reported in Figs. 11 and 12 were obtained for abrupt voltage steps corresponding to variation of approximately 20% and -20% with respect to the nominal DC input voltage Vcc 0 = 50 V. In both those situations the system reacts within tens of milliseconds. Figure 7. Fast Fourier Transform of V o in steady-state. The system provides good performance even in presence of highly nonlinear loads; in fact, additional tests were carried out when the inverter was loaded by the rectifier circuit reported in Fig. 8. The parameters R = 390 Ω and R L = 4 Ω were chosen so that the peak current absorbed by the diode can be several orders of magnitude larger than the maximum current in resistor R. In Fig. 9 the inset time of the non linear load is shown whereas Fig. 10 displays the spectrum of V o in steady state after the insertion of the nonlinear load. The plots in the latter figures clearly show that the system is able to react to transients recovering the desired sinusoidal trend within few hundreds of microseconds; the waveform, initially perfectly sinusoidal, after insertion of the nonlinear load shows 5 Conclusion This work reports on the design of a digital control system for a power inverter which is capable to operate in the presence of strong and fast variations of the load and of the DC input voltage as it is commonly found in UPS and in on-board systems. The proposed control system was tested by means of a demonstrator capable to produce a sinusoid at 400 Hz which is typical of certain applications in the aerospace field. The tests reveal a good quality of the output waveform and reveal the ability to react to strong variations/nonlinearities of the load with response times of a few hundreds of microseconds. The system has also proven to be robust with respect to large variations in the DC input voltage; however, in this situation response times were of the order of tens of milliseconds. A limitation of the obtained controller is given by the computational complexity of the control algorithm which leads to using at least a DSP in its implementation. 198

5 Figure 10. Fast Fourier Transform of V o in steady-state with the nonlinear load. Figure 12. Output voltage V o correspondig to approximately a -20 % step variation of V cc. k L(s) Figure 13. Feedback system. Figure 11. Output voltage V o correspondig to approximately a 20 % step variation of V cc. Acknowledgement latter branch points toward the right-half of the complex plane if ( ) arg N L(j ω) D L(j ω) < π 2. Consider now the control system in Fig. 14 with G strictly This work was partially supported by MIUR under the program Incentivazione alla mobilità di studiosi stranieri e italiani residenti all estero. k R(s) G(s) A Root locus around a pole on the imaginary axis Figure 14. Feedback control system. Consider the feedback system in Fig. 13 with L strictly proper rational function and set L(s) = N L(s)/D L(s). Assume that L possesses a simple pole on the imaginary axis at j ω. Note that the characteristic equation D L(s) kn L(s) = 0 implicitly defines, for small k, a function σ(k) satisfying and σ(0) = j ω σ k (0) = N L(j ω) D L(j ω) where D L denotes the derivative of D L. Consider the branch of the positive root locus of L that starts from the pole at j ω; from the previous calculation it follows that the proper rational function and R proper rational function. Set G(s) = N G (s)/d G (s) and assume that G possesses a simple pole on the imaginary axis at j ω, and that j ω is not a pole of R. By using the previous result, it is easy to obtain that the branch of the positive root locus of RG that starts from the pole at j ω points toward the right-half of the complex plane if ( ) arg NG (j ω) D G (j ω) R(j ω) < π 2. References [1] G.J. van der Merwe and L. van der Merwe, Invertersthe investigation to the optimal topology to the designing of a sinewave inverter range for the use 199

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