Automated Digital Controller Design for Switching Converters

Transcription

1 Automated Digital Controller Design for Switching Converters Botao Miao, Regan Zane, Dragan Maksimović Colorado Power Electronics Center ECE Department University of Colorado at Boulder, USA {botao.miao, regan.ane, Abstract This paper presents an approach to automated digital controller design for switching power converters. Starting from an experimentally identified frequency response, parameters of the converter transfer function are estimated using a least logarithmic squares method. A direct digital design method then yields a compensator that results in the desired closed loop response. Application of the method is illustrated on an experimental digitally controlled 9 W DC-DC forward converter. I. INTRODUCTION Digital control of high-frequency switching power converters offers potential advantages of reduction of the number of passive components, programmability of control and system parameters, as well as system integration, calibration and diagnostics capabilities. Digital techniques also increase the feasibility of automation in design and operation, including on-line identification of converter dynamic responses [, 5, 6], tuning of controller parameters based on identification results [7], detection and adaptive change of compensator parameters [8] and application of other adaptive control techniques [9]. This paper focuses on an automated approach for digital controller design, which relies only on experimental data extracted from the digital controller itself to identify the system dynamics followed by an automated algorithm to derive a controller design to meet a desired closed-loop response. The identification and automated V g Switched-Mode Power Converter controller design algorithms can be performed in Matlab or other software for simple off-line design or can be integrated into the system hardware for a fully automated self-designing controller capable of re-tuning control parameters on command, as shown in the block diagram of Fig.. The controller is implemented digitally, including a self-designing block (identification and desig and a programmable compensator. With high flexibility, digital control algorithms do not need to be restricted to discrete versions of analog designs. In particular, it is possible to formulate controllers that, using direct digital design methods, will produce the desired closed loop response. In this paper an automated algorithm is developed to drive the closed loop response to behave as a first-order system with time delay and unity gain. However, in order to automatically design the high performance controller, an accurate parametric model is necessary. Particularly, a Z-domain transfer function is required for the switched-mode power converter. By injecting a Pseudo Random Binary Signal (PRBS), the correlation method can be used to derive the accurate impulse response of switching converters [5, 6]. The procedure of this automated digital controller design is illustrated in Fig.. Starting from this result, this paper focuses on the parametric identification of converter dynamics followed by direct digital compensator design. The paper begins with a review of the identification method that is applied to generate the impulse response of the power converters in Section II, followed by the parametric Frequency response identification u[n] Programmable compensator Compensator parameters V ref Parametric identification of converter transfer function Direct digital compensator design Identification & design Hardware realiation Fig. : Block diagram of intelligent converter module including an identification and design block used to determine and upload appropriate compensator parameters. Fig. : Automated digital controller design procedure /5/$. 5 IEEE. 79

2 identification to obtain the Z-domain transfer function based on frequency response in Section III. The automated controller design algorithm is described in Section IV. Section V describes an experimental digitally controlled 9 W 5 V-to-5 V forward converter with an FPGA-based controller. Simulation and experimental results validate the automated design approach and demonstrate good performance of the resulting closed-loop system. II. IDENTIFICATION OF THE POWER CONVERTER IMPULSE RESPONSE In this section we review application of the cross correlation method to identify impulse responses and frequency responses of digitally sampled and controlled switching power converters [5, 6]. In steady state, for small-signal disturbances, a power converter can be regarded as a linear time-invariant discrete-time system, where the sampled system can be described by y( h( k) u( n k) v( () k where y( is the sampled output signal; u(k) is the input digital control signal; h(k) is the discrete-time system impulse response; and v(k) represents disturbances, including switching noise, measurement error, quantiation noise, etc. The cross-correlation of the input control signal u(k) and the output signal y( is: R uy n n u( y( n m) h( R uu ( m R uv where R uu is the auto-correlation of the input signal. Now, if the input control signal u(k) is selected to be white noise, then we benefit from the following characteristics: Ruu δ () Ruv In other words, the auto-correlation of the input is an ideal delta function and the cross correlation of the white noise input with disturbances v(k) is ideally ero. Under the conditions of (), the cross-correlation of () can be reduced to R uy h( m) (4) Thus the cross correlation of the input and output sampled signals give the discrete time system impulse response. The control to output transfer function of the target power converter in frequency domain can then be derived by applying the Discrete Fourier Transform (DFT) to R uy (m): DFT Ruy H( jω). (5) This theoretical result requires the ability to generate white noise as an input perturbation to the system. A simple compromise in a digitally controlled power converter is to approximate white noise through use of PRBS perturbations. The PRBS is periodic and deterministic. The n-bit PRBS can () V g v in FPGA controller Switched-Mode Power Converter PRBS u[n] D Correlation Impulse Response Programmable Compensator be easily generated using an n-bit shift register with feedback. The data length for one period of an n-bit maximum length PRBS is given by M n -, and the signal itself has only two possible values: ±e. In the identification there are some constraints to choose the bit number n and sampling frequency f of PRBS [5]. The desired frequency range is f /M to f / (after DFT), and the frequency resolution is f /M. To reduce the cost of computation, a practical and efficient algorithm is derived based on the fast Walsh-Hadamard Transformation (WHT) [6], demonstrating that the identification can be implemented online with relatively low-cost hardware. Figure shows a schematic diagram of a switching power converter with identification hardware built into the digital controller. In normal operation, the system operates in the closed-loop mode (switch is at position ). When operating under steady-state, the converter duty cycle D is fixed. The identification procedure is as follows: open the loop (switch at position ), inject the PRBS u into the duty cycle command, d D u, while collecting the resulting disturbance e of output voltage; perform the cross correlation of u and e, and obtain the control-to-output impulse response of the converter. There is a compromise between the magnitude of the PRBS and the quantiation level of the A/D converter. If the disturbance caused by the injected PRBS is desired to be small, then a higher resolution A/D converter with a smaller quantiation level is required to maintain the identification precision. Assuming the required A/D resolution is available, the minimum PRBS magnitude (and the resulting output voltage perturbatio is limited by the noise present in the system. III. PARAMETRIC IDENTIFICATION OF THE CONTROL-TO-OUTPUT TRANSFER FUNCTION In general, system identification is divided into parametric and nonparametric methods []. In parametric methods, a system model is assumed, and the identification amounts to an estimation of the model parameters. The correlation method H - A/D V ref Fig. : Functional block diagram of a switched-mode power converter with an identification module 7

3 described in Section II results in nonparametric identification of the converter impulse response. We then convert the time domain data into the frequency domain through the FFT in order to perform parametric identification based on the frequency response data. The parametric identification is based on the logarithmic least squares method [, 4], which fits template data to the experimental frequency response data to obtain the transfer function by minimiing a cost function. A digitally controlled converter (buck, boost or buck-boost) operating in continuous conduction mode (CCM) can be regarded as a second order discrete-time system [] p ( ) H, (6) p p p where P {P, P, P, P 4 }are the parameters to be estimated. When operating in CCM, the boost and the buck-boost converter exhibit control-to-output transfer functions containing two poles and a right half-plan (RHP) ero. The buck converter exhibits two poles and a LHP ero. Each of the converter types share the same system model with different parameters. The model can be expanded to account for additional components, such as an input filter, if desired. The cost function to be minimied is given by [4] jωit N H ( e, P) J ( P) {[ln ] M ( ω ) i ωi θ ( ωi )] }ln[ ] ω i i [ H ( e jωit, P), (7) where ln denotes the natural logarithm. M ω ) ( i and θ ( ω i ) are the magnitude and phase data, respectively, obtained by nonparametric frequency response identification. j H ( e ω i T, P) are the model frequency response data. N is the number of frequency points. The weighting term ln[ ω i / ωi ] may be eliminated if the frequency points are evenly distributed on the logarithmic axis. The parametric identification reduces to a search for the set of parameters P that results in the best fit to the frequency-response data, i.e., that minimies the cost function (7). The Quasi-Newton search method is applied to minimie the cost function. In the search process, initial values are chosen to facilitate convergence in the search. In our applications, the initial values are determined from the estimated nominal values of the converter devices. When the magnitude of directional derivation in the search direction is less than a preset tolerance value, the search is completed and the final values of the parameters are obtained. The method based on the cost function (7) has a number of advantages (as detailed in [4] in more general terms) when applied to converter frequency responses. Low-gain regions are not neglected in the best-fit search, which means that the method is well suited for frequency response data over a wide dynamic range. Second, the magnitude and phase can have different weighting functions, allowing emphasis to be placed on frequency bands of interest. Third, for a minimum phase transfer function, the logarithmic frequency response magnitude data is sufficient to identify the parameters. IV. DIRECT DIGITAL COMPENSATOR DESIGN In order to avoid approximations and errors associated with continuous-to-discrete conversion required for indirect digital design methods [], we apply a direct digital design procedure. This is especially useful here where the system response has been identified directly from the sampled data in digital hardware as described in Sections II and III, which results in an accurate discrete-time identification including quantiation errors and conversion delays. d[n] ( H( Converter Z - Process delay Figure 4 shows a closed-loop block diagram of a digitally controlled switched-mode converter. H( is the Z-domain transfer function of the converter. The processing delay block takes into account the time interval between sampling the output voltage error and changing the switch duty cycle. This delay depends on hardware implementation details including the A/D conversion time and computation delays. In this paper, we assume that the delays amount to one switching period. Hence the Z - block is included in the model of Fig. 4. The transfer function combines the converter and the processing delay blocks, H. (8) ( is the discrete time transfer function of the compensator. Ignoring the A/D and quantiation, the closed-loop reference- to-output voltage transfer function is: v G H out C Gvr. (9) vref GC The ideal compensator would force (9) to unity, which of course is not possible in a real system. A practical compensator design method is applied here based on the Internal Model Control, which has been applied in motor control []. A. Minimum phase systems If is minimum phase (e.g. buck converter), A/D V ref Fig. 4: Block diagram of a closed-loop digitally controlled switching converter 7

4 has no poles or eros outside the unit circle. We can design the compensator to force the closed loop system to behave as a unity-gain first-order system plus time delay, ( q) Ts / τ G, q e, k. () vr q The time constant τ is used to represent the rate of response and T s is the switching period, which is the same as the sampling interval of the discrete-time system. The constant k represents the number of unit delays in the response. Then from (9) and (), the compensator transfer function can be found as q GC. () q ( q) The time constant τ can be used as a tuning parameter to vary the speed of response. A lower τ represents a faster response. In the extreme case, τ, q, which results in the quickest, deadbeat response, where the output perfectly tracks the reference with a delay of k cycles. Unfortunately, the deadbeat response is very sensitive to modeling errors and the practical system is prone to instabilities. In another extreme case, when τ is very long, q, which means that the feedback loop is open. The choice of τ is a compromise between the speed of response and adequate stability margins. As an example, we consider the choice of the time constant τ for second-order systems with k. The compensator () introduces two poles to the closed loop system, at and at q. A smaller τ means that the pole at q is closer to the unit circle, which implies a reduced stability margin. Considering the and A/D quantiation effects, the stability margin of the loop gain should be sufficiently high to avoid limit-cycling oscillations. A gain margin condition is derived in [] 4 GM log( ) L > 4. db. () π For the case of k, when τ T s, the gain margin is.54 db; when τ T s, the gain margin is 4.5 db. So, in order to make the loop gain satisfy (), τ should be at least T s. For example, a discrete time control-to-output transfer function of a buck converter with typical parameters is given by.76(.7). () ( ) Setting k and choosing τ T s, from () the compensator becomes.897 ( ) (4) ( )(.7)(.85) Figure 5 shows the step response obtained by MATLAB simulation of the closed-loop buck converter discrete-time small-signal model (), (4) when the reference voltage V ref changes from ero to V. B. Non-minimum phase system When represents a non-minimum phase system which has eros outside the unit circle (e.g. boost or buck-boost converters), () cannot be used directly due to the resulting (unstable) pole outside the unit circle. Assuming that the ero of the transfer function (6) is outside the unit circle, the closed loop system can be forced to be C ( )( q) Ts / τ Gvr, q e, k q C (5) where the constant term C is added in the numerator to maintain the unity DC gain. From (9) and (5), the corresponding compensator is given by Time (sec) x -4 Fig. 5: Step reference response obtained by simulation of the closed-loop buck converter discrete-time small-signal model when the reference V ref is changed from ero to V Time (sec) x -4 Fig. 6: Step reference response obtained by simulation of the closed-loop boost converter discrete-time small-signal model when the reference V ref is changed from ero to V. 7

5 v in L C 4 V g FPGA controller u[n] Programmable compensator Compensator parameters Identification & design A/D H V ref Fig. 7: Digitally controlled forward converter: V g 5 V, V out 5 V, I out 6 A, :: transformer, L µh, C µf, f s kh. The digital controller is implemented on a Xilinx Virtex-II FPGA. p C ( ) p p GC p q q C ( )( q) p (6) There is no unstable pole in the compensator. As an example, a discrete time control-to-output transfer function of a boost converter is described as.8(.5) (7) ( ) We set k to make the compensator feasible, and choose τ T s. From (6), the compensator is given by ( ) (8) ( )( ) A step response of the closed-loop boost converter discrete-time small-signal model (7), (8) is shown in Fig. 6. V. AUTOMATED CONTROLLER DESIGN: EXPERIMENTAL EXAMPLE The digitally controlled forward converter of Fig. 7 was constructed to experimentally test the parametric identification method described in Section III, and to verify design of the digital controller based on the identification result, as discussed in Section IV. The digital controller was implemented using a Xilinx Virtex-II FPGA. The FPGA-based controller includes a -bit digital pulse-width-modular (), a programmable compensator, and a system identification module. The converter output voltage, scaled by a : resistive voltage divider (H.), is sampled by an A/D converter (TI-THS). The sampling rate equals the Fig. 8: Experimental results of frequency response identification obtained by experimental data (points) from the correlation method and the resulting parametric identification (solid line). switching frequency, f s kh. The A/D converter is -bit. When performing the identification, all bits are used to improve the precision. When the system is operating closed loop, only the 7 most significant bits are used to avoid limit-cycling. In this section we describe how to automatically design the digital compensator for the forward converter according to the design flow shown in Fig.. First, the experimental frequency response of converter is derived by the correlation identification method described in Section II. In our experiment, the magnitude of PRBS is selected to be.5. The length of PRBS is. So the impulse response we obtained has points. Then taking DFT, the effective frequency response has 5 points, and maximum frequency is 5 kh (half of the sampling frequency), as shown in the experimental results of Fig. 8. The next step is to specify the transfer function template in order to apply the parametric identification method described in Section III. The template transfer function is p ( ). (9) p ( ) p p We then perform the search algorithm described in Section TABLE I THREE SETS OF THE BUCK CONVERTER PARAMETERS USED TO INITIATE THE PARAMETRIC IDENTIFICATION H L(μH) C(μF) V g (V) R(Ω) A 5 B C 7

6 5 Bode Diagram k Magnitude (db) Phase (deg) Ident A B C Frequency (rad/sec) Fig. 9: Bode plots of the control-to-output transfer functions using the parameter from Table I, and obtained by the parametric identification. III to obtain the parameters P. Figure 8 shows frequency responses of the transfer function obtained by the experimental data from the cross-correlation method of Section II (points), and the parametric identification of Section III (solid line), respectively. A close match can be observed. The initial value P of the parameter P can be obtained from the forward converter averaged model based on estimated device parameters, ignoring non-idealities and tolerances. The parameteric identification method described in Section II is robust against errors in the selection of the initial values of the parameters. Table I gives three sets of parameters used to initiate the parameteric identification. Case A corresponds to the actual nominal values of the forward converter parameters. Cases B and C correspond to the parameter values quite different from the actual converter parameters. Nevertheless, the parametric identification in all three cases converges to the same set of parameters, P { }, demonstrating that accurate a-priori knowledge of the converter parameters is not required for convergence of the Z - k k k 4 Z - d[n] parametric identification search. The corresponding frequency responses are shown in Fig. 9. The resulting -domain transfer function is given by.76(.7) H. () ( ) Based on (), selecting k, and τ T s, from () we obtain the compensator.897 ( ). () ( )(.7)(.85) The compensator is implemented in a parallel structure with the following form k k k k, () a a which becomes () when [k, k, k, k 4, a, a ] [.897,.66, -.57, -.997,.7, -.85]. Figure shows a block diagram of the compensator realiation. Finally, the digital compensator () is realied in the FPGA hardware using Verilog HDL coding. Figure and Fig. show the simulation (Verilog HDL) and experimental step responses of the digitally controlled forward converter, respectively, when the reference voltage V ref is switching between. V and.5 V, so that the output voltage is a a Z - Z - Fig. : Block diagram of the compensator structure Fig. : Step response obtained by simulation of the digitally controlled forward converter when V ref is switching between. V and.5 V. Top is duty cycle and bottom is the output voltage. Fig. : Experimental output voltage (ac coupled) step response of the forward converter when V ref is switching between. V and.5 V. 74

7 Fig. Load transient responses obtained by simulation of the digitally controlled forward converter. From top to bottom are the duty cycle, the output voltage and the load current. switching between V and 5 V. Figure and Fig. 4 show simulation and experimental load transient responses, respectively, when the load current is switching between 6. A and.4 A. The oscilloscope waveforms are the ac coupled output voltage and the load current i load. The simulation and experimental results demonstrate good dynamic performance resulting from the proposed automated digital controller design method. VI. CONCLUSION This paper presents an automated digital controller design method for switching converters. Based on the experimental frequency response data, parameters of a defined Z-domain transfer function model are estimated using a least squares method. Using the experimentally identified discrete-time control-to-output transfer function of the converter, a direct digital compensator design method is described to achieve the desired closed-loop dynamic behavior. Simulation and experiments show that the proposed method can give reliable identification results and good dynamic performance in the presence of parameter uncertainties, switching and quantiation noise. The approach is well suited for automated off-line system design, or for on-line adaptive control in digitally controlled switching power converters. As an example, a digitally controlled 5-to-5 V forward converter operating at kh is constructed and the proposed method is tested using an FPGA-based digital controller, demonstrating high-performance closed-loop dynamic voltage regulation. ACKNOWLEDGMENT The authors wish to acknowledge Mr. Robert Button at the NASA Glenn Research Center in Cleveland, Ohio who Fig.4 Experimental load transient responses: ac coupled output voltage (top) and load current (bottom). sponsored this work as part of NASA's research and development program entitled "Intelligent Power Management and Distribution Systems". REFERENCES [] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, Second Edition. Norwell, Mass. Kluwer Academic Publishers, [] L. Ljung, System identification: theory for the user, Second Edition, Prentice- Hall, N.J., 999 [] Pintelon, R. Guillaume, P. Rolain, Y. Schoukens, J. Van Hamme, H, Parametric identification of transfer functions in the frequency domain-a survey, IEEE Transactions on Automatic Control, Vol. 9, Issue., 994, pp [4] M.D. Sidman, F.E. DeAngelis, G.C. Verghese, Parametric system identification on logarithmic frequency response data, IEEE Transactions on Automatic Control, Vol. 6, Issue , pp [5] B. Miao, R. Zane, D. Maksimovic, A modified cross-correlation method for system identification of power converters with digital control, IEEE PESC 4. pp [6] B. Miao, R. Zane, D. Maksimovic, Practical on-line identification of power converter dynamic responses, IEEE APEC 5. pp [7] A. S. McCormack and K. R. Godfrey, Rule-based autotuning based on frequency domain identification, IEEE Transactions on. Control Systems Technology, Vol. 6, No. pp. 4-6, 998. [8] B. Miao, R. Zane, D. Maksimovic, Detection of Instability and Adaptive Compensation of Digitally Controlled Switched Mode Power Supplies, IEEE APEC 5, pp [9] Karl J. Astrom, Bjorn Wittenmark, Adaptive control, Addison Wesley, 989. [] Raymond T. Stefani, Bahram Shahian, et al, Design of Feedback Control Systems, Fourth Edition. New York, Oxford University Press, [] L. Harnefors, H.P. Nee, Model-based current control of AC machines using the internal model control method, IEEE Trans. On Industry Applications, Vol. 4, Issue., 998. pp. -4. [] H. Peng, D. Maksimovic, A. Prodic, E. Alarcon, Modeling of quantiation effects in digitally controlled DC-DC converters, IEEE PESC 4, pp: