Chapter 4 Design of a Digital Tri-mode Controller

Transcription

1 Chapter 4 Design of a Digital Tri-mode Controller As described in section.4, digital control is not new in the field of Power Electronics. It is often associated with DP or other micro-processors. Generally the digital control system presents sufficient resources to accommodate the modest switching frequency of the converter in the range of khz. However in low-level battery-powered applications, switching frequencies in the range of MHz and plus are necessary to reduce the size of passive components, which challenges the feasible DP-implementation. Thus for the considerations of computation speed and power consumption, the dedicated digital controllers used in highfrequency low-power MP are supposed to implement in the FPGA/ or AIC with the capability of high-speed computation and low-power consumption. One issue of the monolithic integrated digital controller design is to meet the high-speed real-time control with high-performance, while consuming low power with small area. ophisticated control strategies can possess better dynamic performances, but the power consumption cost is increasing with added performances. Thus for the high-power converter, the power consumption of its digital controller is not so critical when it is compared with the system overall output power. However in low-power MP, the power consumption of the digital controller may become intolerable and can not be neglected. Besides with the switching frequency increasing, the algorithm computation will consume more and more energy. Furthermore at a certain constant switching frequency, the power consumption depends on the algorithm complexity, such as the step number of computation and area (multipliers and adders etc.). Thus the challenge of digital controller design is to reduce power consumption while keeping high-dynamic performance. Due to the cost/complexity constraints existing in low-power MP with integrated digital controller, most existing digital controller for high-frequency low-power MP with AIC standard implementation [A, A3, A7, B, J, J3, T, Z, Z] are designed using. The dynamic performances of these controllers with respect to load variations are still limited. In order to satisfy the constraints on the load variation to achieve high transient performances and accuracy, the auto-tuning process of the digital controller are proposed [W]. Unfortunately on-line tuning solutions increase algorithm complexity and thus the silicon area of the IC controller and power consumption as well. The practical implementation in high frequency (>MHz) and very low power (<W) is still questionable. 57

2 In this chapter an off-line tuning RT controller is presented [X]. The so-called RT robust controller offers better performances and rejection of disturbance when it is compared to a controller. Based on the pole-placement method combined with the sensitivity function shaping, this chapter investigates an off-line automated approach using fuzzy logic and genetic algorithm to correctly specify the desired performances by adjusting the sensitivity functions in the frequency domain where it is necessary. The robust RT controller has better performance than that of but pays at cost of a structure with more multipliers, which probably results in larger area in future AIC implementation. In order to minimize power consumption and offer fast dynamic response, a Tri-mode controller including transient-state, steady-state and stand-by three modes is proposed. The robust RT control which gives access to high dynamic performances is adopted in transient state. In steady-state a control law is applied to maintain the output stable, and in stand-by the controller is clocked at a frequency lower than the converter switching frequency. 4. ensitivity Functions for Robust Control The closed-loop system operates in presence of disturbances and it is important to assess the effects of these disturbances upon the plant output and input. In order to quantify system dynamics, robustness and noise rejection properties of tested controllers, the sensitivity functions are introduced [C4]. These sensitivity functions play a critical role in the design of the controller. These functions (or some of them) will be shaped for the rejection of the disturbances and the stability of the closed-loop system [I4]. 4.. ensitivity Functions for MP For DC-DC switching converter, three types of disturbances will be considered in the modelling: the output disturbance converter noise) and control noise MP (P) and its controller (K) with the three disturbances. W y (e.g. load variation), measurement noise W b (e.g. A/D W u (e.g. PWM noise). Fig. 4- represents the model of a From Fig. 4-, it can be established the following relation that leads to the sensitivity functions. The MP output voltage of MP is given by y Vref Wy yb Wb yu W u (4.) 58

3 V ref - (DPWM) W u (Load variation) W y x K x P x y Controller Plant x (A/D converter) W b Fig. 4- Block diagram of a typical MP with disturbances where is the closed-loop transfer function, let the open-loop transfer function L K P, K P L K P L (4.), yb and yu are respectively the output-to-output, measure-to-output and control-to output sensitivity function. The output-to-output sensitivity disturbance W y and plant output y is given by K P L The measure-to-output sensitivity plant output y is given by The control-to-output sensitivity y is given by yb between the load variation yb between the disturbance measurement noise W b and K P L K P L (4.3) (4.4) yu between the disturbance PWM noise W u and plant output yu P P K P L (4.5) Constraints or disturbance rejections are naturally expressed in terms of frequency sensitivity shapes. For a given controller, the sensitivity functions allow to evaluate the controller behavior in relation to the desired attenuation constraints. Fig. 4- is an example of the gain plot of sensitivity functions for a buck converter. PWM and output noise attenuations are pointed considering a MHz PWM frequency and a 3kHz (output filter frequency f LC ) output disturbance resonance. at low frequency determines the steady-state properties of the system. The bandwidth of yb defines the influence of measurement noise on the output voltage and the closed-loop bandwidth since it has the same transfer function as expect for the sign. The gain of yu verifies the rejection of control perturbations such as the PWM-related noises. 59

4 [db] - - output disturbance rejection Band width Modulus margin yb attenuation of steady-state yu PWM noise attenuation f [KHz] s Fig. 4- Example of sensitivity functions for a buck converter 4.. Robust Modulus and Delay Margins Among these sensitivity functions, the output-to-output sensitivity function is the key indicator for the nominal and robust performance as well as for the robust stability of the closed-loop system. The inverse of the maximum value of the output sensitivity function, i.e., the inverse of its H norm, gives the minimum distance between the Nyquist plot of the open-loop system and the critical point (-, j) (see Appendix A). This quantity, called the modulus margin M, is a significant robustness indicator as compared to the phase and gain margins. Moreover conditions for ensuring a certain delay margin which is also a very important robustness indicator, particularly in the high frequency region, can also be expressed in terms of the shape of the output sensitivity function. The modulus margin M corresponds to the tolerance related to the model mismatch in the high frequency range, and the delay margin gives the maximum delay which can be neglected. The briefly review of the definition of modulus margin M and delay margin are described in Appendix A. In order to ensure robustness, generally the modulus margin M is kept higher than.5 and the delay margin period T s [I, I4], i.e. 4. Design of and Robust RT Controllers M T s.5 must be higher than the switching (4.6) Based on the useful state-space averaging model, the transfer functions of a switched buck converter can be developed using small signal analysis [D3]. Considering the Current 6

5 Continuous Condition (CCM) mode, the transfer function of the buck converter can be written in continuous-time s-domain (see Appendix B and C): Vˆ out s ( srcc ) Vin P s ˆ d s s ( R R) LC s( R C R C R R C R L R) R R C L C L C L (4.7) Transfer equation (4.7) into discrete-time z-domain, the buck converter can be regarded as a second-order system [R]: P z b z b z az a (4.8) 4.. Control Design As mentioned in section.4., the controller is the most common type of digital control used in digitally-controlled high-frequency and low-power integrated MP. Here a discrete-time controller is designed for comparison purpose with RT controller. The discrete-time filtered controller can be written as [X]: K z r r r z z r z r r r z r z z s z z s (4.9) where r, r, r and s are the controller parameters to be determined by the pole placement method. The digital control system including the controller P z is shown in Fig V ref e z x - K d z Vout K z P(z) controller Buck converter z and a buck converter Fig. 4-3 Block diagram of -controlled buck converter Where V ref is the reference voltage, V out is the output voltage, e is the voltage error, and d is the PWM duty ratio. The closed-loop transfer function is: V z K z P z out V z K z P z ref etting r r a and r r a to cancel the poles of P z with the zeros of K rb z rb rb z rb z s r b z r b s z p z p z, then (4.) (4.) 6

6 where p and p are to be determined by the desired closed-loop dynamics which correspond to the second-order dynamics with a pulsation cr and a damping ratio cr (in s-domain s cr cr crs cr ). Finally the parameters are determined as r p p b b r r a r a r s r b p (4.) The buck circuit elements are L 4.7µH, C µf, R 5, V 3.V, V.5V and sampling frequency is set to switching frequency f 4MHz. Thus the parameters of discretetime transfer function for buck converter in equation (4.8) can be obtained: s a.989, a.9895, b.34, b. (4.3) and the open-loop pulsation can be calculated 9834rd/s. Considering the trade-off between the dynamic behavior and robustness (modulus and delay margins), cr is set to 6 times the open-loop pulsation corresponding to 5385 rd / s. It can be noted that this pulsation is 5 times smaller than the Nyquist-hannon sampling frequency (4MHz). With the closed-loop damping ratio cr.7, the parameters p and p of discrete-time equation (4.) can be calculated: p.493, p.5586 (4.4) ubstituting equation (4.3) and (4.4) into (4.), then the parameters of controller can be acquired: r 4.587, r 8.636, r 4.43, s.7959 (4.5) From equation (4.9) and Fig. 4-3, we can get the digital controller: d z r z r z r K z e z z z s in out (4.6) ubstituting equation (4.5) into (4.6), the controller is detailed as follows: d k r e k re k r e k s d k s d k 4.587e k 8.636e k 4.43e k.7959d k.7959 d k (4.7) where d k is the discrete value of output (duty ratio), ek is the discrete value of the error signal between Vref current k and V out, d ki and eki are the values in i cycles before the cycle respectively. The determination of the fraction precision of the parameters will be discussed latter in section 4..3 (Matlab simulation). 6

7 [db] The corresponding sensitivity functions, yb and yu of controlled system are presented respectively in Fig For an output disturbance with a pulsation of resonance), the gain of (LC filter on gives the information on the disturbance rejection. In the studied case 5kHz. It can be seen that stability robustness, the modulus margin is about -8dB. Concerning the M, phase margin and delay margin respectively are: M.83, 6, T s.5 effect, sensitivity functions are plotted until the Nyquist frequency.. Due to the sampling - (w ) yb yu f [KHz] s Fig. 4-4 ensitivity functions for the -controlled system 4.. Robust RT Control Design Compared to the control, RT allows taking different dynamics for the reference tracking and the rejection of disturbance rejection [I, I3]. A RT controller is considered here in order to obtain a better output disturbance rejection while keeping a good robustness. The structure of a RT-controlled buck converter system is presented in Fig Vref B z m A z m T(z) RT control e z x /(z) x - R(z) (DPWM) W u d z P Plant (Load variation) W y Fig. 4-5 Digital RT-controlled buck converter system x y z x (A/D noise) W b where Rz (), zand () T() z are the polynomials of the digital RT controller, Pz () is the discrete-time model of the buck converter, W y, Wb and W u are respectively the disturbances of output-to-output (load variation), measure-to-output (A/D sampling noise) and control-to 63

8 output (PWM signal noise) and B ( z) A ( z ) is a reference model which determines the m m reference tracking dynamics. The reference tracking model is generally designed as a secondorder transfer function so that the reference dynamics may be slower than the disturbance rejection in order to avoid control saturation. This tracking model not discussed here, and the design attention is mainly paid to the issue of attenuation for the rejection of load variation. If the discrete-time buck model Pz () is described in form of the transfer function P z B z A z, where B(z) and A(z) are polynomials, then the sensitivity functions can be expressed as: yb yu A( z) ( z) A( z) ( z) B( z) R( z) B( z) R( z) A( z) ( z) B( z) R( z) B( z) ( z) A( z) ( z) B( z) R( z) (4.8) From these expressions, it can be noted that the three sensitivity functions have the same denominator D( z) A( z) ( z) B( z) R( z ) which determines the closed-loop poles and can be distinguished to the dominant and auxiliary closed-loop poles. The knowledge of disturbances leads to design the RT controller in terms of pole and zero assignments. ome fixed parts can be specified for the polynomials z () and Rz (). For example to insure the output accuracy, a pole for z (integral part) in (z) is necessary for static error elimination. The closed-loop poles are chosen either for filtering effects in certain frequency regions or for improving the robustness of the closed-loop system. For an output disturbance at pulsation, the lower the gain of the better the attenuation of the output disturbance rejection. However it can be shown that the larger the attenuation of the larger the area of the maximum value of at, over the zero value [I, I, I3, I3, I4]. It can induce an increase in. As the maximum value of is inversely proportional to M, a larger output noise rejection leads consequently to a worse robustness. More details can be found on [I]. How to determine a controller which offers a trade-off between the robustness and a good rejection of disturbances? This can be described as an optimization problem by defining a cost function which qualifies the controller robustness and noise rejection properties. 64

9 Fuzzy logic is suitable to qualify the robustness of a controller and noise rejection properties [C]. Indeed the frontier between a good controller and a bad controller is not strict. For example if one considers the modulus margin is correct if it is higher than.5, it is clear that a controller will not be qualified with a bad robustness getting to good by crossing this value. With membership functions of fuzzy logic, the controller quality can be evaluated continually from bad to good across medium. An example of membership functions qualifying the gain at ( G ) and the modulus margin ( M ) is shown in Fig. 4-6 and Fig. 4-7 respectively. G is normalized over {- } and M uses its natural scale. The output membership function is given in Fig The stability robustness can be expressed by fuzzy rules as defined in Table. 4-. After the disfuzzyfication, the robustness analysis is quantified by the function V, f G M which corresponds to a surface as presented in Fig It can be seen that for M.5, the lower the values of G the better the output function V. In the same way other membership functions and fuzzy rules related to the delay margin ( ) and other sensitivity functions can be defined to quantify constraints of robustness and satisfy the requirements of disturbance rejection performances. A weighted sum of all fuzzy functions defines the quality function to maximize. Membership function of Gw.5 Good Medium Bad G w Membership function of M.5 Bad Good M Fig. 4-6 Input membership function for G Fig. 4-7 Input membership function for M Membership function of V.5 Bad Medium Good V M Bad Good G w Table 4- Fuzzy Rules Bad Bad Bad Medium Bad Medium Good Medium Good Fig. 4-8 Output membership functions 65

10 The optimization problem is addressed by a genetic algorithm which is a stochastic approach based on the mechanism of natural selection. Each variable X i (chromosome ) are coded on n i bits between a minimum value, min i, and a maximum value max i. An initial population of strings (individual ) is arbitrarily created. Genetic algorithm makes it change by using three main operations: reproduction, crossover and mutation in order to maximize an objective function ( fitness value ) [D4]. The performed computation time can be important but it is offline, so this is not a limitation for real-time implementation. The offline approach used to determine the controller parameters is summarized in Fig. 4-. This optimization problem is solved in the Matlab/ imilink environment. Fig. 4-9 Fuzzy function V Initial parameter setting Computing sensitivity functions Computing module margins Output disturbance rejections... Evaluating control performances (fuzzy logic) Generating new parameter sets (genetic algorithm) Terminnation Criteria satisfied? No Yes Optimal parameter set Fig. 4- Off-line approach used to determine the controller parameters 66

11 For the same buck converter as described previously in section 4.., the denominator of the sensitivity function is chosen as follows to determine a RT controller which presents a good robustness and a good attenuation of the influence of the output disturbance at 5kHz (output filter cut-off frequency). The denominator D( z) A( z) ( z) B( z) R( z ) can be represented as: Where the dominant closed-loop part disturbance rejection, the auxiliary part D z c z p z p z (4.9) cz determines the desired performance of pz pz allows introducing filtering effects in some frequency regions. o the coefficient c can be varied between. and.99, pz pz corresponds to a pair of complex zeros for which the frequency band varies between Thus the coefficients c, 5 rad / s to 5 3 rad / s and damping ratio is between.3 and. and constitute three degrees of freedom (or chromosomes) for the optimization problem. For each combination of c, and (i.e. each individual for the genetic algorithm), the fuzzy logic quantifies the quality function (or fitness value). The genetic algorithm then finds the optimal solution for c, and over twenty generations with about thirty individuals for n i 6, crossover probability.9 and mutation probability are plotted in Fig. 4-, where c.7, rad / x 5.9 s.8..the individuals which have been tested by the genetic algorithm.7 c rad / s and.6. The best set of parameters Fig. 4- Diagram of individuals distribution in the genetic algorithm

12 [db] In the RT structure of Fig. 4-5, the corresponding optimal polynomial Rz (), z () and T() z are calculated by solving the Bezout equation [I]: d k T w k T w k T w k T w k 3 3 R y k R y k R y k d k d k (4.) where d k is the discrete value of RT output (duty ratio), wk and y k are the discrete values of the Vref th i cycles respectively. For fs 4 listed as below. and V out respectively, d k i, wki and R z z z y ki are the values in the precious MHz application the parameters of the RT controller are z z z T z z z z The corresponding sensitivity functions of (4.), yb and yu for the RT controller are given in Fig. 4-. The gain of at (LC filter resonance) is -47dB. The good robustness is represented with modulus margin M RT.79, phase margin 6 o RT and delay margin RT Ts. ( Ts is the switching period). The determination of the fraction precision of the parameters will be discussed latter in section 4..3 (Matlab simulation) (w ) RT yb yu f [khz] s Fig. 4- ensitivity functions for RT controller The hardware implementation of the controller is quite simple: it just needs a few memories, multipliers and adders in FPGA/AIC. 68

13 [db] 4..3 imulation Comparison In order to quantify the controller dynamics, robustness and noise rejection properties, the most important output-to-output sensitivity function is presented in frequency domain in Fig. 4-3 for the comparison between RT and controllers (derived from Fig. 4-4 and Fig. 4- respectively). It can be seen that the gain of at 5kHz (output filter cut-off frequency) determines the rejection of the load variation disturbance at the output voltage. The lower the gain of at 5kHz, the better the attenuation of this output disturbance. In addition the maximum value of corresponds to the inverse value of the modulus margin M. It is clear that the gain of at 5kHz is -47dB for RT controller against -8dB for the controller whereas their robustness are similar. In other words RT has better attenuation of the load variation disturbance performance than. The performance characteristics of the two controllers (at fs 4MHz ) are shown in Table. 4-. Table. 4- The characteristics comparison of RT and controllers Controller Modulus margin Delay margin Phase margin attenuation of load variation RT M RT.83 RT Ts.5 RT 6o -47db M.79 Ts. 6o -8db db -5 RT -6 3 f [KHz] Fig. 4-3 comparison plot of RT and controllers The time domain behaviour of both controllers ( and RT) is studied using Matlab/ imulink. Considering that the digital controller is finally to be implemented in FPGA/AIC, the controllers parameters and all computations must be represented in fixed-point data 69

14 presentation instead of float-point form. The fixed-point parameters with limited precision probably affect the accuracy of the computation. In order to obtain high accuracy, the parameter s precision is expected to be the highest. However for a fixed word-width register, the availability of parameter s range is contradictory with its precision. Furthermore for certain FPGA/AIC process, the available register s word-width is contradictory with the algorithm computation speed. Therefore the choice for the parameter s precision should be taken into account carefully with the restraints of word-width, parameter s range and capacity of process. In the studied case the ADC model has a -bit (i.e. ek ( )) resolution and the DPWM ratio (i.e. dk ( )) is set to -bit resolution, which meets the condition of non-limit cycle NDPWM N ADC [A7]. Thus the precision of the controller s parameters are expected to be at least as high as that of DPWM. Here we adopt a 3-bit (binary) precision for the parameters which can achieve a 4-bit (decimal) fraction as fine as. (see the parameters above). The modelling of the digitally controlled buck converter is shown in Fig. 4-4, where the buck converter is modelled by a hybrid model [] using Matlab s-function. In order to keep the simulation close to practical implementation, all the calculation are computed in fixed-point computation with 3-bit fraction. Fig. 4-5 shows the dynamics response of the RT and the controller operating at 4MHz respectively when the load changes from.3a to.46a (R: 5Ω 3.3Ω). In order to validate the disturbance rejection in larger range of variation, Fig. 4-6 shows the dynamic results when the load changes from 3mA to.46a (R: 3Ω 3.3Ω). It can be seen that both controllers can work in large range of load variation. The transient response of the RT controller is superior to the controller since it offers shorter response time and produces smaller undershoot and overshoot on the output voltage. PWM -bit In Out Vref -bit d D[N] C(t) Ramp oft start Vref sampling Vout controller Vin clock t FixPit Fixed-Point etting -bit Out In Vout sampling R Buck -function Buck Fig. 4-4 The modelling of the digitally controlled buck converter in imulink 7

15 duty ratio Unit: A / div Unit: V / div control RT control Time: / div x -4 (a) Output voltage V out RT control control Time: / div x -4 (b) Inductance current I L RT control control Time: / div x -4 (c) PWM duty ratio d Fig. 4-5 Dynamic response of both controllers when load changes from.3a to.46a: output voltage V out (a), inductance current I L (b) and PWM duty ratio d (c) 7

16 duty ratio Unit: A / div Unit: V / div control RT control Times: /div x (a) Output voltage V out RT control control Time: / div x -4 (b) Inductance current I L RT control control Time: / div x -4 (c) PWM duty ratio d Fig. 4-6 Dynamic response of both controllers when load changes from 3mA to.46a: output voltage V out (a), inductance current I L (b) and PWM duty ratio d (c) 7

17 4.3 Tri-mode Controller Based on RT and In order to reduce the energy consumption of the digital controller in the future AIC implementation, a so-called Tri-mode controller is proposed here. The idea of the Tri-mode controller is to minimize power consumption of the control algorithm when it is in steadystate and stand-by mode, and obtain the highest performance dynamic response when the load features a transient variation. The Tri-mode controller includes the and robust RT controllers which have been designed previously Design of a Tri-mode Controller Previous section has detailed the RT controller for high-performance of dynamic response. o it is preferred when the converter load changes fastly. However compared with the controller, this advanced RT algorithm needs more resources such as multipliers, adders, and computation steps to realize. Review the digital controller formula in section 4.., d k r e k re k r e k s d k s d k (4.) and the digital RT controller formula in section 4.., d k T w k T w k T w k T w k 3 3 R y k R y k R y k d k d k (4.3) then the resource consumption and performance of the both controllers can be summarized in Table 4-3. From the simulation results in section 4..3, the dynamic and steady-state performances of both controllers can be also summarized in Table 4-3. It can be seen that the RT implementation in FPGA consumes more area than that of. This means it would consume more area in AIC implementation, resulting in an increase in power consumption. Table. 4-3 Resource consumption and performance of RT and controllers Controller Multipliers Adders Computation steps FPGA area Dynamic teady-state RT More Good Good Less Medium Good In fact when the buck converter works in steady-state, i.e., the load is stable, the primary task of the controller is to maintain the output voltage stable. Thus the control law which features less area but well maintains the output voltage stable is suitable with respect to power consumption. Therefore using the controller for steady-state can not only keep the output voltage stable, but also relax tight requirement of algorithm computation, and save energy in future AIC application. 73

18 In addition many portable devices spend a large part of time in idle mode, i.e. in stand-by mode. Under stand-by conditions, the portable device can not only turn off some external functions such as display backlight, but also can reduce internal power consumption inside the controller. Thus a so-called Quarter controller which has the same structure as the applied in steady-state but clocked at a quarter of the switching clock f s, is considered for stand-by modes. That is to say that the controller will be updated under-sampled mode, i.e. f s 4 changing rate mode, and its computation will renew once per four periods with respect to the buck converter operation. The Tri-mode controller shown in Fig. 4-7 consists of a mode selection block, the RT and the controllers. According to different modes, the mode selection block will select the different controllers: RT for transient-state, for steady-state and Quarter for stand-by mode. Activity signal F CLK f s mode-signal Mode-selection Delay DPWM c(t) e[n] block z- block m tand-by Quarter control d[n] teady-state control d[n] V ref [n] V out [n] Transient-state RT control d[n] Fig. 4-7 Block diagram of the Tri-mode controller 4.3. Operation of the Tri-mode Controller The Tri-mode controller depends on an external activity signal m or a sensor to select the proper controller. Obtaining this activity-signal is out of the scope of the paper but the digital functions inside any low-power systems are able to issue such a signal. For instance in the operation of a portable phone, the activity signal is set low-voltage level m = when it is in stand-by and high-voltage level m = when it is in working state. The change among the three states is performed through a mode-selection block. The function of this block is to detect the state of activity signal and select the corresponding control mode. To eliminate potential stability problems related to dynamic mode switching between different control 74

19 modes [R], the operation of the Tri-mode is designed as shown in Fig. 4-8 (a), and the mode changes procedure management is shown in Fig. 4-8 (b). The tuning time t and t of RT controller for transient tuning can be adjusted to meet the practical application. For example the constant tuning time t tune is set for t and t tune for t here. The en from the voltage error between Vref and V out is normalized in discrete-time data and the maximum tolerant voltage error is set en, where the number means a certain voltage such as 5mV or other values which are chosen by user. In brief the requirements of the signal m, the tuning time t and t, and the maximum tolerant voltage error en, can be adapted in practical implementation. This is not discussed here. load m= ' m= ' m= ' m= ' m= ' Mode I Mode II Mode III Mode II Mode I tand-by teady-state tand-by Transient Fig. 4 (a) Transient Quarter RT Control Control RT Control Quarter 3 4 t t t Tuning t t Tuning time 3 time t 4 e[n]< tand-by control (Quarter) Mode I e[n]> loading m= ' e[n]< and t >t tune (a) e[n]> or t <t tune Transient RT control Mode II e[n]> or t <t tune e[n]< and t >t tune e[n]> unloading m= ' e[n]< teady-state control Mode III (b) Fig. 4-8 Operation procedure of the Tri-mode controller (a) and its state change management (b) The operation procedure of the Tri-mode controller is detailed as follow: ) Initially, after the MP initialization, it is assumed that the controller is in stand-by mode, using the Quarter to regulate the output voltage. It will be kept in this state until the output variation is larger than error unity, i.e., en (normalization), or an activity signal m= is detected. Then the controller switches to procedure ). ) The controller will switch to transient-state using RT control law to regulate the MP output voltage, and this control mode will be maintained long enough tuning ( t t tune) to obtain en condition, which means the MP enters a steady-state mode. 3) In steady-state, controller selects the controller to regulate the output voltage. This state will be maintained until the output variation is larger than error unity, i.e., en, or an activity signal m = is detected. t 75

20 4) The RT controller will be selected again for the regulation of unloading in transientstate. This control mode will be held long enough tuning time t ttune until en condition occur, which means that unloading has finished and the MP arrives in a steadystate mode again. 5) After quit the RT transient tuning, the controller stays in an unloaded situation and will be set in stand-by, which returns to procedure ) again for a next transient cycle. Compared with the Dual-mode controller designed with the simple hysteretic logic method in [Z], this Tri-mode controller offers more flexible selection with three modes to save the energy consumption of control algorithm. Due to the Tri-mode controller where the Quarter updates the whole control-law computation under-sampled mode at 4 f s frequency, evidently it can reduce the energy consumption compared with those alone and RT controllers. Unfortunately there is no sufficient proof to prove the point that how much energy can be saved and how much efficiency can be improved in this current case of FPGA prototype implementation. A.35µm CMO technology AIC implementation of the digital controller is under process and the chip will be available in a coup of months, which enables the performance analysis and energy evaluation. 4.4 ummary In this chapter a classical controller and a robust RT approach have been designed for the voltage-controlled buck converter operating in CCM. Based on the sensitivity functions with respect to the modulus margin M and delay margin, an offline automated design of a robust RT digital controller is detailed. In Matlab/imulink tool box, the Fuzzy logic is used to qualify the robustness of a controller and noise rejection properties, and a Genetic algorithm is used to optimize the robust RT controller. The simulation results are presented to verify that the RT controller offers better performances compared with a classical controller. For the consideration of energy reduction inside digital controller, a Tri-mode controller based on the and robust RT controllers is proposed here. In steady-state, the control law is applied to minimize power consumption and keep output voltage accuracy. While in stand-by mode if the converter is light-loaded, then the controller is clocked at a frequency lower than the converter switching frequency for consideration of energy consumption. In transient load, the RT robust control law is adopted to obtain high performance response. 76