ADAPTIVE CONTROL METHODS FOR DC-DC SWITCHING POWER CONVERTERS VARAPRASAD ARIKATLA

Transcription

1 ADAPTIVE CONTROL METHODS FOR DC-DC SWITCHING POWER CONVERTERS by VARAPRASAD ARIKATLA JABER ABU QAHOUQ, COMMITTEE CHAIR TIM A. HASKEW YANG-KI HONG JEFF JACKSON DANIEL J. FONSECA A DISSERTATION Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the Graduate School of The University of Alabama TUSCALOOSA, ALABAMA 2011

2 Copyright VaraPrasad Arikatla 2011 ALL RIGHTS RESERVED

3 ABSTRACT Tight regulation of the output voltage is often required in many power supply applications, despite the highly dynamic nature of the loads. This is conventionally obtained by the design of high bandwidth feedback loop or recently by using adaptive control methods. The control loop is designed with specified safe bandwidth and gain and phase margins such that it maintains stable operation under variable conditions and parameters. However, this results in a compromise between achievable dynamic performance and robustness of control loop. The large variations in operating points and load makes the system design challenging. The tight regulation requirements, in addition to size and weight requirements, are getting stricter by time, which makes it necessary to investigate new control concepts in order to meet these requirements. Not meeting the tight regulation requirements may result in either the malfunctioning of the device (load) being powered or the destruction of that device. This work focuses on the development and implementation of adaptive control methods that result in the improvement of the dynamic performance of power converter, by utilizing the flexibility of digital controllers to realize advanced control schemes. Four different methods are proposed that improve the dynamic performance of converter without compromising the steadystate performance. A Sensorless Adaptive Voltage Positioning (SLAVP) control scheme is proposed in Chapter 2, in order to realize Adaptive Voltage Positioning (AVP) control without the need for load or inductor current sensing and high-resolution high-speed Analog-to-Digital Converter ii

4 (ADC) sampling. The SLAVP control law utilizes the readily available error signal of the conventional voltage-mode closed-loop compensated controller, or in other words the duty cycle of a DC-DC buck converter, in order to realize AVP control. The elimination of the need for high-speed and accurate sensing and sampling of currents using the proposed SLAVP control reduces the size and cost of the digital controller, reduces the power losses associated with current sensing and sampling, and simplifies hardware design, apart from improving dynamic performance. In Chapter 3, an Adaptive Digital PID (AD-PID) controller scheme is proposed. The controller adaptively adjusts the integral constant (K i ) and the proportional constant (K p ) of the compensator following a new control law. The control law is a function of the magnitude change in the error signal, and its peak value during dynamic transients. The proposed AD-PID controller adaptively detects the peak value of the error signal which is a function of the transient nature and magnitude and utilize it in the control law such that no ocillations are generated as a result of the adaptive operation. As a result, the dynamic output voltage deviation and the settling time of the output voltage are reduced. A novel Compensator Error Observe and Modulate method (CEO&M) for online closed-loopcompensator auto-tuning of digital power controller is proposed in Chapter 4. The proposed method is relatively simple, and does not require the knowledge and/or measurement of the power stage or closed-loop frequency response. Moreover, the proposed method does not depend on conventional design methods and the associated rule of thumb design criteria in order to tune closed-loop feedback controllers of power converter for high, and possibly optimum, dynamic performance. iii

5 Furthermore, two approaches for dynamic variable switching frequency digital control scheme under dynamic transients are proposed in Chapter 5 in order to improve the dynamic performance of the DC-DC switching power converter. The proposed controller varies the switching frequency of the converter, higher or lower than the steady-state frequency, during the transient as a function of peak and magnitude of error signal depending on the amount and type of the transient. Finally, Chapter 6 summarizes this work and provides conclusions before discussing future related research direction. iv

6 LIST OF ABBREVIATIONS AND SYMBOLS AC ADC AD-PID APWM ATerror Alternating Current Analog to Digital Converters Adaptive Digital PID Analog PWM Auto-Tuning controller Controller AVP C CCM CEO&M Adaptive Voltage Positioning Capacitor Continuous Conduction Mode Compensator Error Observe and Modulate C Limit on the number of counts of the counter limit D ds () Duty cycle or Duty ratio Laplace of duty cycle D Maximum duty cycle value 1mx D Minimum duty cycle value 2mn v

7 DC DCR Direct Current Output inductor equivalent DC resistance D Ideal duty cycle for a lossless DC-DC buck converter ideal DPWM DSP Digital Pulse Width Modulators Digital Signal Processor D ( I ) Additional duty cycle caused by resistive voltage drop v drop o DVSF ESL ESR Digital Variable Switching Frequency Equivalent series inductance of the output capacitors Equivalent Series Resistance of the output capacitors f Clock frequency clk f Frequency of DPWM DPWM f Maximum Frequency of DPWM DPWM max f Minimum frequency of DPWM DPWM min Fm () s PWM Modulator transfer function/gain FPGA Field Programmable Gate Array f Switching frequency sw f Ve comp Frequency of V e comp vi

8 Gcom () s Compensator transfer function Gdg () s Input voltage to duty cycle transfer function Gdi o () s Output current to duty cycle transfer function G Gain of DPWM DPWM G () PID z Transfer function of a digital parallel PID controller Gvd () s Duty cycle to output voltage transfer function Gvg () s Input voltage to output voltage transfer function H() s Output voltage sensor transfer function/gain HL Upper limit i c Current through C IC Integrated Circuits i o Output current I Maximum load current value o max I Minimum load current value o min I Current sensed signal sense K Gain of compensator K d Derivative gain constant vii

9 K d-steady Steady state value of K d KHz Kilo Hertz: Unit of Frequency K i Integral gain constant K i-steady Steady state value of K i K i-trans Transient value of K i K p Proportional gain constant K p-steady Steady state value of K p K p-trans Transient value of K p L LL mf nh NL P1 PID PWM RAM Inductor Lower limit Milli Farad: Unit of capacitance: Nano Henry: Unit for inductance Non-Linear Pole of compensator Proportional Integral Differential Pulse Width Modulation Random Access Memory R Equivalent resistance eq. viii

10 R Output capacitor ESR esr R o Load resistance R on MOSFET ON state resistance SLAVP Sensor Less Adaptive Voltage Positioning S L Low side switch SPC Switched power converters S U High side switch T A Time period of ramp signal Td () s SLAVP loop gain T Minimum time period of DPWM DPWM min T Maximum time period of DPWM DPWM max T Time period of DPWM at steady state DPWM steady Tv () s Voltage loop gain V Resolution of ADC ADC V c Compensated error signal v C Voltage drop due to C ix

11 V Value of compensated error signal ca V Compensated error signal e comp V Peak-to-peak value of the compensated error signal e pp v Error signal error V error (n) Value of error signal in nth switching cycle V error-peak Peak value of v error v Voltage drop due to ESL ESL v Voltage drop due to ESR ESR vg () s Laplace of input voltage VID Voltage Identification Code V Nominal input voltage in nom V in nom D 2mn Nominal input voltage of the power converter at which D 2mn value is measured v o Output voltage V Maximum allowed output voltage o max V Output voltage middle value o mid V Minimum allowed output voltage o min V Nominal output voltage o nom x

12 V o nom D 2mn Nominal output voltage of the power converter at which D 2mn value is measured V Desired nominal output voltage o VID V Peak voltage of ramp signal peaka VR Vref Voltage Regulators Reference Output Voltage V Voltage sensed signal sense V thr Threshold voltage Zo () s Output current to output voltage transfer function Zoc () s Output impedance transfer function x Absolute value of x I o Load current variation R eq. Change in R eq. t Delay in the response of the controller del t Transient time trans v Transient voltage drop due to ESL ESL v Transient voltage drop due to ESR ESR v Transient voltage deviation due to power stage output filter LC, xi

13 v o Transient output voltage drop V Desired AVP control voltage window o spec v Transient voltage due to closed loop control delay tdel c Cutoff frequency xii

14 ACKNOWLEDGEMENTS The author would first like to express his heartfelt gratitude to his advisor Dr. Jaber Abu Qahouq for his guidance, encouragement and support in conducting this research. Dr. Abu Qahouq s critical thinking and extensive vision has been the source of inspiration for the author throughout his work. The author is grateful to his committee members Dr. Tim A. Haskew, Dr. Jeff Jackson, Dr. Yang-Ki Hong and Dr. Daniel J. Fonseca for their valuable time and support. The author would also like to acknowledge the non-academic help of his friends, and his roommates Dr. Pankaj S. Kolhe and Nandhakumar Kathiresshan. Last but not least, the author is grateful to his family, whose love and support has enabled him to accomplish this work. xiii

15 CONTENTS ABSTRACT... ii LIST OF ABBREVIATIONS AND SYMBOLS...v ACKNOWLEDGEMENTS... xiii LIST OF TABLES... xvii LIST OF FIGURES... xviii 1. INTRODUCTION Overview Digital Control of Power Converters Main Motivations and Objectives of This Work Dissertation Outline SENSOR LESS ADAPTIVE VOLTAGE POSITIONING (SLAVP) CONTROL Introduction Sensorless Adaptive Voltage Positioning Control Basis SLAVP Control Law Derivation and Hardware Realization SLAVP Control Law with Fixed Input and Output Voltages SLAVP Control Law with Variable Input Voltage SLAVP Control Law with Variable Output Voltage Effects of Component DC Resistance Tolerance and Input Voltage Variation Analysis of DC Resistance Tolerance Effect on the SLAVP Window Analysis of Input Voltage Variation Effect on the SLAVP Window...28 xiv

16 2.5. Proof-Of-Concept Experimental Prototype Results Dynamic Modeling Results Summary ADAPTIVE DIGITAL PID (AD-PID) CONTROLLER Introduction Background for the Proposed AD-PID controller AD-PID Control Law and Algorithm AD-PID Control Law Design Guidelines Proof-Of-Concept Experimental Prototype Results Comparison Of AD-PID With Other Non-Linear PID Strategies Summary A NOVEL ADAPTIVE AUTO-DESIGN AND AUTO-TUNING METHOD FOR CLOSED-LOOP CONTROLLERS OF POWER CONVERTERS Introduction Bases of the Proposed Online Auto-Tuning Controller Online Auto-Tuning Digital Controller Algorithm and Architecture Proof-Of-Concept Experimental Prototype Results Experimental Verification of the Auto-Tuning Controller Bases Experimental Operation and Results of the Online Auto-Tuning Controller Summary AN ADAPTIVE DIGITAL VARIABLE FREQUENCY CONTROL SCHEME Introduction Digital Pulse Width Modulation Adaptive Switching Frequency Control Schemes...91 xv

17 DVSF I DVSF II Theoretical Analysis Experimental Prototype Results DVSF I DVSF II Summary CONCLUSIONS AND FUTURE WORK Summary of Conclusions Digital Sensor Less Adaptive Voltage Positioning Control Scheme An Adaptive Digital PID Controller for Power Converters A Novel Adaptive Auto-Design and Auto-Tuning Method for Closed-Loop Controllers of Power Converters An Adaptive Digital Variable Frequency Control Scheme Additional Comments on the Use of the Proposed Concepts Future Research Directions Application of Proposed Control Schemes for Multiphase Buck Converter Application of Auto-Tuning and Auto-Design Technique for Pole and Zero Variation Combined Utilization of Proposed Control Schemes Application of SLAVP Control Scheme for Multi-Sampled Implementation Optimization of the Digital Controller Realization and Implementation Application of Proposed Control Schemes for Other Topologies REFERENCES xvi

18 LIST OF TABLES 3.1. Values of variables used in the design example Comparison of improvement in overshoot using different DVSF control methods xvii

19 LIST OF FIGURES 1.1. Block diagram of a power converter with digital controller Illustration of DPWM functionality Buck converter with consideration of circuit component parasitic Illustration of output voltage overshoot during step-down load transient (a) DC-DC buck converter with one implementation type of conventional AVP control and (b) Conventional AVP control waveforms DC-DC buck converter duty cycle plots as a function of load current, input voltage, and output voltage to illustrate duty cycle linearity (a) for different input voltages and (b) for different output voltages (a) A theoretical plot for the output voltage vs. load current for a DC-DC buck power converter with AVP control and (b) a theoretical plot for the output voltage vs. D for a DC-DC buck power converter with AVP control Theoretical SLAVP control waveforms Digital System Block Diagram for SLAVP control Hardware Realization Digital System Block Diagram for SLAVP control Hardware Realization which accounts for both variable input voltage and variable output voltage (a) SLAVP controller with variable output voltage and (b) SLAVP with variable input and output voltages Experimental results to show the linear relationship (within the range of operation) of duty cycle as a function of the input and output voltages and load current for the experimental prototype (a) D as a function of input voltage at 1.5V output 2mn voltage and 10A load current, (b) D2mn as a function of output voltage at 9V input voltage and 10A load current and (c) D as a function of load current at 9V input voltage xviii

20 2.8. Experimental results of the prototype with SLAVP under dynamic load transients of 0A-10A-0A (full load range from minimum to maximum) with V 1.5V and SLAVP window of 50mV (a) at Vin 9V and (b) at Vin 10V Experimental results of the prototype with SLAVP under dynamic load transients of 0A-10A-0A (full load range from minimum to maximum) with V 9V and SLAVP window of 50mV (a) at Vo 1.7V and (b) at Vo 1.4V Experimental results of the prototype with SLAVP window of 50mv and under dynamic load transients of (a) 4A-7A-4A at Vo 1.5V and Vin 9V and (b) 0A- 8A-0A at Vo 1.3Vand V 8V...33 in Experimental results of the prototype with SLAVP window of 50mv and under 0A- 10A-0A dynamic load transients showing zoomed in view of output voltage and inductor current during (a) load step-up transient and (b) load step-down transient Small signal control block diagram with SLAVP Equivalent control block diagram to that shown in Figure Bode-plots for Tv () s and Td () s Output impedance plot DC-DC buck converter with digital controller A conventional digital PID controller realization diagram Example bode-plots for different values of (a) Kp and (b) Ki and (c) Kp and Ki A general Adaptive digital PID controller realization diagram Illustration of the AD-PID controller operation Flowchart for the proposed adaptive controller Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 7A-0A (a) with conventional PID controller and (b) with AD-PID controller Experimental results of the prototype with zoomed in view under dynamic load step-up transient of 0A-7A (a) with conventional PID controller and (b) with AD- PID controller...57 o in xix

21 3.9. Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 6A-2A (a) with conventional PID controller and (b) with AD-PID controller Experimental results of the prototype with zoomed in view under dynamic load step-up transient of 2A-6A (a) with conventional PID controller and (b) with AD- PID controller Experimental results of the prototype with zoomed in view under steady-state operation (a) with PID controller with K p-trans and K i-trans and (b) with PID controller with K p-steady and K i-steady A block diagram of a power converter system with closed loop control Bode-plots for (a) different gain (K) values and (b) different pole (P1) locations Simulation results of a DC-DC buck converter to demonstrate the basis of the proposed CEO&M control concept based on several K values (Note that V V ): (a) during steady-state and (b) during step-up load transient e conv. e comp 4.4. Simulation results of a DC-DC buck converter to demonstrate the basis of the CEO&M control concept (Note that Ve conv. V e comp ) based on several pole locations (one pole is moved): (a) during steady-state, (b) during step-up load transient and (c) during step-down load transient An illustration of the compensated error signal behavior under different bandwidth values with analog compensator An illustration of the compensated error signal behavior under different bandwidth values with digital compensator DC-DC buck converter with digital closed-loop compensator and ATerror Controller General main implementation flowchart of the ATerror controller Digital compensator used in the proof of concept experimental prototype Experimental results of a DC-DC buck converter to demonstrate the basis of the proposed CEO&M control concept when varying gain. (a) and (b): Lower gain ( K T ). (c) and (d): Medium gain ( K T ). (e) and (f): Higher (Unstable) gain ( K T 2.531). (a), (c) and (e): During Steady-State Operation. (b), (d) and (f): Under 8A-0A-8A Load Current Transient A flowchart for the detection of direction of gain change (increase/decrease)...79 xx

22 4.12. A flowchart for the detection of frequency change and setting of gain Illustration of the controller operation to determine the variable under auto-tuning (the gain here) required direction change and the detection of frequency change condition Experimental waveforms of the prototype with the ATerror controller. (a): The variation of gain until new optimized gain value is achieved.(b): Periodic tuning operation of the ATerror controller Dynamic response of the power converter during a load transient of 8A to 0A (a) before auto-tuning (b) after auto-tuning Block diagram of a Power Converter with Digital Controller Generation of duty cycle command signal with (a) analog controller (b) digital controller DPWM operation principle illustration with fixed switching frequency during (a) steady state (b) step-up load transient and (c) step-down load transient Illustration of operational principle of DPWM with variable switching frequency during (a) steady-state (b) step-up load transient which causes output voltage undershoot and (c) step-down load transient which causes output voltage overshoot Illustration of Dynamic Variable Switching Frequency (DVSF) Controller Operation Flowchart for the adaptive switching frequency controller Illustration of the adaptive switching frequency controller operation Dynamic Digital Variable Switching Frequency Controller Flowchart Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with variable frequency DPWM Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 0A-5A (a) with fixed frequency DPWM and (b) with variable frequency DPWM Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with adaptive frequency DPWM xxi

23 5.12. Experimental results of the prototype with zoomed in view under dynamic load step-up transient of 0A-5A (a) with fixed frequency DPWM and (b) with adaptive frequency DPWM Illustration of different adaptive concepts utilization xxii

24 CHAPTER 1 INTRODUCTION 1.1. Overview In the recent decade, the Switched Power Converters (SPC) have gained interest due to their high efficiency, small size and increased reliability, among others. The SPC is used to provide regulated power to many systems, including but are not limited to, microprocessors, FPGAs, DSPs, RAMs, communication systems, optical networks, consumer electronics, vehicle electronics, and wireless applications. The increased demand for providing tightly regulated voltages or currents to the loads has sparked interest in advanced control algorithms for SPCs [A1-A7]. For these loads, tight regulation of the output voltage is an important performance constraint [A1-A23] under dynamic conditions of operations. For a standard fixed-frequency, linear controller, tight regulation is conventionally achieved through the design of a high bandwidth feedback loop at the expected operating point of the converter. Though there are a wide range of load requirements, the most important dynamic output specifications that need to be satisfied by SPCs are: 1. Overshoot or undershoot. 2. Settling time. The most important causes of the transient conditions are: a. Load Step. 1

25 b. Reference Step. c. Input Voltage Step. Overshoot and undershoot are defined as the deviation of the output from its final value. Settling time is defined here as the time taken for the system transient to decay to within 1% of its final value. The transients may lead to high load temperatures (power losses), damage or reduced lifespan [A4-A13]. The goals of this dissertation are to investigate the stability issues related to the steady-state performance of converters, and to develop adaptive digital controllers that optimize the dynamic performance, in other words, to decrease the output voltage overshoot or undershoot and decrease its dynamic settling time Digital Control of Power Converters The digital control of power converters has gained popularity during recent years [A24-A29]. Figure 1.1 shows the block diagram of a power converter with digital controller enclosed with in the dashed box. Analog to Digital Converters (ADC) are used to sense and digitize the voltage and/or current and fed to the digital controller. These sensed voltage and/or current are utilized by the closed loop voltage/current compensator of the digital controller to generate the compensated error signal ( V e comp ).This is then compared with the digital pulse width Modulator (DPWM) to generate the required duty cycle (D) to maintain a regulated output voltage (in some power converter also a regulated current or power). This is illustrated in Figure 1.2. The sensed voltage and/or current may also be utilized to adaptively adjust parameters, including but are not limited to switching frequency, duty ratio/cycle, and number of phases of the power converter that result in improvement of efficiency and/or dynamic performances, among others [A4-A10, A34-A44]. 2

26 The considerations associated with the utilization of digital controllers for power converters are 1. The limited resolution of Analog to Digital Converters (ADC) and Digital Pulse Width Modulators (DPWM). 2. The size and power consumption of ADC(s). 3. The speed of ADC(s) and DPWM. 4. Power consumption incurred by the digital circuitry. Su i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Voltage/Current Compensator ADC ADC Other Functions and Adaptive Control ADC Figure. 1.1: Block diagram of a power converter with digital controller. 3

27 Digital Ramp V e comp D Figure. 1.2: Illustration of DPWM functionality. However, the following advantages associated with the digital implementation of controller compared with analog controllers, motivated the utilization of digital controllers for power converters: 1. The digital controllers ability to implement sophisticated algorithms for efficiency and dynamic performance improvement of power converters. 2. The flexibility of reconfiguration and scalability of the parameters of the control loop without the need for significant changes in hardware. 3. The potential reduction or elimination of controller component variation and sensitivity that effect the controller performance. 4. Decrease in the cost due to integration of multiple functionalities into a single digital chip. 5. Increased flexibility with improved protection, health monitoring and non-linear control techniques. 4

28 1.3. Main Motivations and Objectives of This Work Before discussing the motivation for the research work presented in this Dissertation, it is important to identify the dependence of the power converter voltage deviation from its steady state value under different operating conditions and different design parameters of the converter. The discussion is based on a non-isolated DC-DC buck topology and is applicable to many other types of topologies, especially those that are buck derived. Similar relationships could also be derived for other topologies that are boost derived for example. S u Ron i L L DCR Vin D Drivers Latches D1 S l C ESL + Vo Io Ron ESR D - PWM Modulator V e comp Closed Loop Voltage/ Current Compensator V sense I sense Figure. 1.3: Buck converter with consideration of circuit component parasitic. Figure. 1.3 shows a buck converter with some of the component non-idealities taken in to consideration. Ron is the MOSFET ON state resistance. DCRis the output inductor equivalent DC resistance. ESR is the equivalent series resistance of the output capacitors. ESLis the equivalent series inductance of the output capacitors. 5

29 V sense and I sense are the voltages and currents sensed signals for control and protection. Because of the ESR and ESL of the output capacitance, the output voltage is given by v ( t) v ( t) v ( t) v ( t) o ESR ESL C t dic () t 1 ic( t) ESR ESL ic( t) dt dt C (1.1) 0 Figure shows an illustration of output voltage deviation during step down load current transient [A31]. V LC, V o V tdel V ESR V ESL I 1 I o I 2 I o t delay t trans Figure. 1.4: Illustration of output voltage overshoot during step-down load transient. The deviation in the output voltage due to a step down or step up load transient is given by [A19, A31] v v v v v o ESR ESL tdel L, C I L I ESR ESL v I t C (1.2) o o tdel o trans 6

30 where I I I is the load current variation o 2 1 t trans is the transient time t del is the delay in the response of the controller and is proportional to the bandwidth of the closed loop (assuming no adaptive scheme is used to reduce this delay). V tdel is the voltage deviation associated with the delay in the response of the controller in the loop to the load transient. The transient voltage drop due to ESL is due to the inherent inductance of the capacitor and is given by V ESL I t o trans ESL (1.3) The transient voltage drop due to the inherent resistance of the capacitor is given by V I ESR ESR o (1.4) This voltage deviation is sufficiently large and cannot be ignored. This can be reduced by selection of capacitors with very low ESR value. The transient voltage deviation due to power stage output filter is given [A33] as follows V L, C I o L C (1.5) This can be reduced by selection of a large capacitor ( C ) or small inductor ( L ). However, space limitations and cost limit the maximum capacitor value and cannot be increased further. Also, the inductor cannot be reduced less than the value given by Eq. (1.6) which is the minimum inductor value for the operation of buck converter in Continuous Conduction Mode 7

31 (CCM). Moreover, reducing the inductor value will result in increasing the power conduction losses (lower efficiency). L crit Vo max( D,1 D) 2I f o s (1.6) The transient voltage due to closed loop control delay ( V tdel ) is caused by the closed loop control delay time which is the total delay time because of the controller bandwidth delay, and the control logic component delays until the time when the appropriate switch is turned ON or OFF. The time delay t delay is a function of the switching frequency, controller bandwidth, delay and controller and driver logic speed (assuming no adaptive scheme is used to reduce this delay). A larger closed loop bandwidth results in a smaller time delay. This reduces the voltage deviation. Thus, there is a motivation to increase the control loop performance without increasing the switching frequency so that there is an improvement in dynamic performance without decrease in efficiency, and without adding additional capacitors that increase the space and cost. This dissertation research work proposes adaptive control techniques that improve the dynamic performance of power converters without addition of extra capacitors (which would result in increased size), and without increasing the steady state switching frequency of the power converter (since increasing the steady-state switching frequency would reduce the efficiency). Though the methods presented in this dissertation research work are discussed for a DC-DC buck power converter, these methods can be expanded and applied to any switched power converter topologies. Each chapter in this dissertation includes introduction section that is related to the specific concept presented in that chapter. 8

32 1.4. Dissertation Outline Chapter 2 proposes a Sensorless Adaptive Voltage Positioning (SLAVP) control scheme in order to realize Adaptive Voltage Positioning (AVP) control without the need for load or inductor current sensing and high-resolution high-speed ADC. The proposed control scheme improves the dynamic performance of the converter with the elimination of the need for highspeed and accurate sensing and sampling of currents. The dynamic modeling of the proposed control scheme is also presented. Chapter 3 proposes an adaptive digital Proportional Integral Differential (PID) compensator in order to improve the dynamic performance of the converter. The control law is a function of the magnitude change in the error signal and its peak value during dynamic transients. The proposed AD-PID controller adaptively detects the peak value of the error signal which is a function of the transient nature and magnitude, and utilize it in the control law such that no ocillations are generated as a result of the adaptive operation. As a result, the dynamic output voltage deviation and the settling time of the output voltage are reduced. Chapter 4 proposes a novel Compensator Error Observe and Modulate method (CEO&M) for online closed-loop-compensator auto-tuning of digital power controller. The proposed method is relatively simple and does not require the knowledge and/or measurement of the power stage or closed-loop frequency response. Moreover, the proposed method does not depend on conventional design methods and the associated rule of thumb design criteria in order to tune closed-loop feedback controllers of power converter for high, and possibly optimum, dynamic performance. 9

33 Chapter 5 proposes two dynamic variable frequency control schemes that vary the frequency of power converter as a function of the error signal. The proposed controller varies the switching frequency of the converter, higher or lower than the steady-state frequency, during the transient as a function of peak and magnitude of error signal depending on the amount and type of the transient. The experimental results show the improvement in the dynamic performance of the power converter. A summary of the conclusions of this work and the directions of future related research work are given in Chapter 6. 10

34 CHAPTER 2 SENSOR LESS ADAPTIVE VOLTAGE POSITIONING (SLAVP) CONTROL 2.1. Introduction Adaptive Voltage Positioning (AVP) control has been used in DC-DC power converter applications, especially in those converters powering high speed Integrated Circuits (ICs) such as microprocessors, in order to achieve smaller dynamic output voltage deviation while at the same time using less output filter capacitance for the power converter [B1, B2, B6-B10,B48]. The use of AVP control has been motivated by the increased dynamic current slew rate and/or magnitude of newly coming ICs and microprocessors, while at the same time requiring lower (down to less than 1V) output voltage from the power converter with tighter output voltage regulation [B3-B5, B41]. While the AVP control basic concept is relatively simple, its modeling and design for optimal performance in order to achieve the maximum benefit is relatively complex [B6-B11]. Moreover, there are several proposed schemes presented in the literature to implement AVP control along with their associated modeling and design guidelines [B6-B19]. The conventional AVP control schemes are based on sensing the load current value or the buck converter s inductor current value [B14-B19]. Figure. 2.1(a) shows an example of a conventional AVP control realization assuming a closed loop digital controller implementation. As illustrated in Figure. 2.1(b), the AVP control slightly adjust the output voltage of the power converter based on the load current such that the output voltage is slightly higher when the load 11

35 current is lower and is slightly lower when the load current is higher. The AVP control sets the output voltage to the maximum allowed output voltage ( V o max ) when the load current is at its minimum value ( I o min ), it sets the output voltage to the minimum allowed output voltage ( V o min ) when the load current is at its maximum value ( I o max ), and it sets the output voltage to its middle value ( V o mid ) when the load current is at its middle point value ( I max I min 2 ) [B10]. This provides a larger allowable margin for the output voltage to overshoot when a load current step-down occurs, and provides a larger allowable window for the output voltage to undershoot when a load current step-up occurs. Based on this behavior, even if the AVP control design is not optimal, as long as the dynamic response of the output voltage is free of oscillations, using the AVP control is advantageous, and will lead to reduced dynamic output voltage deviation. o o Nowadays, the AVP control is being used for special high end applications, mainly for buck power converters that are used to power microprocessors, where the cost and design complexity is tolerable. However, AVP control use is potentially advantageous to any power converter application. Therefore, it is desired to obtain a lower cost and simpler realization that can be used for wider range of applications. The use of digital controllers, as an alternative to analog controllers, for power converter applications have increased in the last few years because of several potential advantages. These advantages include the digital controllers ability, and easiness to implement sophisticated algorithms, and laws to improve dynamic and efficiency performances of power converters, they are easier to be reconfigured and scaled compared to their analog counterpart, and they can potentially reduce or eliminate the controller component variations and sensitivity that affect the 12

36 controller performance [B20-B37, B42-B45]. However, there are several challenges associated with using digital controllers in power converters, to mention a few, the resolution limitation of digital controllers and the size, cost and power consumption incurred from the required highspeed high-resolution Analog-to-Digital Converters (ADCs) and Digital Pulse Width Modulators (DPWMs). The technological advancement in digital circuit design and process features and performance along with newly proposed digital control schemes is resulting in alleviating such challenges with time. As it can be observed from Figure. 2.1(a), AVP control realization as a part of a fully digital controller implementation for a power converter requires a high-resolution and high-speed ADC for the load or inductor current sampling. The performance of the current ADC will affect the AVP control performance, and hence, it will affect the dynamic output voltage deviation. Several sensorless control schemes have been discussed in the literature over the years such as those in [B25, B33, B38-B40, B46, B47], among others. However, none of these is for AVP control. In this chapter, a sensorless AVP (SLAVP) control scheme is presented. The SLAVP control eliminates the need for load current sensing and the associated high-speed high resolution ADC in digital controller implementation. It also does not require any additional voltage and/or current sensing or ADC. The presented SLAVP control requires minor addition to an existing basic digital controller with voltage-mode closed-loop control. Moreover, the low cost realization of the presented SLAVP control makes it more possible to utilize the SLAVP in a wider range of power converter applications with lower cost and simpler design. 13

37 S u i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Compensator ADC1 + - Gain/ Compensation ADC 2 Vref Digital Controller with Conventional AVP (Example of a Conventional Method) (a) I o max Output Current I o min V o m id Output Voltage Without AVP V o max V o m id V o min Output Voltage With AVP (b) Figure. 2.1: (a) DC-DC buck converter with one implementation type of conventional AVP control and (b) Conventional AVP control waveforms. Section 2.2 introduces the basis of the SLAVP control. Section presents the basic SLAVP control law derivation and hardware realization. Section and Section present the control laws of the SLAVP under variable input and output voltages of the power converter. 14

38 The effect and analysis of components DC resistance tolerances and input voltage change on the SLAVP control are discussed in Section 2.4. A proof-of-concept experimental prototype results are presented in Section 2.5, and dynamic modeling analysis is discussed in Section 2.6. The summary is given in Section Sensorless Adaptive Voltage Positioning Control Basis The controller duty cycle D, or equivalently the compensator s output error signal V e comp function of the power converter s load current. For a DC-DC buck converter, the duty cycle of the controller increases as the load current increases because of the additional voltage drop between the input and the output at higher load current, and in order to deliver the necessary energy for a regulated output voltage. This behavior can be approximated by the following equation assuming that the power converter has an equivalent resistance, R eq., between the input and the output:, is a Vo Io Req. V I o o Req. D Dideal Dv drop ( Io) V V V in in in (2.1) Where V is the input voltage of a DC-DC buck converter, R eq. is the equivalent resistance in between the ideal input voltage source and the output voltage at the output capacitor, D ideal is the ideal duty cycle for a lossless DC-DC buck converter and D ( I ) is the additional duty cycle v drop caused by resistive voltage drop which is a function of the output current. o 15

39 (a) (b) Figure. 2.2: DC-DC buck converter duty cycle plots as a function of load current, input voltage, and output voltage to illustrate duty cycle linearity (a) for different input voltages and (b) for different output voltages. Figure. 2.2 shows plots of Eq. (2.1) for an example design with Req. 30m. The plots shows the duty cycle as a function of the load current, input voltage and output voltage variables. It can be observed that the duty cycle is linear as a function of the three variables. Figure. 2.3(a) shows a theoretical plot for the output voltage vs. load current for a power converter with AVP control, which agrees with what is described in the previous section and Figure Figure. 2.3(b) shows a theoretical plot for the output voltage vs. D for a power converter with AVP control which 16

40 agrees with the above description of the relation between the load current and D It can be observed that a sensorless AVP (SLAVP) control can potentially be realized if the appropriate SLAVP control law as a function of D (or V e comp expected to have the theoretical waveforms as shown in Figure ) is derived. Such SLAVP control law is V o V o max V o min I o min I o max I or I o L (a) V o V o max V o min D1mx D2mn D V e comp (b) Figure. 2.3: (a) A theoretical plot for the output voltage vs. load current for a DC-DC buck power converter with AVP control and (b) a theoretical plot for the output voltage vs. D for a DC-DC buck power converter with AVP control. 17

41 I o max Output Current I o min D 2mn D 1mx Duty Cycle Or Compensator Error Signal V o max V o m id V o min Output Voltage With SLAVP Figure. 2.4: Theoretical SLAVP control waveforms SLAVP Control Law Derivation and Hardware Realization This section shows the SLAVP control law under different input and output voltage conditions SLAVP Control Law with Fixed Input and Output Voltages It can be shown that based on Figure. 2.3(b), the following basic SLAVP control law can be obtained: V V V ( D) ( D D ) V o min o max o SLAVP 1 1mx o max D2mn D1mx D V o spec D 2mn 1mx ( D D ) V ( D D ) V 1mx o max 1mx o max (2.2) V V Vo spec D D D D, Vo min Vo nom V o max and D1mx D 2 o min o max Where 2mn 1mx 2mn 1mx mn V o max and o min V values are known based on given specifications and requirements for a design. They are given by: 18

42 Vo max V V o min o spec Vo max Vo nom V o nom (2.3) 2 2 Vo max V V o min o spec Vo min Vo nom V o nom (2.4) 2 2 Where V o spec is the desired AVP control voltage window centered around V o nom based on design specifications. The relationship between Eq. (2.2) and the load current is as explained earlier in Figure. 2.3 and Figure All the parameters in Eq. (2.2) are known constants for a given design except D which is an available variable in any conventional controller of a power converter. D value varies as a function of the load current. As apparent from Figure. 2.3 and Figure. 2.4, D 2mn can be obtained by setting the operating point of the power converter at I o max and V o min and D 1mx can be obtained by setting the operating point of the power converter at I o min and V o-max. As the load current varies from I o min (which is usually zero amperes) to I o max, the duty cycle D varies from D 1mx to D 2mn. This will cause the result of Eq. (2.2) to vary from V o min to V o max, resulting in SLAVP control realization. 19

43 S u i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Compensator ADC SLAVP Controller Vref Digital Controller with SLAVP Figure. 2.5: Digital System Block Diagram for SLAVP control Hardware Realization. Figure. 2.5 shows the block diagram of the SLAVP hardware realization by using a digital controller. The SLAVP control loop simply adjusts the closed loop voltage reference based on Eq. (2.2) and as a function of V e comp which is used to generate the DPWM duty cycle D. It can also be observed that the current sensing and sampling and high-resolution high-speed ADC is eliminated, resulting in less hardware requirements and hence lower size and cost. The SLAVP controller in Figure. 2.5 involves Eq. (2.2) and it also involves setting limits on Eq. (2.2) results. If for some reason the result of Eq. (2.2) is larger than V o max, the controller will limit the value of the voltage reference ( V ref equal to V o max ) that is provided to the voltage mode compensator to a value that is. Similarly, if for some reason the result of Eq. (2.2) is smaller than V o min, the controller will limit V ref to a value that is equal to V o min. Therefore, V ref will always satisfy V V V. o min ref o max SLAVP Control Law with Variable Input Voltage There are two types of power converters in terms of input voltage. The first type is constant input voltage power converters and the second type is variable input voltage (either with narrow 20

44 range or wide range) power converters. A given system, such as a computing platform system, for example and not for limitation, may include both types. The SLAVP control law that is presented in the previous section, namely Eq. (2.2), is apparently suitable for power converters with fixed input voltage. This limits the application of Eq. (2.2) to converters with fixed input voltage. If the input voltage is varied within significant range, the output voltage will be limited by the SLAVP controller to V o max or V o min. If the input voltage is slightly varied, the SLAVP controller with Eq. (2.2) may still work to a certain degree (see Section 2.4.2) but it will not perform as expected. The input voltage change impacts Eq. (2.2) mainly because for different input voltage values, there are different sets of D 1mx and D 2mn values. For a DC-DC buck converter, the duty cycle is a linear function of the input voltage as discussed in Section 2.2. For practical converters with variable input voltage, including those with conventional AVP control, the input voltage is sensed and sampled by an ADC that is relatively slower than the one used to sample the output voltage when digital controller is used. Such sensing is usually needed for reasons such as protection and/or feed forward control. If D 1mx and D 2mn are obtained at the nominal input voltagev in nom, then the new values of D 1mx and D 2mn at any input voltage value can be obtained as follows: V D ( V ) D ( V ) in nom 1mx in 1mx in nom Vin V D ( V ) D ( V ) in nom 2mn in 2mn in nom Vin Therefore, the SLAVP equation for any input voltage value becomes: 21

45 Vo SLAVP 2 ( D ) Vo min Vo max Vin nom ( D D ) V V V D D V in nom in nom in 2mn 1mx Vin Vin 1mx o max Vo D min V o max D 2mn 1mx ( D D ) V 1mx o max ( D D ) V 1mx o max ( D D ) V 1mx o max V V V V ( D D ) V o min o max in nom in 1mx o max Vin nom ( D2mn D1mx ) Vin Vin D Vin nom D1 mx Vo max V o SLAVP 2 ( D) Vin D V o max (2.5) Where Vin nom V in, V in nom is the nominal input voltage of the power converter at which D 1mx and D 2mn values are measured, V in is the actual input voltage of the power converter, Vo min V V o max o spec V V,, and Vin nom D 1mx. V ( D D ) V ( D D ) 1 in in nom in nom 2mn 1mx in nom 2mn 1mx The SLAVP control law of Eq. (2.5) with the input voltage consideration is relatively simple since, and V o max are constants for a given design even under variable input voltage and variable load current. Eq. (2.5) becomes equal to Eq. (2.2) when the input voltage is constant and satisfies Vin V in nom. 22

46 SLAVP Control Law with Variable Output Voltage Some applications such as Voltage Regulators (VRs) for powering microprocessors have adjustable output voltage for example via the Voltage Identification Code (VID). In such applications, the output voltage varies within a given range. If D 1mx and D 2mn are obtained at the nominal output voltage V o nom and at the nominal input voltage V in nom, then the new values of D 1mx and D 2mn at any output voltage and input voltage values can be obtained as follows: V V D ( V, V ) D ( V, V ) o in nom 1mx in o 1mx in nom o nom Vin Vo nom V V D ( V, V ) D ( V, V ) o in nom 2mn in o 2mn in nom o nom Vin Vo nom Therefore, the SLAVP equation for any output voltage and input voltage values becomes: V o spec in nom D o SLAVP 3 1mx o max V Vin nom D V Vin V o o nom D 2mn in nom D1mx 1mx D2mn D1mx Vin Vo nom D Vo nom D o 1mx V ( D) ( D D ) V 2mn 1mx V V V V in o spec V V o in nom D1 mx ( D D ) V V V V V V o in nom D2mn in nom D in o nom D 1mx D2mn D1mx Vo nom D Vo nom D 2mn 1mx 1mx 1mx o max Vin in nom D D 1mx D V V o V V o nom D 1mx 1mx o max Vin D V o Vo max 23

47 Vin D V o VID Vo V o spec 2 Vo SLAVP 3 ( D ) Vin V o D (2.6) Where V V in nom D o nom D D V o spec V in nom D 2mn D1mx Vo nom D 2mn 1mx 2mn 1mx V in nom D 1mx, V o nom D 1mx D 1mx, Vo spec V o VID, 2 V o nom D 1mx and V in nom D 1mx are the nominal output voltage and nominal input voltage of the power converter at which D 1mx value is measured, V o nom D 2mn and V in nom D 2mn are the nominal output voltage and nominal input voltage of the power converter at which D 2mn value is measured, and V o VID is the desired nominal output voltage. The SLAVP control law of Eq. (2.6) with the input voltage and output voltage consideration is relatively simple since and are constants for a given design even under variable output voltage, variable input voltage and variable load current. is just the value of the output voltage ( V o V o VID ) plus half the value of the allowed SLAVP window ( V o spec ). Eq. (2.6) becomes equal to Eq. (2.2) when the input voltage is constant and satisfies Vin V in nom and when the output voltage is constant and satisfies Vo V o nom. Consider an example power converter design with output voltage range 1.3V - 1.8V and input voltage 8V 10V. Then V o nom can be selected to be equal to 1.5V and V in nom can be selected to be equal to 9V. At these values, D 1mx and D 2mn values can be determined and also with the 24

48 knowledge of V o spec, and values can be obtained. Eq. (2.6) can be used and will be valid when the input voltage and output voltage values are not at their nominal values. This is because the equation is scaled (adapted) as a function of the input and output voltages. S u i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Compensator ADC SLAVP Controller Vref V o-vid Digital Controller with SLAVP (a) S u i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Compensator ADC ADC SLAVP Controller Vref V o-vid Digital Controller with SLAVP (b) Figure. 2.6: Digital System Block Diagram for SLAVP control Hardware Realization which accounts for both variable input voltage and variable output voltage (a) SLAVP controller with variable output voltage and (b) SLAVP with variable input and output voltages. 25

49 Based on SLAVP Eq. (2.6), which accounts for both variable input voltage and variable output voltage, Figure. 2.5 block diagram is adjusted as shown in Figure Effects of Component DC Resistance Tolerance and Input Voltage Variation Analysis of DC Resistance Tolerance Effect on the SLAVP Window: Power stage components DC resistances values have tolerances. These tolerances may affect the performance of the AVP control loop. As mentioned earlier, the digital controller with the proposed SLAVP controller clips and limits the output voltage to a window between V and o max V even if the SLAVP control law equation resulted in a voltage outside this window, which o min may result because of components resistive tolerances. While the voltage is not allowed to go outside this limited window under such condition, the AVP control loop performance may be degraded. The performance degradation is because the output voltage may not be exactly at the desired value, within the AVP window, for given load current values. It should be noted here that the same issue also exists in conventional current sensing based AVP controllers. For example, the tolerances in the DC resistance (DCR) of the inductor may affect the accuracy of the sensed current and as a result may affect the AVP control accuracy and degrade its performance. Other sources that may affect the current sensing accuracy (in conventional current sensing based AVP controllers) is the current processing circuits (current amplifiers) accuracy and mismatches and noise. Calibration and using components with lower tolerances are usually the way to reduce this possible performance degradation. 26

50 In the SLAVP control, a change in R eq. ( R eq. ) will cause a change in the duty cycle with an amount of: D I o ( R ) in eq. V (2.7) By using Eq. (2.7) and Eq. (2.6), it can be shown that the error in the SLAVP window as a result of R is given by: eq. SLAVP error ( R ) eq. I o ( R ) o eq. V (2.8) Eq. (2.8) indicates that the maximum error because of a R eq. will occur at the maximum load current when the output voltage is near to V and the error decreases to zero as the load o min current decreases to zero and the output voltage approaches V. o max For example, for a DC-DC buck power converter with V 1.5V, SLAVP window of 50mV and 10% tolerance in R eq. of 30m, the maximum error at maximum load of 10A is about o 2.4mV. Note that in this calculation 0.11 is used from the experimental section design (see Section 2.5) as an example. Given the fact that in SLAVP control, the current sensing and high-speed high-accuracy analog to digital sampling is eliminated in a fully digital controller implementation, the SLAVP control performance is acceptable even under large tolerance values. Moreover, the error caused by these tolerances can be estimated based on Eq. (2.8) and can be accounted for in the design with a design safety margin in the AVP window. 27

51 Analysis of Input Voltage Variation Effect on the SLAVP Window: As mentioned earlier, especially for power converter applications with wide input voltage variation range, the input voltage is usually sensed for functions such as feed forward control in order to maintain optimized dynamic performance at different input voltage values. The second and third forms of the SLAVP law, Eq. (2.5) and Eq. (2.6), can take care of the input voltage variation effect on the SLAVP window based on input voltage sensing. However, if the input voltage variation range is narrow, the SLAVP controller could be used without the need for sensing the input voltage if some error in the SLAVP window is acceptable especially if the input voltage range is narrow. It can be shown that the error in the SLAVP window as a result of input voltage variation from its nominal value is given by: SLAVP error ( V ) in ( V V ) ( V I R ) in nom in o o eq. ( V ) ( V ) in nom in (2.9) For example, in the design given in the experimental section of this chapter (Section 2.5), the error in the SLAVP window as a result of input voltage change to 9.5V from its nominal value of 9V while using Eq. (2.2) in the controller (which does not account for input voltage variation) is approximately 6mV (assuming R eq. of 30m as an example). Eq. (2.9) has been verified experimentally Proof-Of-Concept Experimental Prototype Results A proof of concept prototype is built in the laboratory for verification and test of the SLAVP control concept. The power stage is a single-phase DC-DC buck converter with the following design specifications: Input voltage range of 8V-10V and nominal output voltage of 1.5V, output 28

52 inductor of 440nH, output capacitance of 3mF, switching frequency of 350KHz and full load current of 10A. Fully digital control hardware is used to implement the voltage mode feedback controller with SLAVP control. The ADC has 7-bit resolution and takes 2.8M sample/second. The DPWM used is with 10-bit resolution. The controller is implemented using Altera FPGA Altera Cyclone II EP2C35F672C6. The voltage mode controller is with a PID (Proportional-Integral-Derivative) digital compensator and the SLAVP control is realized as described earlier in this chapter. The desired SLAVP window is 50mV. Based on this, the following values are obtained: D 1mx 0.168, D , 0.11, 0.991,and V o VID mn In order to verify the linear relationship of the duty cycle as a function of the input voltage and output voltage for the prototype, D2mn values are measured for input voltage range of 8V- 10V and output voltage range of 1.3V-1.8V. The results are plotted as shown in Figure. 2.7(a) and Figure. 2.7(b), respectively. Note that there is only one D2mn value and one D 1mx value used in the digital controller and Eq. (2.6) will scale automatically for different input and output voltages, however, Figure. 2.7 is shown here in order to verify the bases used to obtain Eq. (2.6). Moreover, Figure. 2.7(c) shows a plot of the duty cycle as a function of the load current. As expected, the relationship between the duty cycle and the load current is linear. 29

53 (a) (b) (c) Figure. 2.7: Experimental results to show the linear relationship (within the range of operation) of duty cycle as a function of the input and output voltages and load current for the experimental prototype (a) (b) D 2mn as a function of input voltage at 1.5V output voltage and 10A load current, D 2mn as a function of output voltage at 9V input voltage and 10A load current and (c) D as a function of load current at 9V input voltage. Figure. 2.8 through Figure show experimental results of the prototype under dynamic load transients for different input and output voltages for the controller with SLAVP. Figure. 2.8(a) shows the experimental results under the nominal input voltage and output voltage values (9V, 1.5V) and under dynamic load transients from zero load to full load. 30

54 Figure. 2.8(b) shows the experimental results when the input voltage is increased to 10V. It can be observed that the SLAVP controller performs as expected with 50mV SLAVP window. 50mV 10A (a) 50mV 10A (b) Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current (3A/div., 2ms/div.). Figure. 2.8: Experimental results of the prototype with SLAVP under dynamic load transients of 0A-10A-0A (full load range from minimum to maximum) with V 1.5V and SLAVP window of 50mV (a) at Vin 9V and (b) atvin 10V. o 31

55 50mV 10A (a) 50mV 10A (b) Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current (3A/div., 2ms/div.). Figure. 2.9: Experimental results of the prototype with SLAVP under dynamic load transients of 0A-10A-0A (full load range from minimum to maximum) with V 9V and SLAVP window of 50mV (a) at Vo 1.7V and (b) atvo 1.4V. in Figure. 2.9 shows the experimental results when the output voltage is varied from 1.5V to 1.7V and 1.4V. The results show that the SLAVP controller is able to perform as expected under different output voltage values. 32

56 Figure shows the results when the load transient is not from zero load (0A) to full load (10A), but when it is from 4A-7A-4A and 0A-8A-0A for a given input voltage and output voltage values. The results show that the SLAVP controller is able to perform as expected under different input voltage values. 15mV 3A (a) 40mV 8A (b) Top Trace: Output Voltage (50mV/div, 2ms/div., AC coupled) and Bottom Trace: Load Current (3A/div., 2ms/div.). Figure. 2.10: Experimental results of the prototype with SLAVP window of 50mv and under dynamic load transients of (a) 4A-7A-4A at Vo 1.5V and Vin 9V and (b) 0A-8A-0A at V 1.3V andv 8V. o in 33

57 50mV 10A (a) 50mV 10A (b) Top Trace: Output Voltage (50mV/div, 20µs/div., AC coupled) and Bottom Trace: Inductor Current (3A/div., 20µs /div.). Figure. 2.11: Experimental results of the prototype with SLAVP window of 50mv and under 0A- 10A-0A dynamic load transients showing zoomed in view of output voltage and inductor current during (a) load step-up transient and (b) load step-down transient. Figure shows a time-scale zoomed in view (with 20µs/div. time scale) during load stepup and load step-down transients. The figure shows the results for the output voltage and inductor current. It can be observed that for the design of this chapter, the output voltage reaches 34

58 the new output voltage value in about 10µs to 20µs (less than 7 switching cycles). Different designs, for example a design with smaller inductor value and/or higher switching frequency, may result in a faster speed. The results indicate that the performance of the SLAVP controller are comparable to those presented in [B6] and [B7] for the conventional AVP control. This can be achieved with appropriate control loops design. It can be observed from the experimental results that the SLAVP controlled output voltage scales within the SLAVP window according to the load current value without the need to sense the load or inductor current. It may be necessary to mention that Figure. 2.8 through Figure show only the AC component and not the DC component of the output voltage waveforms as indicated on the figures in order to make the SLAVP window clear and any change in it visible. This is because the SLAVP window represented by the AC component is much smaller (50mV) than the DC component (1.3V 1.7V) Dynamic Modeling Results This section presents dynamic modeling work results for power converter with SLAVP control. Figure shows the small signal control block diagram with SLAVP control. An equivalent small signal control block diagram with SLAVP control to that of Figure is shown in Figure In order to obtain and simplify the two equivalent block diagrams, the concept presented in [B7] is utilized. It can be observed from the block diagrams how the duty cycle is fed back to the input of the compensator and used as the reference for the voltage loop, forming the SLAVP control loop. This loop replaces the current loop in conventional AVP control. 35

59 i o Z 0 v g =v in d G vg G vd H v o F m v c G com G dio β G dg Figure. 2.12: Small signal control block diagram with SLAVP. i o Z 0 v g =v in d G vg G vd T v H v o F m v c T d G com G dio β 1+Gcom -1 G dg Figure. 2.13: Equivalent control block diagram to that shown in Figure The transfer functions used in the small signal model are as shown below. - Output current to output voltage transfer function: s s (1 ).(1 ) v () s Zo() s R i s s s o L esr eq. 2 o() 1 2 Q o o - Input voltage to output voltage transfer function: 36

60 s (1 ) vo () s esr Gvg () s D vg () s s s 1 Q 2 2 o o - Duty cycle to output voltage transfer function: s (1 ) vo () s esr Gvd () s Vg ds () s s 1 Q 2 2 o o - Output current to duty cycle transfer function: G di o () s ds () R i () s V o o g s (1 ) esr s (1 ) R - Input voltage to duty cycle transfer function: G dg () s ds () D Ro Co s vg() s Vg (1 s ) R - Compensator transfer function: Gcom () s. - PWM Modulator transfer function/gain: Fm () s. - Output voltage sensor transfer function/gain: H() s. 37

61 Ro Where o 2 L C ( R R ) o o o esr f o, R 1 R. C o o 2 f R, esr R esr 1 C o 2 f esr, L R eq. L o 2 f L, and Q 1. Lo ( R C ) R o esr o o Resr is the output capacitor ESR and Ro Vo I o is the load resistance. From Figure. 2.13, the voltage loop gain and the SLAVP loop gain can be obtained as: Tv ( s) Fm ( s) Gvd ( s) H( s) Gcom ( s ) Td ( s) Fm ( s) 1 Gcom ( s ) The output impedance transfer function is given by: Z oc () s Z ( s) (1 T ( s)) F ( s) G ( s) G ( s) H ( s) 1 G ( s) o d m di vd com o 1 Td( s) Tv( s ) (2.10) In order to achieve a constant impedance design with 50mV window and 10A load range, it is desired to achieve Zoc( s) 50mV 10A 5m. All the other terms in Eq. (2.10) are known since they can be calculated from the power stage and controller parameters. Therefore, it is desired to design a compensator Gcom () s that will result in Zoc( s) 5m. Note that value is based on Eq. (2.6). The design of this compensator is relatively simple. A single-zero two-pole compensator is sufficient. The zero is placed at the resonant frequency f o and one of the two poles is placed at zero frequency (integrator) or at low frequency in order to boost the low frequency gain. The second pole is placed at frequency that is much higher than f esr. The location of the second pole 38

62 is flexible and can be used together with the compensator gain to control the bandwidth and phase margin. For the design example presented in Section 2.5, f 354Hz and with R 5m, f 10.61kHz. Therefore, the compensator zero can be placed at 354Hz and the esr esr non-zero pole can be placed at 55.7kHz. T () s crossover frequency should be placed close to the crossover frequency of Tv () s or higher. d o 0 20 log Tv i n 20 log Td i n Tv (s) Td (s) Phase of Tv (s) Phase of Td (s) Figure. 2.14: Bode-plots for Tv () s and Td () s. Figure shows the bode-plots for Tv () s and Td () 39 2 n arg Tv i deg arg Td i deg n n arg Zoc i deg s and Figure shows the output impedance plot. It can be observed that a constant impedance design is achieved. The crossover frequencies of Tv () s and Td () s are about 90kHz with phase margin of 30º, and 200kHz with phase margin of 100º, respectively. Note that the 200kHz crossover frequency of T () s for the SLAVP control loop is comparable to (about the same) the crossover frequency of the AVP current loop in [B7] for the 300kHz switching frequency design (see Figure. 19(b) in [B7]). d n Angle of

63 Zoc i n Zoc (s) Angle of Zoc (s) arg Zoc i deg n n 2 Figure. 2.15: Output impedance plot 2.7. Summary The chapter presents a method to realize adaptive voltage positioning control for power converters with no need for current sensing, namely, the SLAVP control. Moreover, the presented SLAVP control eliminates the need for high-speed and accurate current sensing and eliminates the need for high-resolution high-speed ADC in a digital controller implementation, and therefore, it reduces the associated size and cost and it reduces sensing and sampling power losses. Moreover, the presented SLAVP control simplifies the design and implementation of AVP control and therefore it can be used for wide range of applications and not only for highend applications like powering microprocessors. In addition, SLAVP control can be easily added to controllers with conventional voltage mode closed loop control without significant hardware requirements and cost increase unlike conventional AVP controllers. The SLAVP control laws (equations) are derived for several power converter design cases. These are power converters with fixed input and output voltages, power converters with a range of variable input voltage and fixed output voltage, and power converters that have a range of 40

64 variable input voltage and output voltage. The SLAVP control law and controller adjust the output voltage of the power converter within a specified range based on the readily available controller s duty cycle or compensated error signal/voltage. This is possible because the duty cycle of a switching power converter is a function of load current. The SLAVP control theoretical analysis and design are presented in this chapter and experimentally verified by preliminary proof-of-concept prototype experimental results that strongly agree with the theoretical analysis. Future work includes implementation to high-current multiphase power converters and other power converter topologies and more thorough dynamic modeling and analysis. 41

65 CHAPTER 3 ADAPTIVE DIGITAL PID (AD-PID) CONTROLLER 3.1. Introduction Digital power control has made the implementation of many sophisticated control strategies easier and possible, which can result in significant improvement in the dynamic performance and efficiency of power converters [C1-C6, C27]. Digital power control offers the flexibility of adjusting the parameters of the control loop without the need for significant changes in the hardware. Moreover, the digital controller s components aging effects are negligible compared with analog controllers. The aforementioned advantages, among others, have made digital power controller a strong competitor to analog controllers in many power converter applications [C7- C12]. The dynamic performance of power converters is critical in many applications. Modern Digital Signal Processors (DSPs) including microprocessors operate with low supply voltages. During the transients, the voltage deviation should be minimized for proper and safe operation. This requires a very well designed closed loop controller which can respond quickly to the dynamic transients and limit the overshoot/undershoot [C13-C17]. Figure. 3.1 shows a block diagram of a power converter with a digital controller. Figure. 3.2 shows the block diagram of a conventional Proportional-Integral-Derivative (PID) controller [C18-C25]. The conventional PID controller parameters are usually designed using either the 42

66 bode-plot based methods or root-locus diagram based methods [C26]. Usually, a PID controller is designed for particular power stage parameters [C27]. The PID controller is designed with a specific safe bandwidth and gain and phase margins such that it maintains stable operation under varying conditions and parameters such as load current, input voltage and components parasitic variations. Such a safe design may affect and limits the dynamic performance of the system. Vin Su D Drivers Latches D1 i L S l Lo Co + Vo Io D - DPWM Modulator Compensator v error ADC V e comp Vref Figure. 3.1: DC-DC buck converter with digital controller. The values of K p and K i (in addition to K d, the derivative constant) in the PID controller of Figure. 3.2 determine the bandwidth, phase margin and gain margin of the power converter closed loop system and hence the stability. In general, as K p and K i increase, the gain and bandwidth of the system increase. Increasing the gain and bandwidth of the system above certain values may cause instability during steady state operation and dynamic operation [C23]. However, during the dynamic transient time period, the allowable bandwidth can be increased in order to achieve improved dynamic response [C23]. 43

67 Vout ADC v error K p Vref K i -1 Z -1 Z To DPWM V ( ) e comp z K d Figure. 3.2: A conventional digital PID controller realization diagram. Adjusting the compensator design or constants during transients may cause additional output voltage ringing and overshoots/undershoots if not carefully implemented and if appropriate adaptive strategy is not used. Moreover, the amount of improvement is based on the strategy used in the adaptive PID scheme Background for The Proposed AD-PID Controller The transfer function of a digital parallel PID controller as shown in Figure. 3.2 is as follows: K G z K K z 1 z i 1 PID ( ) p (1 ) 1 d (3.1) The values of K p, K i and K d determine the controller design, performance and stability. A large proportional gain (K p ) results in a large change in the output of the PID controller for a small change in error. In terms of the frequency response, it increases the gain of all frequency components. The integral constant (K i ) decreases the settling or recovery time and helps in reducing the steady state error. In terms of frequency response, it is equivalent to a low pass filter, i.e., it has high gain at low frequencies and low gain at high frequencies. The derivative term (K d ) slows the rate of change of the PID controller output. In terms of frequency response, it has high gain at higher frequencies and low gain at lower frequencies [C31]. Figure. 3.3(a) 44

68 shows example bode plots for different values of K p. From this it can be observed that as K p increases, the bandwidth of the system increases. Figure. 3.3(b) shows the example bode plots for different values of K i. From this, it can be observed that as K i increases, the low frequency component gain increases. Figure 3.3(c) shows example bode plots when both K p and K i values increase simultaneously. In general, the higher the loop bandwidth, the better the transient performance of the closed loop system given that stability is still maintained [C12]. The theoretical limit on the bandwidth is half (50%) of the switching frequency. However, in practical designs, the bandwidth of the loop is usually designed to be not more than 20-30% of the switching frequency, because a bandwidth higher than this has very low noise susceptibility and may lead to instabilities [C23]. During transients, the bandwidth can be increased to a higher value such that the transient response is faster [C23]. If the higher bandwidth is used in steady state, the system may be unstable. Therefore, a better PID controller is the one which can have a higher bandwidth during the transient to improve the transient performance (lower voltage deviation and shorter settling time) of the system and yet maintain a lower bandwidth which makes the system stable during the steady state operation. This concept is implemented in the proposed adaptive PID controller with a special strategy. 45

69 (a) (b) (c) Figure. 3.3: Example bode-plots for different values of (a) Kp and (b) Ki and (c) Kp and Ki. Figure. 3.4 shows a general diagram of an adaptive digital PID controller. K i and K p values are adjusted by adjusting the values of α and β respectively. The equation for this Adaptive PID controller is as follows: V z v v K z v 1 z 1 ( ) (1 ) e comp error 1 error d error (3.2) 46

70 The values of and are not constant and are adaptively varied as a function of the error signal value and its peak value as discussed in the next section. Section 3.3 presents the adaptive control strategy used by the proposed AD-PID controller which smoothly transitions the PID parameters between steady state period values and dynamic transient period values, thus avoiding ringing and multiple overshoots/undershoots while reducing the power converter output voltage deviation and settling time. Vout ADC v error K p Vref To DPWM -1 Z K i -1 Z Ve comp () z K d Figure. 3.4: A general Adaptive digital PID controller realization diagram. Several methods are discussed in the literature in order to adaptively regulate a PID compensator or adaptively control the switching actions during dynamic transients [C18, C23, C28-C30]. The complexity and practicality of these methods vary as the amount of improvement varies. In addition, some of these methods are more sensitive to power stage parameters and parasitic compared to others. Many of these methods pre assume given specific transient magnitude and behavior which limits the achievable improvement to certain dynamic conditions. This chapter presents an Adaptive Digital PID (AD-PID) controller that result in dynamic performance improvement. The AD-PID uses a control strategy which smoothly transitions the PID parameters between steady state period values and dynamic transient period values, thus 47

71 avoiding ringing and multiple overshoots/undershoots while reducing the power converter output voltage deviation and settling time. This is achieved by dynamically detecting the peak value of the error signal, which is a function of the transient magnitude and nature, and utilizes it together with the error signal magnitude on cycle by cycle bases in a new adaptive PID control law. Moreover, the AD-PID controller adaptive operation does not require sensing parameters that does not exist in any conventional power controller. It only requires the knowledge of the output voltage, nothing more, and it is not sensitive to power stage characteristics because of its operation nature as will be discussed in this chapter. While other existing methods that are more complicated and depend on sensing several parameters may result in larger dynamic response improvement under given conditions, the AD-PID controller combines the simplicity and the ability to achieve dynamic transient improvement. Section 3.3 discusses the proposed AD-PID controller background. Section 3.3 presents the AD-PID control law and algorithm. Section 3.4 presents the guidelines to determine the values of parameters (K p-trans, K i-trans and V thr ) for AD-PID algorithm implementation. Section 3.5 presents the experimental prototype results while Section 3.6 presents a comparison with other non-linear PID controllers. The summary is given in Section AD-PID Control Law and Algorithm Figure. 3.5 shows theoretical waveforms that illustrate the proposed AD-PID controller operation. The controller flowchart shown in Figure. 3.6 observes the error (v error ) caused by the difference between the output voltage of the power converter and the reference voltage as shown in Figure Once v error is outside a very small window around zero (determined by the value of threshold voltage, V thr ), as a result of transient, the values of α and β (whose values are K i-steady and K p-steady respectively before the start of transient or in other words during steady state) 48

72 are increased abruptly to a large value ( determined by K i-trans and K p-trans respectively, the selection criteria of which will be given in Section 3.4) in order to increase the bandwidth and speed of the closed loop system. The controller then watches the v error in order to detect its peak value (V error-peak ) and the instant when it starts to decrease back towards zero as shown in Figure. 3.5 and Figure K p trans K p steady ( v error ) K i trans K i steady ( v error ) V error peak 0 verror ( n) V error peak vout () t V out peak Output Voltage V out peak I o max Output Current I o min Figure. 3.5: Illustration of the AD-PID controller operation. 49

73 Start K i steady K p steady Obtain the value of error signal v ( n) error No v ( n) V error thr Yes K i steady K p steady Yes v ( n 1) v ( n) error error No Verror peak verror ( n) K i trans K p trans V V v v error error error error ( n).( K K ) K peak i trans i steady i steady ( n).( K K ) K peak p trans p steady p steady v ( n 1) v ( n) error error Figure. 3.6: Flowchart for the proposed adaptive controller. 50

74 K, v ( n) V i steady error thr ( v ) K, v ( n) V and v ( n 1) v ( n) error i trans error thr error error v V error error ( n) peak ( K K ) K, v ( n) V and v ( n 1) v ( n) i trans i steady i steady error thr error error (3.3) K, v ( n) V p steady error thr ( v ) K, v ( n) V and v ( n 1) v ( n) error p trans error thr error error v V error error ( n) peak ( K K ) K, v ( n) V and v ( n 1) v ( n) p trans p steady p steady error thr error error (3.4) The AD-PID controller starts to adjust α and β values gradually toward their original steady state values (K i-steady and K p-steady respectively) by using Eq. (3.3) and Eq. (3.4), which utilize the detected peak value of the v error (V error-peak ) in addition to its magnitude on a cycle by cycle bases. It should be noted that V error-peak value is different for different transient magnitudes and types (ex. load current transient 1A-3A, load current transient 0A-7A, input voltage transient 8V-12V, etc.), which is a unique aspect of the AD-PID controller. It means that the AD-PID controller law adapts to different transient magnitudes and types. By this way, dynamic performance is improved at different transient types and magnitudes without the need to sense any additional variables other than the output voltage, which is readily sensed in any power controller. From Eq. (3) and Eq. (4), it can be noted that the rate of change of α and β values are inversely proportional to V error-peak. Moreover, V error-peak is detected adaptively in order to have a smooth 51

75 transition from high bandwidth (during transient-state) to low bandwidth system (during steadystate). It should be noted that if a fixed V error-peak is used in Eq. (3) and Eq. (4) rather than a variable V error-peak that is adaptively detected, the values of α and β may not be equal to the desired (by design) K i-trans and K p-trans at the peak instant of the error signal (observe the last part of each equation, this is because V error (n) / V error-peak will not be equal to one for all transient conditions), which may result in instabilities and/or oscillation during transients and thereafter in steady-state. But in the proposed method when V error-peak is adaptively detected and varied in Eq. (3) and Eq. (4), α and β will always be equal to the desired K i-trans and K p-trans at the peak instant of the error signal. This provides the AD-PID controller with the ability to adapt and work well under different magnitudes and types of transients. This is in fact one of the unique characteristics of the proposed AD-PID controller in addition to the smooth transition it provides between the transient-state and the steady-state operation AD-PID Control Law Design Guidelines This section provides the design guidelines for the AD-PID control law constants. Specifically, the selection of K p-trans, K i-trans and V thr in Eq. (3.3) and Eq. (3.4) for a given design of a conventional PID with K p-steady, K i-steady and K d-steady. The guidelines are summarized as follows: (1) A given conventional PID design for a switching power converter usually has a bandwidth of 5%-30% of the switching frequency and a phase margin of 45º-70º [C19,C20,C32]. This results in a set of K p-steady, K i-steady and K d-steady values. 52

76 (2) In order to compute K p-trans, K p-steady obtained in step 1 should be adjusted until a higher bandwidth is achieved with additional 10%-20% of the switching frequency. For example, if the design in step 1 result in a closed loop with 8% bandwidth, K p-trans is selected in order to have 20% bandwidth. (3) In order to compute K i-trans, K i-steady obtained in step 1 should be adjusted until the low frequency loop gain is increased by 20%-30%. (4) The threshold voltage, V thr, should be selected to be larger than that of the output voltage ripple of the power converter with a safe margin. A suitable value for V thr is twice the output voltage ripple. (5) The values of K p-trans, K i-trans and V thr are used in Eq. (3.3) and Eq. (3.4). These are the only three values that need to be predetermined for the AD-PID since V error-peak and v error (n) values are dynamically and adaptively detected during the operation. (6) It should be noted that the PID with K p-trans and K i-trans may not be stable in steady state (as will be shown in the next section) and cannot be used to replace the original conventional PID with K p-steady, K i-steady. The K p-trans and K i-trans values are only used during the transients by Eq. (3.3) and Eq. (3.4) and based on Figure. 3.6 AD-PID controller algorithm. The K p-trans and K i-trans values selected based on the above design guidelines should satisfy the following theoretical restrictions. (1) The selected K p-trans and K i-trans should not make the loop bandwidth more than half the switching frequency. While the K p-trans and K i-trans values can be selected such that the bandwidth is close to half the switching frequency, they should be selected such that the AD-PID bandwidth during dynamic transients is less than half the switching frequency with a sufficient safety 53

77 margin to account for component non-idealities, modeling errors, linearization errors of transfer functions among others. (2) The selected K p-trans and K i-trans values should result in negative closed loop poles in the s- plane or closed loop poles inside the unit circle in the z-plane. It should be noted that for the same power converter, there are several possible conventional (not adaptive) compensator designs, and this affects the coefficients selection of the AD-PID and its performance. Based on the above design guidelines and the power stage design given in Section 5 next, first, a conventional PID controller is designed with K p steady , K i steady and 0 K to yield a bandwidth of 29KHz and a phase margin of 45. The switching d steady frequency used is 350KHz. The value of K p-trans is selected to be to yield an additional ~12% bandwidth. The value of K i-trans is selected to be to yield a 20% increase in the low frequency gain from 53dB to 64 db. The value of V thr is selected to be 16.2mV, which is twice the ripple voltage. The selected K p-trans and K i-trans values result in a system bandwidth of 70KHz (during transients) which is below the half of switching frequency limit. In Figure. 3.2(c) shown earlier in this chapter, the bode-plot with lowest bandwidth represent the bode-plot with K p-steady and K i-steady values, and the bode-plot with highest bandwidth is the bode-plot with K p-trans and K i-trans values. Table I summarizes the values of different parameters used in the implementation of PID compensator and AD-PID controller algorithm in this chapter. With these values, Eq. (3.3) and Eq. (3.4) now become Eq. (3.5) and Eq. (3.6), respectively. 54

78 , v ( n) V ( v ) , v ( n) V and v ( n 1) v ( n) ( n) error error error error error v V error error peak , v ( n) V and v ( n 1) v ( n) error error error (3. 5) , v ( n) V ( v ) , v ( n) V and v ( n 1) v ( n) ( n) error error error error error v V error error peak , v ( n) V and v ( n 1) v ( n) error error error (3. 6) Table 3.1: Values of variables used in the design example. Variable Value Bandwidth Low frequency gain K p-steady K i-steady K d-steady K p-trans K i-trans KHz 70KHz 53dB 64dB V thr 16.2mV 3.5. Proof-Of-Concept Experimental Prototype Results A proof of concept experimental prototype is built in the laboratory for verification and test of the proposed AD-PID controller. The power stage is a single-phase DC-DC buck converter with input voltage range of 8V-10V and nominal output voltage of 1.5V. The output inductor is 440nH 55

79 and the output capacitance is1mf. The switching frequency of 350KHz is used. The digital controller is implemented using Altera FPGA, Altera Cyclone II EP2C35F672C6. Figure. 3.7 through Figure shows the experimental results. Figure. 3.7(a) shows the results with the conventional PID with optimized design for a load transient from 7A to 0A while Figure. 3.7(b) shows the results with the proposed AD-PID for the same load transient conditions. 57mV 50µs 7A (a) 45mV 22µs 7A (b) Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor Current (5A/div., 20µs/div.). Figure. 3.7: Experimental results of the prototype with zoomed in view under dynamic load stepdown transient of 7A-0A (a) with conventional PID controller and (b) with AD-PID controller. 56

80 Figure. 3.8(a) shows the results with the conventional PID for a load transient from 0A to 7A while Figure. 3.8(b) shows the results with the proposed AD-PID for the same load transient conditions. Figure. 3.9 and Figure show the results with conventional PID, and proposed AD-PID under load step-down and step-up transients of 6A to 2A and 2A to 6A, respectively. 65mV 50µs 7A (a) 48mV 22µs 7A (b) Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor Current (5A/div., 20µs/div.). Figure. 3.8: Experimental results of the prototype with zoomed in view under dynamic load stepup transient of 0A-7A (a) with conventional PID controller and (b) with AD-PID controller. 57

81 32mV 30µs 4A (a) 25mV 21µs 4A (b) Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor Current (5A/div., 20µs/div.). Figure. 3.9: Experimental results of the prototype with zoomed in view under dynamic load stepdown transient of 6A-2A (a) with conventional PID controller and (b) with AD-PID controller. 58

82 30µs 40mV 4A (a) 20µs 33mV 4A (b) Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor Current (5A/div., 20µs/div.). Figure. 3.10: Experimental results of the prototype with zoomed in view under dynamic load step-up transient of 2A-6A (a) with conventional PID controller and (b) with AD-PID controller. 59

83 (a) (b) Top Trace: Output Voltage (50mV/div AC coupled, 20µs/div.) and Bottom Trace: Inductor Current (5A/div., 20µs/div.). Figure. 3.11: Experimental results of the prototype with zoomed in view under steady-state operation (a) with PID controller with K p-trans and K i-trans and (b) with PID controller with K p-steady and K i-steady. It can be observed from the results that the AD-PID controller results in reduction in the output voltage dynamic deviation and in shorter settling time. Moreover, this is achieved with no additional oscillations or ringing during the AD-PID operation. The output voltage with the AD- PID controller looks similar in shape to that with conventional PID controller, but with less output 60

84 voltage dynamic deviation and with shorter settling time. For this specific design example, the overshoot is reduced by 15mV (about 26%), the undershoot is reduced by 15mV (about 26%) and the settling time is reduced by more than 25µs (> 50%) in the case of 0A-7A load transient range. In the case of 2A-6A load transient range, the overshoot is reduced by 7mV (about 18%), the undershoot is reduced by 6mV (about 15%) and the settling time is reduced by 9µs (about 30%). As mentioned earlier in the chapter, if the K p-trans and K i-trans values are used during the steady state operation, the closed loop system will be unstable. Figure. 3.11(a) shows the experimental results for this case where the instability can be observed since K p-trans and K i-trans values are used in steady state. Figure. 3.11(b) shows the steady state experimental results with K p-steady, K i-steady values where the stable operation can be observed Comparison of AD-PID with Other Non-Linear PID Strategies The non-linear PID strategy proposed in [C23] uses hysteretic control to switch abruptly between two predetermined compensators. This type of action may cause ringing and instability problems when switching between transient and steady state operations. Moreover, the performance may be affected for different transient types and magnitudes. The non-linear PID strategy proposed in [C18] varies the PID parameters smoothly. However, the strategy requires a complicated design and it requires selection of several variables that affects performance under different transient types and magnitudes. It has two threshold levels for the variation of error signal namely a and b. Also, for different PID constants, the values of a and b can be different. The criteria for smooth variation of constants within the window between a and b is not specified. 61

85 The AD-PID controller utilizes a scheme that makes sure that the transition between the steady state and transient operation modes is smooth and free of additional oscillations and ringing. Moreover, the AD-PID controller design and operation do not depend on any additional assumption of the transient magnitudes or types. It is able to adjust and adapt its operation for different transient magnitude and type since it always detects the peak value of the voltage error signal and utilizes it in its control low as discussed earlier in this chapter Summary The chapter presents an adaptive digital PID controller in order to improve the dynamic performance of power converters closed loop system. The AD-PID reduces the dynamic output voltage deviation and settling time by using a simple strategy and without the need to sense any additional information other than the output voltage of the power converter. The AD-PID controller utilizes a scheme that makes sure that the transition between the steady state and transient operation modes is smooth, and free of additional oscillations and ringing. Moreover, the AD-PID controller design and operation do not depend on any additional assumption of the transient magnitudes or types. It is able to adjust its operation for any transient magnitude and type since it always detect the peak value of the voltage error signal and utilize it in its control law. The operation principle and experimental results of the AD-PID controller are presented and discussed in this chapter and compared with conventional PID controller. 62

86 CHAPTER 4 A NOVEL ADAPTIVE AUTO-DESIGN AND AUTO-TUNING METHOD FOR CLOSED-LOOP CONTROLLERS OF POWER CONVERTERS 4.1. Introduction The design and tuning of the closed-loop feedback control of power converters for stable operation with high dynamic performance over variable and wide operating conditions is critical in many applications [D1-D4]. In the design process, the power stage transfer function and design parameters are used to design the closed-loop compensator [D4-D9]. The inaccuracy in the knowledge of the power stage components and their parasitic values in addition to the approximations used in the transfer functions affect the design accuracy and performance of the designed compensator. Additional sources of inaccuracy include the delay of the switches drivers, the digital logic component delays, and the Analog-to-Digital Converter (ADC) delays when a digital controller is used. The control loop design is usually based on conventional methods with rule of thumb design guidelines such as gain and phase margins with bode-plots and/or root-locus pole-zero locating [D7-D10]. The drawbacks of using these methods include one or more of the following: (1) they require the knowledge of the power stage transfer function (frequency response), (2) their results are sensitive to design approximations and power stage components parasitic values, (3) the theoretical design is usually not sufficient and additional adjustment or tuning is usually required for the implemented hardware. All this makes the design of a high performance closed 63

87 loopcompensator a non-easy task and requires a tedious manual tuning in the theoretical design and in the experimental hardware. The advantages of digital controllers in power converter applications have made them stronger competitors and alternative to their analog counterpart in several applications [D10- D19]. These advantages include the digital controllers ability and easiness to implement sophisticated algorithms and laws to improve dynamic and efficiency performances of power converters, they are easier to be reconfigured and scaled compared to their analog counterpart, and they can potentially reduce or eliminate the controller component variations and sensitivity that affect the controller performance [D10-D19]. On the other hand, the limited resolution, the size, cost and power consumption incurred from the required high-speed high-resolution Analogto-Digital Converters (ADCs) and Digital Pulse Width Modulators (DPWMs) are among the challenges in designing and utilizing digital controllers in power converter applications. In order to alleviate the challenges and difficulties in closed-loop compensator design discussed earlier, researchers have utilized digital controllers ability to auto-tune and/or calibrate the compensator [D20-D28]. In [D5-D7, D20, D23, D28] auto-tuning controller schemes, the closed loop is perturbed using a test signal and the response to that signal is obtained to find the frequency characteristics of the loop. The phase margin and gain margin are obtained and the necessary adjustment of compensator parameters is made to attain the desired phase margin and gain margin. In [D21], an auto-tuning controller scheme based on Model Reference Impulse Response is presented. This auto-tuning controller compares the measured system response with a reference system response and adjusts a compensator parameter accordingly to minimize the error function. In [D22], an auto-tuning controller based on the relay feedback method is presented. It tunes the proportional-integral-derivative parameters of the 64

88 compensator based on a desired phase margin and control loop bandwidth. In [D26], a selftuning analog current-mode controller is presented. The presented method is based on the insertion of nonlinear (NL) blocks in the control loop and measurement of the closed-loop properties such as gain margin, phase margin, and crossover frequency by perturbing the output voltage. The controller is then tuned according to desired set of specifications. The power converter closed-loop auto-tuning schemes discussed in the literature, such as the examples discussed above, usually have one or more of the following characteristics: (1) they are relatively complicated and require adding significant hardware, (2) they require breaking the control loop, interrupting the power converter system operation and/or injecting signal (disturbance) that affects the output voltage regulation, and (3) their operation is based on conventional design methods and the associated rule of thumb design criteria. In this chapter, an online closed-loop-compensator auto-tuning digital power controller (ATerror controller for abbreviation) is proposed. The proposed method is relatively simple and does not require the knowledge and/or measurement of the power stage or closed-loop frequency response and does not depend on conventional design methods and the associated rule of thumb design criteria. Section 4.2 discusses the bases for the proposed concept of the ATerror controller, which is called Compensator Error Observe and Modulate method (CEO&M Method). Section 4.3 presents the ATerror controller digital implementation algorithm and architecture. The proof-ofconcept experimental prototype results are presented in section 4.4 and the conclusion is given in Section

89 4.2. Bases of the Proposed Online Auto-Tuning Controller The proposed online auto-tuning controller is based on observing the compensated error signal time domain characteristics, which is readily available in any compensated closed-loop feedback controller. This method is referred to as CEO&M method. Figure. 4.1 shows a block diagram of a power converter system with voltage-mode closedloop feedback control. Transfer function notation for each part of the system is indicated on the figure. The difference between the reference voltage and the output voltage (the uncompensated error) is applied to a compensator, such as PID (Proportional-Integral-Derivative) compensator to result in a compensated error signal ( V e comp ). V e comp has a DC component and an AC component and is used to generate the controller duty cycle using a Pulse Width Modulator (PWM). V in Power Converter Vo PWM V e comp GM () s Gp ( s) Closed Loop Compensator G ( s) or G ( z) c c V ref Figure. 4.1: A block diagram of a power converter system with closed loop control. The CEO&M will first be introduced using simulation results of a design example. The design example is a DC-DC buck converter closed-loop system with a three-pole two-zero compensator (one pole is at zero), 12V input voltage, 1.5V output voltage, 0.1µH output inductor, 350µF output capacitor, and 1MHz switching frequency ( f sw ). Figure. 4.2 shows the system bode-plots 66

90 (for Gp( s) Gc ( s) GM ( s ) ) for different gain (K) values and different pole (P1) locations (one pole location is varied). (a) (b) Figure. 4.2: Bode-plots for (a) different gain (K) values and (b) different pole (P1) locations. 67

91 (a) (b) Figure. 4.3: Simulation results of a DC-DC buck converter to demonstrate the basis of the proposed CEO&M control concept based on several K values (Note that Ve conv. V e comp ): (a) during steady-state and (b) during step-up load transient. The power converter system is simulated using Matlab /Simulink software package. The simulation results are shown in Figure. 4.3 and Figure. 4.4 that correspond to Figure. 4.2(a) and Figure 4.2(b), respectively. Figure. 4.3 and Figure. 4.2(a) show that as the compensator gain K increases, which corresponds to increase in bandwidth and system speed, the peak-to-peak value 68

92 of the compensated error signal ( V e pp ) increases and the dynamic performance is improved (smaller output voltage dynamic deviation and shorter settling time). This occurs up to a point where the system becomes unstable and the frequency of V e comp ( f Ve comp ) becomes lower than the switching frequency. Similarly, Figure. 4.4 and Figure. 4.2(b) show the same behavior as the pole location P1 is moved in a direction that results in increasing the system bandwidth and improving the system dynamic performance. (a) (b) (c) Figure. 4.4: Simulation results of a DC-DC buck converter to demonstrate the basis of the CEO&M control concept (Note that Ve conv. V e comp ) based on several pole locations (one pole is moved): (a) during steady-state, (b) during step-up load transient and (c) during step-down load transient. 69

93 Therefore, the following conclusion can be drawn from the previous discussion: A closed loop controller s compensator can be tuned or optimized by perturbing one or more of the compensator parameter values such as gain, poles and/or zeros in a direction that will increase V e pp as long as Ve comp sw f f, or until a maximum possible V e pp value is obtained while f f is still maintained. Ve comp sw The theoretical verification to the fact that V e pp is larger for closed-loop with higher bandwidth is relatively simple. For simplicity, assume that the compensator is a simple low pass filter with a gain (K) and a cutoff frequency c as follows: K Gc ( s) Ve comp ( s) Gc ( s) Ve comp ( s) s 1 1 c K s c (4.1) Eq. (4.1) indicates that the magnitude of Ve comp () s ( Ve comp () s ) increases as K (the gain) increases and as c (the pole) increases, which indicates a faster system. Similar behavior is expected with a higher order low-pass filter type (several poles in addition to several zeros). As illustrated in Figure. 4.5, as the bandwidth is increased (by increase of gain), V e pp becomes larger up to a point where the closed-loop system becomes unstable, and the frequency V ( f Ve comp ) becomes lower and not equal to the digital ramp switching frequency. This of e comp will cause the PWM output to have a frequency that is lower than the switching frequency (or the ramp signal frequency). This point is likely to occur as the bandwidth becomes closer to half of the switching frequency [D30- D34]. 70

94 Lower Bandwidth Unstable Higher Bandwidth Figure. 4.5: An illustration of the compensated error signal behavior under different bandwidth values with analog compensator. V e comp LBW Lower Bandwidth V e comp U Unstable DigitalRamp Higher Bandwidth V e comp HBW D Ve comp LBW D Ve comp HBW D Ve comp U Figure. 4.6: An illustration of the compensated error signal behavior under different bandwidth values with digital compensator. Even though the previous discussion and example is based on a compensator transfer functions in analog domain, it should be obvious that the same argument is valid when a digital compensator implementation is used. An example digital equivalent to Figure 4.5 is shown in Figure 4.6. Figure 4.6 shows a digital ramp and digitally compensated error signal assuming 71

95 multisampling operation per switching cycle (multiple ADC samples used for multiple calculations per switching cycle) [D31, D32]. In a conventional digital controller, the duty cycle command can be calculated either once (single sample) each switching cycle or multiple times (multisampling rate) [D31] in order to generate a compensated error signal. Figure. 4.7 shows a DC-DC buck converter with digital closed-loop compensator and a proposed auto-tuning controller (ATerror) block diagram. Based on the previous discussion, by observing V e pp and f Ve comp, the closed-loop compensator parameters can be tuned to achieve a closed-loop converter system with better dynamic performance by tuning one or more of the compensator parameters to a more near to optimum value for a given power converter design. This is discussed further in the Section 4.3. S u i L Lo Vin D Drivers Latches D1 S l Co + Vo Io D - DPWM Modulator V e comp Closed Loop Compensator ADC f sw ATerror Online Auto-Tuning Controller Vref Figure. 4.7: DC-DC buck converter with digital closed-loop compensator and ATerror Controller Online Auto-Tuning Digital Controller Algorithm and Architecture As shown in Figure. 4.7, the main input to the ATerror controller is V e comp. The only other input is the switching frequency ( f sw ) which is the DPWM (Digital Pulse Width Modulation) 72

96 frequency in order to synchronize the operation of the ATerror controller when its V e pp and f Ve comp are measured. These two inputs are readily available in the controller, and therefore, no additional voltage or current sensors are needed. Figure. 4.8 shows a general implementation flowchart of the ATerror Controller. The controller finds V e pp value several times, over H switching cycles in order to confirm steady-state operation and the accuracy of V e pp. Since auto-tuning is performed during a steady-state operation, it is necessary to confirm the steady-state operation of the power stage. If the V e pp value is stable over the H switching cycles (note that one V e pp value is recorded in the digital controller every one switching cycle), the controller will adjust the closed-loop compensator parameter(s) (such as gain, pole or zero) in a direction that will increase or decrease the V e pp value (which result in increase or decrease in the closed-loop bandwidth) after confirming the fve comp f sw condition. Note that fve comp f sw condition can be verified, for example, every switching cycle by measuring the time between two compensated error signal peaks in two or more consecutive switching cycles (this will be detailed in the next section). The fve comp f sw condition is considered satisfied if the consecutive peak values of e pp V are equal or within a specified error range (to account for digital resolution errors). The increase/decrease decision of the compensator parameter being tuned is based on the comparison between the new value of V e pp ( Ve pp () r ) and the previous value of V e pp ( Ve pp ( r 1) ). If Ve pp ( r) Ve pp ( r 1) is satisfied, the ATerror controller will adjust the closed-loop compensator parameter(s) in a direction that will increase the V e pp (and hence closed-loop bandwidth). Taking the compensator gain (K) as an example here, K value is increased. The ATerror controller will then wait Y 73

97 switching cycles to ensure new steady-state operation before repeating the process again. If Ve pp ( r) Ve pp ( r 1) is not satisfied, the ATerror controller will repeat the process starting from recording V e pp again. Start Reset SC Counter Ve pp ( r 1) Ve pp ( r) Increment Counter SC by one Obtain Ve comp ( n ). Ve pp ( m) Ve pp ( m 1) No SC > H Yes No Stop tuning or Wait Z switching cycles to restart V ( n 1) V ( n) e comp e comp Yes V ( n) V ( n 1) e comp No e comp Yes Ve pp ( r) Ve pp ( m) Change a compensator parameter in a direction that decreases bandwidth ex. gain k, Pole p and/or Zero z Ve max Ve comp ( n) V ( n) V ( n 1) e comp Yes e comp Ve min Ve comp ( n) No f Ve comp SC > H f Yes sw No Figure Yes Ve pp ( r) Ve pp ( r 1) No V ( m) V V e pp e max e min Yes Change a compensator parameter in a direction that increases bandwidth ex. gain k, Pole p and/or Zero z Figure Wait Y switching cycles Figure. 4.8: General main implementation flowchart of the ATerror controller. If the value of V e pp is not the same or not stable over the H switching cycles, the controller will check if this condition is because fve comp f sw. If it is the case, the ATerror controller will vary the appropriate parameter (in this example, reduce K) in a direction that will reduce V e pp 74

98 (and hence closed-loop bandwidth) until the condition fve comp f sw is satisfied and then stops its operation for Z switching cycles assuming that a more near to optimum value for the parameter (K value, in this example) has been reached before starting the new auto-tuning process again (the new auto-tuning and calibration cycle). The new auto-tuning process can be performed periodically or when a change is detected that requires a new auto-tuning operation. It should be noted that there may be several possible ATerror controller algorithms/implementations based on the CEO&M concept, and one of them is described in the next section. Also, more specific implementation details for the parts of Figure. 4.8 controller flowchart are presented in Figure and Figure Proof-Of-Concept Experimental Prototype Results This section is divided into two parts. In the first part an experimental verification for the CEO&M concept is presented, and in the second part, the experimental results of the ATerror controller (which is based on the CEO&M concept) are presented and discussed. A proof of concept experimental prototype is built in the laboratory in order to verify the proposed concept and controller. The prototype is a single phase buck converter with a nominal input voltage of 9V and a nominal output voltage of 1.5V, output inductor of 440nH, output capacitance of 2.8mF, switching frequency of 342kHz and full load current of 8A. Fully digital control hardware is used to implement the closed-loop voltage-mode feedback compensator and the ATerror controller. The output voltage ADC has an 8-bit resolution and takes 2.8M sample/second of the output voltage. However, only 4 ADC samples are utilized to obtain (calculate) 4 values of V e comp and the duty ratio update is sent to the DPWM once each switching cycle. The DPWM used is with 10-bit resolution. The digital controller is implemented using Altera FPGA Altera Cyclone II EP2C35F672C6. 75

99 The digital compensator architecture used is as shown in Figure. 4.9, where K p 1.39, K , K and K T is the gain which is varied for optimization by the ATerror i controller. d v out ADC K T v error K p Vref -1 Z Ki 1 Gc ( z) KT ( K p K (1 )) 1 d z 1 z K i -1 Z -1 Z K d To DPWM Ve comp ( z ) Figure. 4.9: Digital compensator used in the proof of concept experimental prototype Experimental Verification of the Auto-Tuning Controller Bases The gain of the compensator ( K ) is varied in order to investigate the effect on T V e comp. Figure shows the experimental results of the output voltage and V e comp under three different example values of K T as indicated in Figure caption. The three different gain values correspond to three different bandwidth values. The lower gain value results in a lower bandwidth, the medium gain value results in a medium bandwidth, and the higher gain value results in a higher bandwidth that causes the system to start becoming unstable as shown in the figure. It could be observed from Figure results that as the gain is increased (and hence bandwidth is increased), V e pp is increased and the dynamic output voltage deviation and settling time are reduced, up to a K T value that makes the system unstable. It can also be observed from Figure 4.10(e) that, in this unstable case, the frequency of the compensated error signal is not equal to the switching frequency ( f Ve comp f sw ). 76

100 95mV 220µs 220µs 100mV 20mV (a) (b) 38mV 100µs 90mV 100µs 40mV (c) (d) 30mV 90µs 160mV 90µs 35mV (e) Time: 2.5µs/div. Top Trace (Output Voltage, AC Coupled): 30mV/div. Bottom Trace (Compensated Error Signal,, AC Coupled): 50mV/div. V e comp (f) Time:100µs/div. Trace (Output Voltage, AC Coupled): 60mV/div. Figure. 4.10: Experimental results of a DC-DC buck converter to demonstrate the basis of the proposed CEO&M control concept when varying gain. (a) and (b): Lower gain ( K T ). (c) and (d): Medium gain ( K T ). (e) and (f): Higher (Unstable) gain ( K T 2.531). (a), (c) and (e): During Steady-State Operation. (b), (d) and (f): Under 8A-0A-8A Load Current Transient. 77

101 These results agree with the theoretical assumptions of the CEO&M concept presented earlier. The same behavior using other several commercially available power converter prototypes with analog controllers is also verified. These results show that CEO&M concept is valid, and it can be utilized for the auto-tuning of the compensator s parameters Experimental Operation and Results of the Online Auto-Tuning Controller The ATerror controller is used to auto-tune the gain, K T, of the compensator as an example parameter. A general implementation flowchart of the ATerror controller is discussed in the previous section (Figure. 4.8). More ATerror controller operation details are given in this section. At the beginning of the auto-tuning cycle, the ATerror controller adjusts the gain of the compensator and identifies the direction of gain change (increase or decrease) that results in an increase in V e pp, while maintaining fve comp f sw, as shown in Figure flowchart. The ATerror controller first decrements (increments) the gain of the compensator (as illustrated in Mode A1 of Figure. 4.13, for decrementing the gain K ) and compares the V e T pp under the current gain value ( Ve pp () r ), with the V e pp under the previous gain value ( Ve pp ( r 1) ). If there is an increase in V e pp ( Ve pp ( r) Ve pp ( r 1) ), the controller identifies this decrement (increment) direction of gain as the correct direction to adjust the gain to increase V e pp. Otherwise, increment (decrement) direction of gain is identified by the controller as the correct direction to adjust the gain to increase V e pp. This process of decrement (increment) of gain occurs for S steps. After the end of S steps, the gain is once again incremented (decremented), until it reaches the initial gain (which takes S-1 steps), when the process of gain change started (as illustrated in Mode A2 of Figure. 4.13, for incrementing the gain K T ). 78

102 Start DC Counter = 1 Increment DC Counter Mode A2 No Yes DC Counter < S Detection = 1 No Mode A1 DC Counter < 2S No Yes Yes Increment K Sign(p) = 1 T Detection = 0 Decrement Sign(p) = 0 K T Yes V ( r) V ( r 1) e pp e pp No V ( r) V ( r 1) Yes e pp e pp No Sign(p) = Sign(p-1) Sign(p) = Not Sign(p-1) Sign(p) = Sign(p-1) Sign(p) = Not Sign(p-1) Direction = Sign(p) Yes Direction = 1 No Figure f Yes Ve comp f sw No Yes f Ve comp f sw No Decrement KT Increment KT DecrementKT Increment KT Wait for Z cycles Figure. 4.11: A flowchart for the detection of direction of gain change (increase/decrease). The duration of the direction detection process is determined by S. The ATerror controller initializes the detection process by setting Detection=1, and initializing DC Counter=1 as shown in Figure The variable Sign is set to be equal to 0, the gain K T is decremented 79

103 and the corresponding change in V e pp is observed. If V e pp s increased ( Ve pp ( r) Ve pp ( r 1) ), then the variable Direction is set to 0 through the variable Sign. Otherwise, Direction is set to 1 by taking the complement of Sign. At the end of the operation cycle of setting Direction value, DC Counter is incremented. This process repeats until the DC Counter value is greater than S (as illustrated in Mode A1 of Figure. 4.13). When DC Counter is greater than S, the gain K is incremented, and the change in V e pp is observed (as shown in T Figure and illustrated in Mode A2 of Figure. 4.13). Based on the change in V e pp, the Direction is set through the variable Sign as described earlier. When the DC counter value is equal to twice S, the gain change direction is set in Direction (0 or 1) and the value of Detection is set to 0 to indicate that the gain direction detection process is completed. The value of Direction is set to 1 if an increase in the gain (or any other variable to be tuned such as a zero or a pole) increases V e pp.otherwise it is set to 0. Once the correct/required direction of gain change to increase V e pp is identified, the ATerror controller adjusts the gain in that direction and observes V e comp for any instability as described in Figure. 4.8 flowchart, or in other words, it watches for the condition when fve comp f sw The controller flowchart for the detection of the condition fve comp f sw is shown in Figure In this experiment, instead of measuring f Ve comp in order to compare it with sw f, the condition fve comp f sw is detected/identified by observing the difference between the consecutive V e pp values over several switching cycles, for simplicity. If this difference is above a preferment value, the controller determines that fve comp f sw. In other words, fve comp f sw is identified (indicating an unstable output voltage) if the deviation between two consecutive values of V e pp 80

104 ( Ve pp ( r) Ve pp ( r 1) ) is greater than an upper limit value ( HL ). The gain is first adjusted in the direction identified earlier until the deviation between two consecutive cycles is greater than HL ( Ve pp ( r) Ve pp ( r 1) HL ). Mode B in Figure illustrates the increase of gain until Ve pp ( r) Ve pp ( r 1) HL is satisfied. Once this condition is detected, the controller starts adjusting the gain value in the opposite direction that decreases V e pp (as illustrated in Mode C of Figure. 4.13) until the difference ( Ve pp ( r) Ve pp ( r 1) ) is less than a lower limit ( LL ),which is considered a stable condition. At this stable condition, the controller sets the gain value and waits for a predetermined amount of time (Z switching cycles) before another autotuning process is initiated. As shown in Figure. 4.12, at the beginning of the frequency change detection process, the variable Flag is set to be equal to 1, which indicates that fve comp f sw. Depending on the value of Direction, the gain, K T, is incremented or decremented. When Direction = 0 (Direction = 1), the gain K T is incremented (decremented) until the deviation between the values of V e pp ( Ve pp ( r) Ve pp ( r 1) ) is larger than HL (as illustrated in Mode B of Figure. 4.13). When the deviation in V e pp exceeds HL, Flag is set to 0 indicating the frequency change condition ( f Ve comp f sw ). The gain is then decremented (incremented) until it reaches the value where the deviation between V e pp values is less than LL (as illustrated in Mode C of Figure. 4.13). For this experiment, HL 20mV and LL 16mV are selected. 81

105 Start Flag = 1 Obtain Direction Direction = 1 No Yes Mode C No Flag = 1 Yes Mode B Ve pp ( r) Ve pp ( r 1) LL Ve pp ( r) Ve pp ( r 1) HL Yes No Wait for Z cycles No Decrement KT Yes Flag = 0 Increment KT No Flag = 1 Yes Ve pp ( r) Ve pp ( r 1) LL Ve pp ( r) Ve pp ( r 1) HL Yes No Wait for Z cycles No Increment KT Yes Flag = 0 Decrement KT Figure. 4.12: A flowchart for the detection of frequency change and setting of gain. 82

106 Ve pp ( r) Ve pp ( r 1) HL K T 1 2 2S-1 Ve pp ( r) Ve pp ( r 1) LL S+2 S+1 S Mode A1 Mode A2 Mode B Mode C Figure. 4.13: Illustration of the controller operation to determine the variable under auto-tuning (the gain here) required direction change and the detection of frequency change condition. Figure shows the experimental waveforms of the prototype during auto-tuning operation. Figure. 4.14(a) shows an auto-tuning cycle starting from an initial gain value until the ATerror controller converges to new gain value, for demonstration purposes. As it can be observed from Figure (a), the ATerror controller initially identifies the correct direction of the gain change, followed by adjusting the gain and the detection and confirmation of the frequency condition (as described earlier) before setting the new optimized gain value. Figure. 4.14(b) shows the periodic re-auto-tuning operation of the controller (the optimized gain value stays same since it is for the same converter design and operating conditions). Figure shows the comparison in the transient response of the converter, before autotuning and after auto-tuning. Figure. 4.15(a) shows the response of the controller before autotuning due to a step-down load transient of 8A to 0A. Figure. 4.15(b) shows the response of controller after auto-tuning is complete with ATerror controller for the same load variation of 8A to 0A. 83

107 (a) Time: 50ms/div. (b) Time: 100ms/div. Top Trace (Output Voltage, AC Coupled): 60mV/div. Bottom Trace (gain): /div. Figure. 4.14: Experimental waveforms of the prototype with the ATerror controller. (a): The variation of gain until new optimized gain value is achieved.(b): Periodic tuning operation of the ATerror controller. 84

108 75mV 210µs (a) 31mV 90µs (b) Time: 50µs/div. Output Voltage, AC Coupled: 60mV/div. Figure. 4.15: Dynamic response of the power converter during a load transient of 8A to 0A (a) before auto-tuning (b) after auto-tuning Summary This chapter proposes a method to tune the power converter closed-loop compensator parameters to improve the dynamic performance. The CEO&M concept observes the time domain characteristics of the compensated error signal ( V e comp ), namely the peak-to-peak value ( V e pp ) and frequency ( f Ve comp ) to tune the compensator. This method eliminates several drawbacks of 85

109 the conventional auto-tuning schemes as discussed in this chapter. The proposed method does not require the knowledge of the power stage frequency response, does not depend on any conventional rule of thumb control design criteria such as gain and phase margins, and is dependent only on the time domain parameters of the compensated error signal. A proof of concept experimental prototype results are presented for verification. The proposed CEO&M concept is then utilized to implement an online closed-loopcompensator auto-tuning digital controller (ATerror controller). The ATerror controller does not require the knowledge and/or measurement of the power stage or closed-loop system frequency response(s). The digital implementation algorithm, architecture, and a proof-of-concept experimental prototype results are presented for the ATerror controller. While in this chapter s experiment, the compensator gain is auto-tuned, the method could also be used to auto-tune other parameters of the compensator such as pole and zero locations. 86

110 CHAPTER 5 AN ADAPTIVE DIGITAL VARIABLE FREQUENCY CONTROL SCHEME 5.1. Introduction DC-DC switching power converters are widely used in many low power to high power applications [E1-E6]. In order to regulate the output voltage of these power converters, analog controllers or digital controllers can be used [E6-E12, E30, E31]. These controllers generate the appropriate control command [E7], which is the duty cycle and/or switching frequency here, under steady-state and dynamic operations. Digital power control has made the implementation of complex and sophisticated algorithms that result in the power converter performance improvement [E13 E15]. Also, the aging effects of the digital controllers are negligible compared to the analog controllers. Figure. 5.1 shows the block diagram of digital controller implementation for a power converter. The dynamic performance of the power converter is critical in many applications [E16-E22]. Two of the most important parameters that are measures of transient performance of power converter are the output voltage overshoot/undershoot and the settling time. The dynamic performance can be improved by means of adaptive control techniques. The method in [E23] utilizes an analog control law that varies the amplitude of the ramp signal dynamically while maintaining constant switching frequency in order to improve the dynamic performance of a power converter. The methods in [E24] and [E25] utilize the adjustment of the PID controller 87

111 constants in order to improve the transient performance. The methods in [E26] utilizes a hysteretic control that switches the compensators used during the steady state and transient in order to improve the performance of the converter during transient. Vin S U D Drivers Latches D1 i L S L Lo Co + Vo Io D - DPWM Modulator Compensator V error ADC V c Vref Figure. 5.1: Block diagram of a Power Converter with Digital Controller. In this chapter, two control methods/laws are proposed in order to improve the dynamic performance of power converters, and the improvement in their dynamic performance is compared. The proposed control methods do not require sensing any other additional parameters that are not already available in any conventional controller, and it is relatively simple to realize. Next section reviews the operational principle of conventional DPWM (Digital Pulse Width Modulation) schemes. Section 5.3 presents the proposed dynamic switching frequency variation control methods/laws and algorithms. Section 5.4 presents the theoretical proof for the proposed methods. Section 5.5 presents experimental results obtained for a proof-of-concept experimental prototype. The conclusion is given in Section

112 5.2. Digital Pulse Width Modulation The output of the converter is maintained at a desired value by varying the ON/OFF condition of the switches ( S U and S L ). This is achieved by generating a control command signal ( D or D A ) by comparing the compensated error signal ( V c ) to a reference ramp signal. This process is referred to as PWM (Pulse Width Modulation), which is illustrated in Figure. 5.2 during a steady state operation of a power converter. Figure. 5.2(a) shows the Analog PWM (APWM) case while Figure. 5.2(b) shows the Digital PWM (DPWM) case [E9, E10, E27-E30]. In digital control, the DPWM can be implemented using different architectures: Countercomparator based DPWM, delay line based DPWM, ring oscillator DPWM, and hybrid segmented DPWM [E4-E8], among others. T A V () c t V ( ) c n V peaka Duty Cycle Duty Cycle (a) (b) Figure. 5.2: Generation of duty cycle command signal with (a) analog controller (b) digital controller. Consider the counter-comparator based DPWM implementation as an example. Figure. 5.3(a) shows the DPWM operation principle illustration during steady-state. The compensated error signal ( V c ) value is compared with the counter value, and when the value of V c is greater than the value of the counter, the switch S U control is set to high or turned ON as shown in Figure 5.3(a). Otherwise it is turned OFF. 89

113 V ( ) c n Duty Cycle (a) V ( ) c n Duty Cycle (b) V ( ) c n Duty Cycle (c) Figure. 5.3: DPWM operation principle illustration with fixed switching frequency during (a) steady state (b) step-up load transient and (c) step-down load transient. During transient operation, the compensated error signal value is greater than or less than its steady-state value depending on whether the transient is a step-up load transient or a step-down load transient, respectively. This results in a duty cycle value greater than or less than the steadystate value during the dynamic operation. Illustrations of these two conditions are shown in Figure. 5.3(b) and Figure. 5.3(c), respectively. Section 5.3 gives the details of the proposed control law and algorithm for its implementation. 90

114 5.3. Adaptive Switching Frequency Control Schemes The proposed Dynamic Variable Switching Frequency (DVSF) control is based on adjusting the switching frequency of the controller as a function of the uncompensated error signal ( V error ) during the controller dynamic operation. The variable switching frequency operation can be realized by adjusting the maximum counts in a counter-comparator based DPWM for example. The frequency of the DPWM is a function of the counter clock frequency, and the limit on the number of counts of the counter. If f clk is the clock frequency, and C limit is the limit on the number of counts of the counter, then the switching frequency of the DPWM is given by Eq. (5.1) f DPWM 1 f C clk limit (5.1) In DPWM, when the frequency is varied using the number of counts as discussed above, the gain ( G DPWM ) of the DPWM also varies as given by Eq. (5.2), where V ADC is the resolution of Analog to Digital Converter (ADC). G DPWM 1 (1 C ) limit V ADC (5.2) The DVSF controller increases the switching frequency during output voltage undershoots and decreases the switching frequency during output voltage overshoots. The variation of duty cycle as a result of variation of switching frequency is illustrated in Figure Two methods for variation of switching frequency are proposed. These methods are referred to as DVSF I and DVSF II. 91

115 V ( ) c n Duty Cycle (a) V ( ) c n Duty Cycle (b) V ( ) c n Duty Cycle (c) Figure. 5.4: Illustration of operational principle of DPWM with variable switching frequency during (a) steady-state (b) step-up load transient which causes output voltage undershoot and (c) step-down load transient which causes output voltage overshoot DVSF I Figure. 5.5 shows the theoretical waveforms that illustrate the proposed adaptive switching frequency controller operation. The controller observes the value of error signal ( V error ) which is a measure of output voltage deviation from a desired reference voltage. When V error is outside a small window (defined by a threshold value, V thr ) around zero, as a result of transient, the value of f DPWM is increased or decreased depending on whether the value of V error is positive or negative respectively as given by Eq. (5.3). Figure 5.6 shows the controller flowchart for the implementation of DVSF I control law. It can be observed that the direction of change in the 92

116 duty cycle, and the direction of change in the digital ramp peak value as a result of varying the switching frequency work together in a way to reduce the output voltage deviation, overshoot and undershoot. f, V ( n) V DPWM steady error thr f ( n) f V ( n), V ( n) V DPWM DPWM steady error error thr (5.3) f V ( n), V ( n) V DPWM steady error error thr T ( ) DPWM n f DPWM steady f ( ) DPWM n 0 V ( n) error Vout ( n) Output Voltage I o max Output Current I o min Figure. 5.5: Illustration of Dynamic Variable Switching Frequency (DVSF) Controller Operation. 93

117 Start f DPWM f DPWM steady Obtain the value of error signal V ( n) error No V ( n) V error thr Yes fdpwm ( n) fdpwm steady No V ( n) V error thr Yes fdpwm ( n) fdpwm steady Verror ( n) fdpwm ( n) fdpwm steady Verror ( n) (b) Figure. 5.6: Flowchart for the adaptive switching frequency controller DVSF II Figure. 5.7 shows the theoretical waveforms that illustrate the proposed adaptive switching frequency controller operation. The controller observes the value of V error which is a measure of output voltage deviation from a desired reference voltage as shown in Figure When V error is outside a small window (defined by a threshold value, V thr ) around zero as a result of transient, the value of f DPWM is increased abruptly to a large value ( f DPWM max ) or a small value 94

118 ( f DPWM min ) depending on whether the value of V error is positive (e.g. under load step-up transient) or negative (e.g. under load step-down transient), respectively. This provides the necessary duty cycle variation to drive the output voltage back to its steady state value faster and with less deviation. The controller then observes the value of V error and finds the peak value of V error ( V error peak ) and the time instant this value is reached. T DPWM max T DPWM steady T ( ) DPWM n T DPWM min f DPWM max f DPWM steady f ( ) DPWM n f DPWM min V error peak 0 Verror ( n) V error peak Vout ( n) V out peak Output Voltage V out peak I o max Output Current I o min Figure. 5.7: Illustration of the adaptive switching frequency controller operation. 95

119 Start fdpwm fdpwm steady Obtain the value of error signal V ( n) error Yes V ( n) V error thr No fdpwm fdpwm steady Yes Verror ( n) 0 No Yes V ( n) V ( n 1) error error No Yes V ( n 1) V ( n) error error No fdpwm fdpwm max Verror peak Verror ( n) f f DPWM DPWM steady V V error error ( n). peak ( f f ) DPWM max DPWM steady fdpwm fdpwm min Verror peak Verror ( n) f f DPWM DPWM steady V V error error ( n). peak ( f f ) DPWM steady DPWM min V ( n 1) V ( n) error error Figure. 5.8: Dynamic Digital Variable Switching Frequency Controller Flowchart. The value of V error peak is used to vary the value of f DPWM gradually towards its steady-state value ( f DPWM steady ) as given by Eq. (5.4). T DPWM steady, T DPWM min and T DPWM max are the time periods corresponding to f DPWM steady, f DPWM max and f DPWM min, respectively. Figure. 5.8 shows the controller flowchart for the implementation of adaptive switching frequency controller law. It should be noted that the value of V error peak changes for different values and types of transients and hence the proposed control law adapts to different transient types and magnitudes. This improves the dynamic performance of converter for different magnitudes and types of transients. 96

120 f if 0 V ( n) V DPWM steady error thr f if V ( n) 0 and V ( n) V ( n 1) DPWM max error error error Verror ( n) fdpwm steady ( fdpwm max fdpwm steady ) V error peak f ( n) if V ( n) 0 and V ( n) V ( n 1) DPWM error error error (5.4) f if V ( n) 0 and V ( n) V ( n 1) DPWM min error error error Verror ( n) fdpwm steady ( fdpwm steady fdpwm min ) V error peak if V ( n) 0 and V ( n) V ( n 1) error error error 5.4. Theoretical Analysis If V peaka is the peak voltage, T A is the time period of the ramp signal and V ca is the value of compensated error signal, as illustrated in Figure. 5.2(b) ( V ca V ), then the duty ratio is given c by Eq. (4.5). D A V V ca peaka (5.5) In the case of constant frequency DPWM, with T A1 and V peaka1 as the time period and peak value of ramp signal, respectively. If V ca is the change in compensated error signal value, then the new duty cycle due to the change in compensated error signal is given by Eq. (5.6) D D A1 A1 V V ca1 ca1 V peaka1 (5.6) The relative change in duty cycle is given by Eq. (5.7) 97

121 D D A1 V V ca1 A1 ca1 (5.7) Similarly, consider the DVSF case. Let the change in the time period be given by T T k V, and the change in peak value as a result of this is given by A2 A1 V V k V, where V is the deviation in output voltage relative to reference peaka2 peaka1 1 voltage ( V ref V out ). k and k 1 are constants that determine the change in the time period and peak value of ramp signal, respectively. Therefore, the change in duty cycle is given by Eq. (5.8) D D A2 A2 VcA1 VcA1 V k V peaka1 1 (5.8) The relative change in duty cycle is given by Eq. (5.9) D V 2 ca1 VpeakA 1 k A 1 VcA 1 V D V ( V k V ) A2 ca1 peaka1 1 V V V V k V ca1 VpeakA 1 k1 V ca1 VcA 1 ca1 peaka1 1 (5.9) V DA 1 D V k V ca1 VpeakA 1 k1 V VcA 1 A1 peaka1 1 V Numerator Denominator V k V V k V Numerator Denominator ca1 peaka1 1 peaka1 1 VcA 1 V V k V V 0, since k 0 1 ca1 ca1 1 VcA1 VcA1 98

122 D D D D A2 A1 A2 A1 (5.10) From Eq. (5.10), it can be observed that the relative change in the duty cycle is more in the case of Variable Switching Frequency compared to constant switching frequency. In other words, the deviation in error signal required to bring about the same change in duty cycle value is less in case of Variable Switching Frequency Case, compared to the Constant Switching Frequency case. Hence, the dynamic performance is improved with the implementation of Variable Switching Frequency Experimantal Prototype Results A proof of concept experimental prototype is developed in the laboratory in order to verify the proposed dynamic switching frequency variation control. The prototype is a single-phase DC-DC buck converter with a nominal input of 10V and a nominal output voltage of 1.5V. The power stage output filter capacitance is 1mF and the output power inductor value is 440nH. The steady-state switching frequency is 342KHz. The controller and the control law are implemented using an FPGA (Field Programmable Gate Array) Altera Cyclone II EP2C35F672C DVSF I The experimental results with DVSF I controller are shown in Figure 5.9 and Figure Figure. 5.9(a) shows the variation of output voltage during a 5A to 0A step-down load transient with a constant switching frequency. Figure. 5.9(b) shows the response during the same load conditions when using the DVSF I controller. Figure. 5.10(a) shows the variation of output voltage during a 0A to 5A step-up load transient with a constant switching frequency. 99

123 Figure 5.8(b) shows the response during the same load conditions when using the DVSF I controller. 70mV 5A (a) 50mV 5A (b) Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div., 50µs/div.). Figure. 5.9: Experimental results of the prototype with zoomed in view under dynamic load stepdown transient of 5A-0A (a) with fixed frequency DPWM and (b) with variable frequency DPWM. It can be observed from the experimental results of Figure. 5.9 and Figure that the DVSF I control results in dynamic performance improvement. For this particular design 100

124 example, there is an improvement of 8.5mV (about 13%), during step up load transients and an improvement of 19.5 mv (about 27%), during step down load transient. 70mV 5A (a) 63mV 5A (b) Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div., 50µs/div.). Figure. 5.10: Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 0A-5A (a) with fixed frequency DPWM and (b) with variable frequency DPWM. 101

125 DVSF II The experimental results for the DVSF II controller are shown in Figure and Figure Figure. 5.11(a) shows the output voltage response during a 5A to 0A load step-down transient without the DVSF II controller being activated while Figure. 5.11(b) shows the response under the same load conditions when the DVSF II controller is activated. Figure shows similar results under 0A to 5A load step-up transient. 70mV 5A (a) 50mV 5A (b) Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div., 50µs/div.). Figure. 5.11: Experimental results of the prototype with zoomed in view under dynamic load step-down transient of 5A-0A (a) with fixed frequency DPWM and (b) with adaptive frequency DPWM. 102

126 It can be observed from the experimental results of Figure and Figure that the DVSF II control law results in dynamic performance improvement. For this particular design example, there is an improvement of 14 mv (about 22%) during load step-up transient, and an improvement of 20mV (about 27%), during load step-down load transient. 70mV 5A (a) 60mV 5A (b) Top Trace: Output Voltage (50mV/div, 50µs/div.) and Bottom Trace: Inductor Current (5A/div., 50µs/div.). Figure. 5.12: Experimental results of the prototype with zoomed in view under dynamic load step-up transient of 0A-5A (a) with fixed frequency DPWM and (b) with adaptive frequency DPWM. 103