E Typical Application and Component Selection AN 0179 Jan 25, 2017

Transcription

1 1 Typical Application and Component Selection 1.1 Step-down Converter and Control System Understanding buck converter and control scheme is essential for proper dimensioning of external components. E is designed for a step-down converter with PI (Proportional-Integral)-controller in a voltage regulation loop (Figure 1). Output voltage error is converted to current by the GM-OTA and fed to pin CMP. Transconductance together with form the proportional part and therefore the important part of loop gain. C CMP1 adds the integral part of regulation: A permanent error voltage at output VBUS will cause a continuous voltage change at pin CMP and change PWM until output voltage is corrected. The main disadvantage of this regulation, the direct modulation of V VBUS by V SW is almost completely suppressed by a feedforward correction of the PWM-ramp, which directly corrects the duty cycle with 1/V SW. VBAT SW CIN PWM Comp VRAMP LX VBUS BUS CMP - GM OTA + REF D1 RCMP RESR CCMP2 CCMP1 E CBUS Figure 1. E Regulator Concept The output filter, consisting of and C BUS has the capability to shift the signal s phase up to 180 (Figure 2, x=1000: no relevant R ESR ). This is critical in combination with the feedback regulation, which can turn from negative to positive feedback, resulting in oscillations. This behaviour cannot be compensated by the PI-regulator so it must be limited from the beginning. Phase shift can systematically be reduced by equivalent series resistance (ESR) of the capacitance. It can be proven, that the output filter s phase shift is mainly depending on the relation of low pass time constant R ESR *C BUS and resonant time constant sqrt( *C BUS ), which shall be called x here: R ESR should be chosen carefully or even intentionally be added to design. R ESR will mean the effective sum of additional resistor, parasitic resistance of PCB and capacitor s ESR. They all can be strongly depending on temperature, ageing, voltage or frequency. Phase shift over frequency with different R ESR is shown in Figure 2. 1/7

2 Figure 2. R ESR dependent amplitude and phase response, L=10µH, C=47µF With the ESR requirements for stability, of course the final voltage ripple due to switched input signal is influenced. Output voltage ripple is the combination of voltage drop at R ESR caused by the AC part of output current and the changing charge on C BUS. The charging/discharging effect can be neglected, if the cut-off frequency resulting from R ESR and C BUS is significantly lower than the SMPS switching frequency. This is always true here because cut-off frequency must be close to -C BUS frequency and both should be one decade below switching frequency to achieve acceptable filter characteristics. So voltage ripple can be written as: I L R ESR This has to be taken into account when stability and voltage ripple have to be balanced, but first of all the inductance should be selected. 1.2 Inductor Selection and Output Current Limitation Settings Inductor selection has an important influence on costs and performance. The asynchronous step-down converter knows two modes of operation: continuous conduction mode (CCM), when current flows through the inductor without interruption and discontinuous conduction mode (DCM), when inductor current reaches zero during SMPS off-time. This is normally associated with excessive ringing at LX because of the node s high impedance and transfer function changes due to the additional open state of the power stage. Furthermore pulse skipping can occur due to minimum on-time t ON,MIN of the power stage, which changes EMI in a hardly predictable manner. If possible, DCM should be avoided at all, so load current should not fall below critical current: I CR = I L 2 (V SW ) 2V SW f SW Operating frequency of course influences current ripple and therefore inductor size. The minimum and maximum current requirements should be known from application, so inductance value can be calculated like: (V SW ) I L V SW f SW 2/7

3 In the following tables, the initial values are indicated for the choke. These inductance values should be used for the first system design of the E as a function of the switching frequency and the required output current limit. This provides a matrix that should be sufficient for a first, basic dimensioning. The calculations are based on a typical input voltage for automotive applications of 13V. The calculated values are rounded to standard values and takes into account a tolerance of 20% of the choke. The term ΔIL represents the output current ripple in relation to the programmed current limit. Inductors saturation current should be greater than current limit and DC resistance must be taken into account for efficiency reasons. Furthermore I RMS must be considered for thermal system design to keep maximum ratings of chosen inductor. Table 1. Recommended Inductance Value at 250kHz Switching Frequency Table 2. Recommended Inductance Value at 500kHz Switching Frequency Table 3. Recommended Inductance Value at 1MHz Switching Frequency Table 4. Recommended Inductance Value at 2MHz Switching Frequency Output Capacitor Selection The stated ratio x from 1.1 Step-down Converter and Control System should be chosen not greater than 4 under worst case condition. With the known inductor from 1.2 Inductor Selection and Output Current Limitation Settings, minimum R ESR should be: R ESR 1 4 C BUS C BUS must be chosen suitably for the application. USB Specification Revision 2.0 for example demands a minimum VBUS to capacitance of 120µF. Small capacity leads to increasing demands on ESR, which finally results in higher output voltage ripple as stated before. 3/7

4 1.4 Loop Compensation The typical recommended compensation network ( =10k, C CMP1 =6.8nF, C CMP2 =33pF) results in a frequency response as to be seen in Figure 3. The choice of defines the proportional part of regulation and therefore part of the loop gain after integral part has decayed. The total loop gain for this frequency is: A= V SW V RAMP A FB g m V RAMP is the internal ramp s peak-to-peak voltage, which is ~1V at V SW =13V and center frequency. It is compared to pin CMP and creates the duty cycle. The V SW -based half bridge works as an additional gain after that. Due to the feed-forward correction this ratio V SW /V RAMP is nearly constant over V SW. A FB is the internal voltage divider, which is 0.24, g m =1.8mS describes the error amplifiers transconductance. Figure 3. Frequency response of OTA and compensation network Design goal is now, to damp this gain until critical phase shift and at least one decade below switching frequency to 0dB. Otherwise the regulator would recognise every switching event as disturbance of regulation loop. As to be seen in Figure 2, output filter s gain decays with 40dB/decade without influence of R ESR and with 20dB/decade later. This should be described with the following approximation: or with medium damping factor of 1.5: V SW V RAMP A FB g m( f SW 10 f LC) 175 ( f SW CBUS 10 ) 4/7 [1..2]

5 Furthermore it is important, that phase shift of integral part has decayed until LC phase shift of output filter begins. With the chosen this leads to the design constraint: C CMP1 C BUS C CMP2 is only added to reduce influence of switching frequency on regulation or more precisely on pin CMP. Since the OTA output has high-impedance, C CMP2 and form another pole at high frequency. It should be clearly beyond the transition frequency, where loop gain reaches 0dB and below the switching frequency, for example: C CMP f SW 1.5 Typical Applications and Characteristics Some application examples will be presented here. They are simulated for a phase margin >50 and gain margin >10dB at normal operation. Due to the voltage regulation scheme with supply forward correction, there is no significant influence of V VBAT on loop stability. f SW C BUS R ESR * C CMP1 C CMP2 ΔI L Δ f T 1a 2M 15µ 120µ 25m+47m 6.8n 10k 33p 0.1A 10m 60k 1b 2M 15µ 120µ 25m+47m 1n 47k 4.7p 0.1A 10m 280k 2 500k 10µ 47µ 25m+100m 33n 3.3k 220p 0.6A 80m 44k 3 500k 10µ 220µ 10m+33m 4.7n 10k 100p 0.6A 30m 56k 4 2M 4.7µ 47µ 25m+47m 1.5n 12k 22p 0.3A 30m 210k * R ESR includes capacitor s ESR, additional resistor and parasitics 1a is the standard setting for evaluation board which is a little bit slower in reaction but stable even at different frequencies and with many external devices. 1b is optimized for quick regulation but it is more sensitive to parasitics and parameter variations and drifts. Detailed measurements and verifications are mandatory. If phase- and gain-margin are non-satisfying, the following options improve stability followed by the main drawback: - increase additional R ESR (output voltage ripple will increase) - decrease (loop gain and therefore regulation behaviour will reduce) - increase C CMP1 (integral regulation will be slower) - decrease C CMP2 (sensitivity to pin CMP increases) 1.6 Stability Measurement The component selection guidelines can only be the starting point for an individually optimized and verified SMPS design. It is strongly recommended to measure gain and phase margin under different operating conditions in complete application environment. The recommended calculations show a strong dependence on parasitic elements of the PCB. Furthermore temperature and ageing of the components must be reviewed. If Jumper J7 of Elmos E Evaluation Kit, Power Board V2.0, is opened, there is a 22Ohm resistor within the feedback path, which is suitable for voltage injection stability measurement. 5/7

6 VBAT SW C IN PWM Comp VRAMP LX L1 VBUS RCMP CMP - GM OTA + REF E C CMP2 C CMP1 C BUS BUS D1 ACIN RFB ACOUT RESR Figure 4. E Loop Stability Measurement Setup Figure 5 shows the in-circuit measurement of the E Evaluation Kit, with an PSM3750 Frequency Response Analyzer from N4L. The phase shifting effect at 200kHz can be traced back to the ferrite output filter on evaluation board. This illustrates, that also the load conditions like other buffer caps can shift phase and must be taken into account to verify system stability. Figure 5. Gain and phase response for E Power Board V2.0, measured with PSM3750, f SW =2MHz, V VBAT =12V, I LOAD =1A 6/7

7 Usage Restrictions Elmos Semiconductor AG provide the E Demonstration Board simply and solely for IC evaluation purposes in laboratory. The Kit or any part of the Kit must not be used for other purposes or within non laboratory environments. Especially the use or the integration in production systems, appliances or other installations is prohibited. The pcb s are delivered to customer are for the temporary purpose of testing, evaluation and development of the Elmos IC s only. Elmos will not assume any liability for additional applications of the pcb. Disclaimer Elmos Semiconductor AG shall not be liable for any damages arising out of defects resulting from (1) delivered hardware or software, (2) non observance of instructions contained in this document, or (3) misuse, abuse, use under abnormal conditions or alteration by anyone other than Elmos Semiconductor AG. To the extend permitted by law Elmos Semiconductor AG hereby expressively disclaims and user expressively waives any and all warranties of merchantability and of fitness for a particular purpose, statutory warranty of non-infringement and any other warranty or product liability that may arise by reason of usage of trade, custom or course of dealing. Elmos Semiconductor AG Headquarters Heinrich-Hertz-Str Dortmund Germany Phone + 49 (0) Fax + 49 (0) sales-germany@elmos.com Note Elmos Semiconductor AG (below Elmos) reserves the right to make changes to the product contained in this publication without notice. Elmos assumes no responsibility for the use of any circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies. Elmos does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications. Copyright 2017 Elmos Reproduction, in part or whole, without the prior written consent of Elmos, is prohibited. 7/7