For Peer Review IEEE-TPEL. Proximate Time-Optimal Digital Control for DC-DC Converters. IEEE Transactions on Power Electronics

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1 Proximate Time-Optimal Digital Control for DC-DC Converters Journal: IEEE Transactions on Power Electronics Manuscript ID: Manuscript Type: Date Submitted by the Author: TPEL--- Regular Paper -Jul- Complete List of Authors: Yousefzadeh, Vahid; University of CO, ECE Babazadeh, Amir; CU Boulder, Elec. Eng. Ramachandran, Bhaskar; University of Colorado Boulder, Electrical Alarcon, Eduard; Technical University of Catalunya, Electronics Engineering Pao, Lucy; University of Colorado, ECE Department Maksimovic, Dragan; University of Colorado at Boulder, Department of Electrical and Computer Engineering Keywords: DC-DC power conversion, Digital control, Time optimal control, Pulse width modulated power converters

2 Page of IEEE-TPEL Proximate Time-Optimal Digital Control for DC-DC Converters Vahid Yousefzadeh, Amir Babazadeh, Bhaskar Ramachandran, Eduard Alarcon, Lucy Pao and Dragan Maksimovic Abstract- This paper introduces an approach to near time-optimal control in DC-DC converters. The proposed proximate time-optimal digital (PTOD) controller is a combination of a constantfrequency PWM (pulse-width modulation) controller employing a linear PID compensator close to a reference point, and a linear or nonlinear switching surface controller (SSC) away from the reference, together with a smooth transition between the two. A hybrid capacitor current estimator enables switching surface evaluation and eliminates the need for current sensing. The SSC, which is implemented as a small Verilog HDL module, can be easily added to an existing digital PWM controller to construct the PTOD controller. In steady state, the converter operates at constant switching frequency. Simulation and experimental results are shown for a. V-to-. V, A synchronous buck converter. Index terms: DC-DC converters, digital control, time-optimal control, switching surface control, boundary control An earlier version of this paper has been presented at IEEE PESC. Corresponding author: Dragan Maksimovic Colorado Power Electronics Center ECE Department UCB University of Colorado Boulder, CO - maksimov@colorado.edu Vahid Yousefzadeh is with Texas Instruments, Digital Power Amir Babazadeh, Bhaskar Ramachandran, Lucy Pao and Dragan Maksimovic are with ECE Department, University of Colorado at Boulder Eduard Alarcon is with Dept. of Electronic Engineering, Technical University of Catalunya, Barcelona, Spain

3 Page of I. INTRODUCTION In the field of control of switched-mode DC-DC power converters, such as the synchronous buck voltage regulator in Fig., most commonly adopted are standard frequency domain design techniques based on approximate linear time-invariant averaged small-signal models [, ]. Starting with the seminal work in [], it has been recognized that directly taking into account the switching nature of the power stage, and operating with large-signal instantaneous state variables to provide the on-off control action accordingly, can result in improved dynamic responses. The switching surface control [] and related approaches have also been designated as boundary or geometric control []. One case of special interest of the switching surface control results in minimum-time responses, as in the example waveforms shown in Fig. (a). By taking into account the converter state trajectories in the two possible switched states, a switching surface can be derived that naturally provides an on/off sequence that results in the fastest, i.e., time-optimal rejection of large-signal disturbances, as illustrated in the state diagram of Fig. (b), which corresponds to the waveforms in Fig. (a). Using converter trajectories as switching surfaces for the case of infinite load is discussed in [], whereas in [], given the complexity of the theoretical switching surface, the behavior of different approximations is explored. The nonlinear state-feedback that provides time-optimal control can also be derived from an energy transfer approach, as discussed in [] and more recently in []. With the advent of recent applications with more stringent specifications in terms of regulator settling time, various approximations to time-optimal control have recently been proposed, e.g., in [-], where time-optimal control is described in terms of + V g Q Q c c v s Controller Figure : Synchronous buck DC-DC voltage regulator. Prototype example: V g =. V, L = µh, C = µf, switching frequency f s = KHz, V ref =. V, I load = - A. i L L + v out _ i c C load V ref +

4 Page of IEEE-TPEL mv -mv -mv -mv v out -V ref V -mv us us us us us us (b) A i c t on -A -A -i t on -A us us us us us us c us us us us us us A A A -A -A i c i (a) -i v out -V ref -A -mv -mv mv mv Figure. (a) Waveforms illustrating time-optimal response to a -A step load transient in the converter of Fig.. (b) State plane diagram for the -A step load transient, a linear switching surface (a) and a nonlinear switching surface (b). t off (a) (b) (b) i (a) boundary control and revisited for the buck converter. Reference [] reexamines the switching-surface time-optimal control and derives analytically equations for the optimal case, similarly to []. Recent works in [-] provide a comprehensive account of geometric control principles, including limits of time-optimal control for switching converters. In the field of general control theory, the fundamentals of time-optimal control, which are directly related to the use of Pontryagin's principle, have been studied extensively []. Unfortunately, it has been recognized that ideal timeoptimal control may be impractical because of the sensitivity to parameter variations, and unmodeled dynamics []. To address this issue, a concept of proximate time-optimal (PTO) control has been proposed [-] and successfully applied in, for example, disk-drive head positioning. The main

5 Page of underlying idea considers saturating the control action to facilitate near-time-optimal response to large-signal disturbances and smoothly switching the controller to a standard continuous-time control action in the vicinity of steady state. By combining a time-optimal and a linear controller, it is possible to achieve the favorable properties of both types, namely, fast large-signal transient responses, precise control in steady state, and overall robustness against parameter variations and unmodeled dynamics. The approach presented in this paper is inspired by the PTO ideas and results. In addition to robustness issues addressed in control theory, a disadvantage that has hitherto precluded widespread use of time-optimal control for DC-DC converters has to do with controller implementation difficulties. In analog controller implementations, the challenges of implementing a nonlinear control law are notable. For example, current-mode circuit techniques to implement squaring functions are proposed in [], whereas fuzzy approximation techniques are used to synthesize the multi-input nonlinear switching surface in []. With advances in digital control for high-frequency switched-mode converters (e.g. [, ]), new possibilities arise to consider practical realizations of more advanced control approaches. In particular, Section II briefly reviews previously reported approaches to digital implementation of near time-optimal or nonlinear control for DC-DC converters [-]. Following this review, we argue that proximate time-optimal digital (PTOD) control proposed in this paper, based on a combination of linear or nonlinear switching surface and standard linear (e.g. PID) control can have advantages in DC-DC voltage regulators where arbitrary load disturbances and realistic component tolerances must be taken into account. An approach to capacitor current estimation, which is a key component of the switching surface controller described in this paper, is introduced in Section III. Section IV describes the complete PTOD controller. Simulation and experimental results for a.v-to-.v, A synchronous buck point-of-load converter with the PTOD controller are described in Section V. Sections VI summarizes the conclusions. II. DIGITAL TIME-OPTIMAL CONTROL IMPLEMENTATION APPROACHES In this section, we use the example in Figs. and to review and discuss approaches to digital realization of near-time optimal control for DC-DC converters.

6 Page of IEEE-TPEL A. Programmed on/off times Assuming a specific type of load transient (e.g. a step in load), the times t on, t on and t off corresponding to time-optimal response can be found in terms of operating conditions and circuit parameter values using the output capacitor charge balance approach [-]. This approach requires implementation of relatively complex computations and also relies on precise real-time inductor current sensing. A combined linear PID and a nonlinear controller with pre-computed on/off times stored in a look-up-table for a limited set of possible step load transients is described in []. The approach presented in [] also combines a linear PID controller with a near-timeoptimal controller in transients. Based on detecting the valley (or peak) in the output voltage waveform, the on/off control is executed with the times t on, t off stored in a look-up table. This approach has advantages of requiring no current sensing, and having relatively simple realization based on continuous-time DSP concept. B. Switching surface As opposed to computing or programming the on/off times to achieve fast large-signal transient response for a specific type of load transient, a switching surface controller (SSC) is based on sensing (or estimating) converter states x. The switch state, i.e., the switch control signal c is then determined from if σ( x) < c = () if σ( x) > where σ(x) = defines the switching surface: the on-to-off switching occurs at the time the converter state trajectory crosses the switching surface. For the case when the states are the capacitor voltage and the capacitor current, Fig. (b) shows examples of a linear switching surface and a non-linear switching surface. As discussed in the introductory section, it has been shown that the switching surface can be designed to enable near-time-optimal responses for the important class of step load transients. Even more importantly, a feedback mechanism is applied at all times, and the controller based on the same switching surface can be shown to result in stable, well-behaved dynamic response in general. This advantage is very significant in DC-DC converter applications where the nature of load transients is generally not known in advance. The main difficulty associated with implementing () in a digital controller is related to sensing or estimation of the converter states. While the output voltage sensing is necessary in any

7 Page of controller realization, it is desirable to consider practical estimation methods to remove the need for precision current sensing. In particular, capacitor current sensing is completely impractical in many cases. The next section introduces an approach to capacitor current estimation. III. CAPACITOR CURRENT ESTIMATION We consider the case when the output voltage error e[n] = V ref v out [n] is sampled by an A/D converter having a least significant bit (LSB) resolution q A/D, at the rate f sample = N os f s, where f s is the switching frequency and N os is the oversampling rate. A very basic finite-difference estimator for the capacitor current is given by Taking the Z-transform of () results in i C icd [ n] = ( e[ n] e[ n ] ) () T sample ( z ) e( z) H ( z) e( z) C ( z) = e T cd = sample jωt The estimation filter transfer function H ( sample e e ) can be written as: jωtsample jωtsample / H ( e ) ( jωc) e sinc( ωt / ) e sample. () =. () We note that at relatively low frequencies H e closely approximates the ideal analog derivative action (jωc) except for a delay of T sample /, which can be neglected if the oversampling rate is high. Fig. (b) shows an example of successful capacitor current estimation using (), assuming N os =, and a very high resolution A/D, q A/D =. Unfortunately, the estimator () is highly susceptible to switching noise in the sensed output voltage, and to quantization errors, as illustrated in Fig. (c) for q A/D = mv: the effective resolution in i cd is very low. Taking advantage of the oversampling, low-pass filtering of i cd can partially alleviate the problem. For example, applying a moving-average filter of order k to i cd in () yields a filtered finitedifference estimator: i k ( z ) e( z) H ( z) e( z) k i C ( z) = z icd ( z) = ek. () k i= ktsample cf = Similar to (), the estimation filter transfer function H jωt ( sample ) ek e can be written as:

8 Page of IEEE-TPEL H ek jωtsample jωktsample / ( e ) ( jωc) e sinc( ωkt / ) = () which shows that () approximates ideal analog differentiation, but with a delay of kt sample /. In digital hardware, the filtered finite-difference estimator is executed as: i cf sample C [ n] = ( e[ n] e[ n k] ) () kt sample One may note that () reduces to () for k =. Fig. (d) illustrates the estimation performance of (). Although an improvement in effective resolution by a factor of k can be observed, a realization of () with the capacitor current estimator () would still be significantly affected by the quantization errors, especially around zero (i.e. around the switching), and by the larger delay of kt sample / due to moving-average filtering. Let us consider an integral estimator of the ac component of the inductor current as an alternative approach. Since v out V ref, in the buck converter of Fig., the inductor current slopes are m (V g V ref )/L and m V ref /L in the two switch states, c = and c =, respectively. Since i c = i L i load, assuming a known initial condition, an integral current estimator can be constructed as: mt sample if c = ici [ n] = ici[ n ] + () mtsample if c = which is not subject to quantization errors. Unfortunately, this approach is not suitable for detecting fast changes in the capacitor current. A hybrid estimator i ch, which is a combination of () and () is proposed to overcome these difficulties: we start with i ch [n] = i cf [n]. Then, taking into account the delay of kt sample / in the estimate (), an initial value for the integral estimator () is found as: kmt sample / if c = ici = icf + () kmtsample / if c = at the point where i cf in () reaches a peak value, e.g., after a fast load transient.

9 Page of (a) (b) (c) (d) (e) mv -mv -mv -mv v out -V ref -mv us us us us us us us us us us A i cd -A i q ad = c k = -A us us us us us us us us us us A A -A i cd i c q ad = mv k = -A us us us us us us us us us us A i cf -A i q c ad = mv k = -A us us us us us us us us us us A i ch -A q i ad = mv c k = -A us us us us us us us us us us Figure (a) Output voltage waveform during a step-load-transient; (b-e) capacitor current i c, and capacitor current estimates i cd, i cf, i ch.

10 Page of IEEE-TPEL From this point on, the integral estimator () is employed, i ch [n] = i ci [n]. To account for arbitrary load disturbances, a reset of the initial value in () can be performed based on () whenever a large (e.g. more than LSB) difference between i cf and i ch is detected. Fig. (e) shows an example of the hybrid estimator performance. Importantly, a high-resolution capacitor current estimate is available around the points where the state trajectory is crossing the switching surface as required in the implementation of the control law (). + V g Q Q c c Switching surface controller (SSC) f sample = N os f s c DPWM f s DPWM v s c DPWM Constant-frequency PWM controller d i L PID IV. PROXIMATE TIME-OPTIMAL DIGITAL CONTROLLER Fig. shows the complete PTOD controller around a synchronous buck converter. The window-flash A/D has q A/D LSB resolution and a total of bins around the reference. The linear PID compensator, and the constant-frequency digital pulse-width modulator (DPWM) are the same as in [, ]. The PID controller sampling frequency is the same as the converter switching frequency f s. The switching surface controller (SSC) takes samples of the voltage error L e + v out _ q ad i c C load V ref + Window-flash A/D Figure. Proximate time-optimal digital controller for a synchronous buck converter. Experimental prototype parameters: V g =. V, L = µh, C = µf (ceramic), R esr = mω, V ref =. V, f s = khz, I load = -to- A, q A/D = mv, N os =, k =.

11 Page of ON OFF λi ch, σ σ > λi ch, σ c = c = e > q A/D, σ < λi cf < q A/D PID ON λi ch, σ λi cf c = σ > c = c DPWM e < q A/D, λi cf > q A/D OFF λi ch, σ σ < c = Figure State machine diagram of the switching surface controller. e at the oversampling rate N os f s. The SSC is realized as a state machine shown in Fig.. In the PID state, the SSC simply passes the switch control signal from the PID controller to the output, c = c DPWM. The controller moves to ON (or OFF) transient state when the voltage error and the current estimate i cf exceed a threshold (equal to one LSB value in the diagram of Fig. ). In the transient ON/OFF states, the hybrid capacitor current estimator i ch described in Section III is employed, and the switching surface is evaluated. For example, a linear switching surface is given by σ [ n] = e[ n] + λi [ n] () where λ is a slope parameter. The state transition conditions are shown in Fig.. It is of interest to note that the SSC simply passes on the switch control signal c DPWM from the PID controller, or enforces c = (in ON states) or c = (in OFF states). The PID controller continues to run at all times, with no modifications required to facilitate smooth transitions. Simulation and experimental results are discussed in the next section. ch

12 Page of IEEE-TPEL V. SIMULATION AND EXPERIMENTAL RESULTS Parameters for the experimental synchronous buck converter with the PTOD controller are shown in Fig.. The slope parameter in the linear switching surface () is such that λc/(kt sample ), so that no multipliers or look-up tables are required in the implementation. The SSC state machine (Fig. ) has been realized in Verilog HDL, resulting in an equivalent gate count of only gates on a Xilinx Virtex IV FPGA. It is worth noting that this very small SSC module can be added to an existing digital PWM controller with no other modifications. We also note that the PTOD controller is intended for custom IC implementations (such as []), whereas the FPGA is used as a convenient development and verification platform. In the experimental prototype, the switching frequency is f s = KHz, k =, and the SSC oversampling rate is N os =, which corresponds to the MHz system clock already present in the constant-frequency PWM digital controller realization with a PID compensator [, ]. Fig. compares performance of the standard PID controller (with the SSC module disabled) against the PTOD controller for three different step-load transients: -%, -% and - %. Significantly improved step-load transient responses can be observed in all three cases. Fig. shows the experimental waveforms collected by Xilinx Chipscope (an embedded FPGA logic analyzer) for the case of -to- A step load transient. The normalized switching-surface waveform σ/q A/D indicates the state transitions according to the diagram in Fig..

13 Page of Figure : Experimental step-load transient waveforms for the PID controller (left) and the PTOD controller (right). Top:.-A; middle: -A, bottom:.-a. The waveforms shown are, top-to-bottom: inductor current i L (A/div), ac coupled output voltage v out ( mv/div), switch-node voltage v s (V/div), and load control signal.

14 Page of IEEE-TPEL The SSC enters the ON state when the voltage error e equals q A/D. In the ON state, the switch control signal is on, c =, and the switching surface σ is evaluated according to (). Transition to the OFF state occurs at the time σ crosses the threshold = q A/D. In the OFF state, c =. Finally, upon detection of the zero-crossing of σ, the controller moves back to the PID state, and the PID controller takes over the task of bringing the output voltage error to the zero-error bin of the A/D converter. Since sensing of the output voltage and evaluation of the switching surface occurs throughout the controller operation, the PTOD controller is capable of providing high performance dynamics under arbitrary load disturbances. The standard PWM controller with the linear PID compensator results in precision static voltage regulation and constant frequency steady-state operation. Since fast large-signal dynamics are handled by the SSC, the PID compensator can be designed conservatively, with large small-signal stability margins, and according to no-limit-cycling conditions in [, ]. - -e/q A/D - us us us us us λi c /q A/D - - us us us us us σ/ q A/D - PID ON OFF PID us us us us us c us us us us us Figure Experimental Chipscope waveforms collected from the FPGA controller prototype for the PTOD controller during a -to-a step load transient.

15 Page of Step-load transient TABLE I PEAK OUTPUT VOLTAGE DEVIATION V Ideal timeoptimal PTOD worstcase nominal An important issue, which deserves further theoretical and practical investigations, is the robustness of the PTOD controller in the presence of realistic power-stage component tolerances. Our initial results are reported in Table I, which summarizes simulated performance of the PTOD controller against parameter variations. The table compares the maximum voltage deviations V obtained with the ideal time-optimal controller, the PTOD controller with nominal power-stage parameters (L = µh, C = µf, R esr = mω), the PTOD controller with perturbed power-stage parameters (L = µh ±%, C = µf ±%, R esr = -to- mω), and the standard PID controller with the nominal parameters. The results show that the PTOD controller consistently results in high-performance responses, even based on the simple linear switching surface (). Further improvements can be expected by employing a nonlinear switching surface, adaptive adjustments of controller parameters including feed-forward compensation of the input voltage, or on-line system identification and parameter tuning (such as [-]), which will be addressed in future work. VI. CONCLUSIONS This paper introduces an approach to near time-optimal control in DC-DC converters using a simple digital controller realization. The proposed proximate time-optimal digital (PTOD) controller is a combination of a constant-frequency PWM controller employing linear PID compensator close to a reference point, and a linear or nonlinear switching surface controller (SSC) away from the reference, together with a smooth transition between the two modes. A key component of the SSC is a hybrid capacitor current estimator that enables effective switching PID nominal.- A mv mv mv mv - A mv mv mv mv.- A mv mv mv mv

16 Page of IEEE-TPEL surface evaluation even with a relatively low-resolution hardware, and eliminates the need for current sensing. The SSC, which is implemented as a Verilog HDL module, is very simple and small (less than gates). The SSC module can be easily added to an existing digital controller to construct the PTOD controller. In steady state, the converter operates at constant switching frequency. Simulation and experimental results are shown for a. V-to-. V, A synchronous buck converter. ACKNOWLEDGMENT This work has been sponsored through Colorado Power Electronics Center (CoPEC). E. Alarcón held a visiting position at CoPEC during summer with a grant provided by AGAUR, Generalitat de Catalunya. Partial funding by project TEC--C- from the Spanish MCYT and EU FEDER funds is acknowledged.

17 Page of REFERENCES [] R. D. Middlebrook, S. Cuk, A general unified approach to modeling switching-converter power stages, International Journal of Electronics, vol., no., pp. -, June. [] R. W. Erickson, D. Maksimovic, Fundamentals of Power Electronics, Springer,. [] W. Burns and T. Wilson, Analytic derivation and evaluation of a state-trajectory control law for DC- DC converters, in Proc. IEEE PESC,, pp. -. [] P. T. Krein, Elements of Power Electronics, Oxford University Press,. [] B. Jammes, J. C. Marpinard and L. Martinez-Salamero, Large-signal control of a buck converter based on time optimal control, in Proc. ECCTD,, pp. -. [] D. Biel, L. Martinez, J. Tenor, B. James and J. C. Marpinard, Optimum dynamic performance of a buck converter, in Proc.IEEE ISCAS, vol.,, pp.. [] A. Capel and D. O'Sullivan, Very high frequency regulator for space applications, in Proc. IEEE PESC, vol.,, pp. -. [] P. Gupta and A. Patra, Super-stable energy based switching control scheme for DC-DC buck converter circuits, in Proc. IEEE ISCAS, vol.,, pp. -. [] K. K. S. Leung and H. S. H. Chung, Derivation of a second-order switching surface in the boundary control of buck converters, IEEE Power Electronics Letters, vol., no., pp., June. [] K. S. Leung and H. S. H. Chung, A comparative study of the boundary control of buck converters using firstand second-order switching surfaces -Part I: Continuous conduction mode, in Proc. IEEE PESC,, pp.. [] K. S. Leung and H. S. H. Chung, A comparative study of the boundary control of buck converters using firstand second-order switching surfaces -Part II: Discontinuous conduction mode, in Proc. IEEE PESC,, pp.. [] M. Ordonez, M. T. Iqbal and J. E. Quaicoe, Selection of a curved switching surface for buck converters, IEEE Trans. Power Electronics, vol., no., pp., July. [] J. T. Mossoba and P. T. Krein, Exploration of deadbeat control for DC-DC converters as hybrid systems, in Proc. IEEE PESC, June, pp.. [] G. E. Pitel and P. T. Krein, Trajectory paths for DC-DC converters and limits to performance, in Proc. IEEE COMPEL,. [] P. T. Krein, Feasibility of geometric digital controls and augmentation for ultrafast DC-DC converter response, in Proc. IEEE COMPEL,, pp. -. [] M. Athans and P. Falb, Optimal Control: An Introduction to The Theory and Its Applications, McGraw-Hill, New York,. [] A. S. I. Zinober and A. T. Fuller, The sensitivity of nominally time-optimal control systems to parameter variation, Int. J. Contr., vol., no., pp. -,. [] W. S. Newman, Robust near time-optimal control, IEEE Trans. Automat. Contr., vol., no., pp., July.

18 Page of IEEE-TPEL [] L. Y. Pao, and G. F. Franklin, Proximate time-optimal control of third-order servomechanisms, IEEE Trans. Automat. Contr., vol., no., April, pp. -. [] L. Y. Pao and G. F. Franklin, The robustness of a proximate time-optimal controller, IEEE Trans. Automat. Contr., vol., no., pp. -, Sept.. [] C. La-orpacharapan and L.Y. Pao, Shaped time-optimal feedback control for disk-drive systems with backelectromotive force, IEEE Trans. Magnetics, vol., no., Part, pp., Jan.. [] E. Alarcón, D. Biel, F. Guinjoan, E. Fossas, E. Vidal and A. Poveda, Current-mode BiCMOS sliding-mode controller circuit for AC signal generation in switching power DC-DC converters, in Proc. IEEE MWSCAS, August. [] S. Gomáriz, E. Alarcón, J. A. Martínez, A. Poveda, J. Madrenas and F. Guinjoan, Minimum-time control of a buck converter by means of fuzzy logic approximation, in Proc. IEEE IECON', Aug. - Sept,, pp. -. [] B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, High-frequency digital PWM controller IC for DC-DC converters, IEEE Trans. Power Electronics, vol., no, part, pp. -, January. [] D. Maksimovic, R. Zane and R. Erickson, Impact of digital control in power electronics, IEEE International Symposium on Power Semiconductor Devices & ICs, pp. -, May. [] G. Feng, W. Eberle and Y. F. Liu, A new digital control algorithm to achieve optimal dynamic performance in DC-to-DC converters, in Proc. IEEE PESC, June, pp.. [] G. Feng, E. Meyer, Y. F. Liu, A new digital control algorithm to achieve optimal dynamic performance in DCto-DC converters, to appear in IEEE Trans. Power Electronics,. [] G. Feng, E. Meyer and Y. F. Liu, High performance digital control algorithms for DC-DC converters based on the principle of capacitor charge balance, in Proc. IEEE PESC, June. [] E. Meyer, G. Feng and Y. F. Liu, Novel digital controller improves dynamic response and simplifies design process of voltage regulator module, in Proc. IEEE APEC, pp. -. [] J. Quintero, A. Barrado, M. Sanz, A. Lazaro and E. Olias, Experimental validation of the advantages provided by linear-non-linear control in multi-phase VRM, in Proc. IEEE APEC, pp. -. [] A. Soto, P. Alou, J.A. Cobos, Nonlinear digital control breaks bandwidth limitations, in Proc. IEEE APEC. [] Z. Zhao, V. Smolyakov and A. Prodic, Continuous-time digital signal processing based controller for highfrequency DC-DC converters, in Proc. IEEE APEC, pp. -. [] H. Hu, V. Yousefzadeh and D. Maksimovic, Nonlinear control for improved dynamic response of digitallycontrolled DC-DC converters, in Proc. IEEE PESC, June. [] V. Yousefzadeh, T. Takayama and D. Maksimović, Hybrid DPWM with digital delay-locked loop, in Proc. IEEE COMPEL, June. [] A. V. Peterchev, S. R. Sanders, Quantization resolution and limit cycling in digitally controlled PWM converters, IEEE Trans. on Power Electronics, vol., no., pp., Jan..

19 Page of [] H. Peng, A. Prodic, E. Alarcon, D. Maksimovic, Modeling of quantization effects in digitally controlled DC DC converters, IEEE Trans. Power Electronics, vol., no., pp., Jan.. [] B. Miao, R. Zane, D. Maksimovic, System identification of power converters with digital control through cross-correlation methods, IEEE Trans. Power Electronics, vol., no., pp., Sept.. [] W. Stefanutti, P. Mattavelli, S. Saggini, M. Ghioni, Autotuning of digitally controlled DC DC converters based on relay feedback, IEEE Trans. Power Electronics, vol., no., pp., Jan.. [] S. Saggini, W. Stefanutti, E. Tedeschi, P. Mattavelli, Digital deadbeat control tuning for dc-dc converters using error correlation, to appear in IEEE Trans. Power Electronics,. [] M. Shirazi, L. Corradini, R. Zane, P. Mattavelli and D. Maksimović, Autotuning techniques for digitally controlled point-of-load converters with wide range of capacitive loads, in Proc. IEEE APEC.