Digital PWM/PFM Controller with Input Voltage Feed-Forward for Synchronous Buck Converters

Transcription

1 Digital PWM/PFM Controller with Input Voltage Feed-Forward for Synchronous Buck Converters Xu Zhang and Dragan Maksimovic Colorado Power Electronics Center ECE Department, University of Colorado, Boulder, CO {xzhang, Abstract- This paper describes a digital pulse-width modulation/pulse-frequency modulation (PWM/PFM) controller with input voltage feed-forward for synchronous buck DC-DC converters. The controller includes automatic PWM/PFM mode switching and effective synchronous operation with a minimum number of active components and without the need for current sensing in PFM mode of operation. Input-voltage feed-forward improves efficiency and dynamic performance over a wide range of input voltages. Controller parameters, including the PWM switching frequency, the PFM pulse period, and the mode transition point are programmable, which enables efficiency optimization. Experimental results are shown for a synchronous buck converter with 5-to-12 V input voltage, and 1.3 V, 0 10 A output. I. INTRODUCTION High efficiency over a very wide range of loads has long been a topic of interest for DC-DC converters in low-power battery-operated systems. Motivated by light-load energy savings and efficiency standards, this is now an increasingly important feature in a much broader range of DC-DC applications. In analog DC-DC controllers, well known approaches to improving light-load efficiency include techniques such as pulse frequency modulation (PFM) that effectively reduce the switching frequency in proportion to the load [1-7]. Such techniques are now widely available in multi-mode analog controllers (e.g. [8-11]) where the mode of operation (e.g., PWM or PFM) depends on the load. Digital multi-mode control techniques have recently received increased attention [13-23]. For example, it has been shown that custom digital multi-mode integrated circuits (ICs) can achieve very low light-load power consumption [12, 14, 15-17]. In addition, digital realizations open possibilities for further efficiency improvements through on-line efficiency optimization [21], or predictive control of segmented powerstages [22-23]. Objectives of this paper are to present a combination of several implementation techniques leading to practical realization of a digital PWM/PFM controller that includes: Effective synchronous rectifier control with minimum number of active components in PFM mode of operation, Automatic PWM/PFM mode switching, Input-voltage feed-forward to improve efficiency and dynamic performance over wide input voltage range, and Programmability of parameters to enable efficiency optimization Throughout the paper, experimental results are presented for a PWM/PFM controlled point-of-load synchronous buck converter shown in Fig. 1, with 5-12 V input voltage, 1.3 V output voltage, 0-10 A load current, and PWM switching frequency programmable in the range from 200 khz to 800 khz. The PWM/PFM controller architecture and the digital PFM control method are described in Section II. Mode switching is discussed in Section III. Section IV describes implementation of the input voltage feed-forward (IVFF). Experimental efficiency results are shown in Section V. Conclusions are presented in Section VI. II. DIGITA PWM/PFM CONTROER The PWM/PFM controller architecture is shown in Fig. 1 together with a prototype synchronous buck converter. Digital portion of the controller in Fig. 1 has been designed in Verilog hardware description language (HD). While the controller is intended for custom-ic implementation, the experimental results reported in the paper are obtained using an FPGA development platform. In constant-frequency PWM mode of operation, all controller components are active. The PWM portion of the controller architecture has been described in [24-27]. An 8- comparator window-flash A/D converter compares the output voltage to a reference and generates the digital error signal e[n]. The sampling rate is equal to the switching frequency f s. A PID compensator computes the duty-cycle command D[n]. An oscillator (HF clock) generates the system clock (25 MHz in the experimental prototype). It should be noted that very low-power digital oscillator techniques can be used to construct the HF clock block in custom IC realizations [12, 14, 15]. The 10-bit digital pulse-width modulator (DPWM), which is based on the hybrid architecture described in [28], generates the switch control signals with programmable dead times and the switching frequency f s set by the f s_command input. When the controller switches to PFM mode, the basic operation is conceptually the same as in many previously described analog PFM controllers [1-3, 8-10]: a single comparator stays on to monitor the output voltage. When the output capacitor voltage discharges to a reference threshold, a pulse is generated to replenish the charge. As a result, the PFM switching frequency is proportional to the load and the output voltage stays in regulation without the need for compensation in the PFM voltage control loop [1-3] /08/$ IEEE 523

2 i R V g Q 1 Q 2 v s P in Ref Syn D Q v out _ i c R esr C load P out P driver HF clock DPWM_enable PFM controller AD_comparator (31/2)V q DPWM f s_command fd[n] f Counter A/D D[n] PID e[n] 0 V q /2 -V q /2 -(31/2)V q Fig.1 Digital PWM/PFM controller for a synchronous buck converter. Experiment prototype parameters: V g = 5-12 V, V out = 1.3 V, load current: 0-10 A, = 1µH, C = 270µF, PWM switching frequency f s = KHz (programmable). High side and low side MOSFETs: PH4840s(NXP), driver: M5101(NSC). Zero-error SB of the output voltage A/D converter: 10 mv. Figs. 2 and 3 illustrate operation of the experimental prototype in PFM mode. During T on, the control MOSFET Q 1 is on. During T off, the synchronous rectifier Q 2 is on. The ontime (T on ) can be considered an efficiency optimization parameter. The optimum off-time (T off ) is such that the synchronous rectifier turns off at the zero crossing of the inductor current. In analog controllers, a high-speed analog comparator is commonly used to sense zero crossing of the inductor current and facilitate synchronous PFM operation [1, 3, 8], which increases the controller power consumption. In the digital controller of Fig. 1, a simpler approach is applied to control the synchronous rectifier without the need for inductor current sensing. In the synchronous buck converter, the ontime T on and the off-time T off are related through: ( V g out) out T V V on = Toff (1) Taking advantage of the fact the duty cycle command D in PWM mode can be easily stored indefinitely, the same dutycycle command D from PWM mode can be used to set the ontime and the off-time in PFM mode by noting that: ( V g out ) out DT V s = D ' T V s (2) with Ton = DT, and s T = D' T = (1 D) T. off s s Output Voltage Inductor Current T PFM High side drive T on T off ow side drive T on T PFM T off Fig.2 Experimental logic analyzer waveforms in PFM mode Fig.3 Experimental oscilloscope waveforms in PFM mode, T PFM = T on T off = 1.28 µs 524

3 Experimental timing waveforms collected by a logic analyzer are shown in Fig. 2. At the time the output voltage crosses a reference threshold, the comparator output (AD_comparator) starts the system clock (HFclock) and enables the DPWM to generate the control pulses of length T on = DT s, and T off = (1D)T s. This results in near-optimum synchronous PFM operation, as shown by the oscilloscope waveforms in Fig. 3, without the need for current sensing in PFM. In PFM mode of operation, only the highlighted blocks (PFM controller, HF clock, DPWM, and Counter A/D) are active during T on /T off pulse generation. For the remaining time in PFM, only a single A/D comparator (highlighted in Fig. 1) is active, and all other blocks are either shut down or idle, thus minimizing the PFM power consumption of the controller. Reusing the same DPWM hardware, the total PFM pulsewidth T PFM = T on T off = 1/f s_command is programmable by the same frequency command f s_command that sets the switching frequency f s in PWM mode of operation. It should be noted that f s_command does not have to be the same in PWM and PFM modes. The independent control of the switching frequency f s in PWM mode and the total pulse period T PFM in PFM mode further enables system efficiency and ripple trade-offs as discussed further in Section V. III. AUTOMATIC MODE SWITCHING At moderate and high loads, the controller operates in constant-frequency PWM mode. At light loads, the controller switches to PFM mode of operation. The PWM/PFM mode transition can be initiated by an external command. Alternatively, to simplify system operation, an automatic loaddependent mode switching is desirable. The PWM/PFM mode switching approach implemented in the digital controller of Fig. 1 is similar to the techniques described in [8-11]. In PWM mode, a single comparator sampled by a control signal Syn is used to detect load current and facilitate switching to the PFM mode. By timing of the sampling signal Syn, PWM-to-PFM mode switching can be initiated either by sensing the voltage drop v s across Q 2 during the synchronous rectifier on-time, thus indirectly sensing the inductor current level for setting a high-current transition point, or by sensing the switch-node voltage v s during the dead time, thus indirectly sensing the polarity of the inductor current, for setting a low-current transition point. The signal PFM_enable is activated to switch to PFM mode, which sets the PID error e[n] to zero, and shuts down PWM components of the controller. Voltage regulation in PFM is achieved as described in Section II: a T on /T off pulse is generated whenever the output voltage crosses a reference threshold as detected by a single active comparator. In PFM mode, as the load current increases, the frequency of the pulses increases. Ultimately, a single pulse is not sufficient to bring the output voltage above the reference threshold. When the number of consecutive PFM pulses exceeds a programmable value (3 in the experimental prototype), the controller switches back to PWM mode. This technique results in a PFM-to-PWM transition point close to Output Voltage [100 mv/div] (a) Output Voltage [100 mv/div] (b) Fig.4 Mode switching: (a) A load step from PFM to PWM; (b) A load step from PWM to PFM. the load where the inductor current in PWM mode stays positive at all times. Note that no additional sensing circuitry is needed to facilitate PFM-to-PWM mode switching. Experimental waveforms in Fig. 4 illustrate the mode switching for the case when the PWM switching frequency is f s = 400 khz, and the PFM pulse period is T PFM = 3.75 µs (1/T PFM = 265 khz). Fig. 4(a) shows PFM-to-PWM mode switching, while Fig. 4(b) illustrates PWM-to-PFM mode switching. The controller enters the PFM mode at the load where the inductor current in PWM is positive at all times. In both mode switching cases, the output voltage transient is determined by the PWM compensator design. The mode transition includes a hysteresis with respect to the load current, which is further discussed in Section V together with efficiency results. IV. INPUT VOTAGE FEED-FORWARD Benefits of input voltage feed-forward (IVFF) in PWM converters are well known [29-32], including improved rejection of input voltage disturbances, and improved dynamic 525

4 responses in the voltage control loop based on the fact that the loop gain becomes independent of the input voltage. Effective input voltage feed-forward is of interest for PFM operation as well. The PFM techniques described in Sections II and III operate well for a fixed input voltage V g, but not over a wide range of input voltages. For example, if V g changes during PFM operation, the T on and T off timing based on D stored in PWM mode becomes incorrect, which reduces efficiency. Furthermore, if constant T on /T off times are kept in the PFM mode, the output ripple increases significantly with the input voltage. In analog PWM controllers for buck converters, an effective IVFF is accomplished simply by adjusting the slope of a PWM ramp signal in proportion to the input voltage. A digital feed-forward implementation has been addressed in [33]. However, the approach described in [33] is best suited only for custom ICs operating at fixed switching frequency. S R V g S Vcon V cc C The IVFF proposed in this paper is shown in Fig. 1: the duty-cycle command D[n] from the PID compensator is multiplied by a feed-forward gain f to generate the duty-cycle command fd[n] for the DPWM. A simple, single-comparator counter A/D shown in Fig. 5 senses the input voltage and C f S V g RC V g1 V g2 V con<<v g C f t(v g1 ) t(v g2 ) f= t RCV con V nom ~ = T clk T clk V g Vg Fig.5 Operation of the counter A/D for input voltage feedforward (IVFF) IVFF gain f Digital Ideal Nominal Voltage=9V Input Voltage (V) Fig.6 Ideal IVFF gain V nom /V g and IVFF gain f in digital implementation as a function of the input voltage V g generates the digital signal f as follows: a current proportional to V g charges a capacitor and a counter clocked by the system clock measures the time t it takes to charge the capacitor to a fixed threshold. As shown in Fig. 5, the counter A/D output f is proportional to V g /V gnom, t RCV V con gnom f = = (3) Tclk TclkVg Vg where V gnom is a nominal input voltage (typically in the middle of the input voltage range). A dual-slope version of the counter A/D could be used to eliminate the dependence of V gnom on the RC time constant. Signal f is the IVFF gain that scales the duty-cycle command D[n] as shown in Fig. 1. Fig. 6 compares the ideal IVFF gain to the quantized value f over the input voltage range from 5 V to 12 V, with V gnom = 9 V. In addition to properly adjusting T on and T off in PFM operation, the benefits of IVFF include improved dynamic performance, as illustrated by the waveforms in Fig. 7. V. EXPERIMENTA EFFICIENCY RESUTS In the PWM/PFM controller of Fig. 1, programmable parameters for efficiency optimization include: PWM switching frequency f s (set by f s_command in PWM mode), PFM Output Voltage [50 mv/div] Output Voltage [50 mv/div] High side drive signal High side drive signal (a) (b) Fig.7 PFM to PWM transition for a A load step transient at input voltage V g =5V: (a) without IVFF, and (b) with IVFF 526

5 pulse period T PFM (set by f s_command in PFM mode), and the mode transition point (which can be set by timing the signal Syn as discussed in Section III). with IVFF 500mV efficiency without IVFF 400mV PFM 300mV 200mV Fig. 8 shows efficiency as a function of load current for the experimental prototype at two input voltages and the same f s_command = 400 khz in both PWM and PFM modes. As expected, significant light-load efficiency improvements can be observed in PFM compared to the case when the converter operates in constant frequency PWM mode at all loads. For further efficiency improvements, different f s_command can be set in the two modes. Fig. 9 shows the result for f s_command = 400 khz in PWM mode, and f s_command = 265 khz (T PFM = T on T off = 3.75 µs) in PFM mode. The hysteresis in mode switching is noticeable in the efficiency plot. 40% 30% 20% 10% 0% PWM Vg=6V Vg=9V 0.0A 0.1A 1.0A 10.0A Fig.8 Experimental efficiency including gate-drive and converter losses as a function of load current for PWM and PFM operations. Switching frequency f s =400KHz in PWM, T on T off =2. 5µs in PFM output ripple 4V 6V 8V 10V 12V Fig.10 Efficiency and ripple comparison with and without Input Voltage Feed-Forward in the PFM mode with 0.5 A load current Fig.10 shows that input voltage feed-forward results in improved efficiency over the entire input voltage range, while at the same time significantly reducing the output ripple. Fig. 11 shows that synchronous operation with input voltage feed-forward results in about 20% efficiency improvement in PFM compared to non-synchronous operation (when the synchronous rectifier is kept off in PFM). Synchronous operation 100mV 0mV PFM Asynchronous operation Vg=5V Vg=9V 40% 30% PWM 40% 0.0A 0.5A 1.0A 1.5A 20% 10% Vg=5V Vg=9V Fig.11 Experimental efficiency test comparing the synchronous and asynchronous operation in the PFM mode. 0% 0.0A 0.1A 1.0A 10.0A Fig.9 Experimental efficiency including gate-drive and converter losses as a function of load current for PWM and PFM operations. Switching frequency f s =400KHz in PWM, T on T off =3.75µs in PFM VI. CONCUSIONS This paper describes a digital pulse-width modulation/pulse frequency modulation (PWM/PFM) controller for synchronous buck DC-DC converters. At light loads, the controller operates in PFM mode using a single active 527

6 comparator to achieve output voltage regulation. Synchronous operation with near-optimum on/off timing of the synchronous rectifier in PFM is accomplished without the need for inductor current sensing. Digital input voltage feed-forward (IVFF) is accomplished using a simple single-comparator counter-based A/D converter for sensing the input voltage. It is shown that IVFF results in improved rejection of input voltage disturbances, improved dynamic responses, as well as reduced ripple and improved efficiency in PFM. The controller includes automatic PWM/PFM mode switching. Programmable parameters (PWM switching frequency, PFM pulse period, and the mode transition point) enable efficiency optimization. Experimental results are shown for a synchronous buck converter with 5-to-12 V input voltage, 1.3 V output, and the load current in the 0-10 A range. REFERENCES [1] B. Arbetter, R. Erickson, and D. Maksimovic, DC-DC converter design for battery-operated systems, in Proc. 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