An Architecture without Current-sensing Circuits for Digital DC-DC Controller to Achieve Adaptive Voltage Position

Transcription

1 An Architecture without Current-sensing Circuits for Digital DC-DC Controller to Achieve Adaptive Voltage Position Peipei Gu, Wenhong i ASIC & System State Key ab Fudan University Shanghai, 433, P.R.China Abstract- this paper describes a novel architecture, which can achieve adaptive voltage position without sensing any load current. In the context, the architecture and algorithms of the controller is introduced. A digital DC-DC controller IC with programmable ability using the method and its experimental results are presented. I. INTRODUCTION Digital control has been studied as another choice for DC- DC converters due to its significant advantages, such as easy to integrate with other digital parts, lower sensitivity to process and environment variations, no need of passive components for tuning the control loop and easy to realize additional functions like power on sequencing. And the digital controller can be monitored and programmed easily through communication bus. Furthermore, The design can be described at the function level using a hardware description language, and modern EDA tools can be used to fast the design [1-5]. Adaptive Voltage Position makes full use of the whole voltage tolerance window, which can reduce the number of output capacitors required to meet the output voltage regulation. The approach is required by the state-of-the-art VRM controllers [6-1]. To design a controller with AVP, load current information has to be sensed. Different kinds of current sensing methods can be found in many publications [11-14]. The requirement of accurate current sensing circuit increases the difficulty of the circuit design. Ordinarily, thermal compensation methods are needed for lossless current sensing to decrease the error between the sensed current and load current. In this paper, the architecture of a digital DC-DC controller with AVP is introduced. It dose not need any current sensing circuit and is similar to voltage mode controller. It can works either as an AVP controller or as a voltage mode controller by programming to suit for different applications. In section II, the architecture of the controller is introduced. In section III, the control algorithm is analyzed. Finally, section IV shows a complete IC implementation based on the method and its experimental results. II. DIGITA CONTROER ARCHITECTURE The architecture of the digital DC-DC controller is presented in Fig. 1. The digital controller includes filter X, the input filter, filter H, the DPWM (Digital Pulse Width Modulator) circuit. An 8-bit ADC is used to sense the output voltage Vo. The reference voltage is denoted by 8-bit VID (Voltage Identification) code. The input filter, filter X and filter H is used to deal with the output of the ADC, VID code and the error signal respectively. Finally the DPWM generates the interleaved 4-Phase PWM signal to regulate the power s of each phase. Comparing with traditional architecture, there is only one voltage loop, and no current information is used. Also, the VID signal is not subtract from Vo directly but pass through a additional filter X before subtracted by Vo. Actually, when the gain of filter X equal to 1, the controller will act as an traditional voltage mode controller. So, it is easy to alternate between the two control modes by programming. III. CONTRO AGORITHM DESIGN Fig. shows the small signal model of the system. The multi-phase buck converter can be simplified into a singlephase model [15]. The control-to-output transfer function of the buck converter is as follows: SCRC + 1 Gvd() s = Vin (1) S C + SC ( R + R C) + 1 where, R C is the ESR of the output capacitors, R is the equivalent value contributed by each phase which includes the DCR of the inductor, the R ds(on) of the, and the parasitic resistance of the traces. The output impedance of the buck converter can be calculated as: S RCC+ S( + RCRC) + R Zo() s = () SC+ SCR ( + R) + 1 C The work was supported by Shanghai Science and Technology Committee (SDC project, No: 4763) and also supported by National Natural Science Fund (No ) /7/$. 7 IEEE. 563

2 Vin DPWM Phase_ Phase_9 R Vin Digital Controller error Filter H Phase_18 Vin R C R C Vo I load Filter X Input Filter R Vin VID ADC Phase_7 R,R )V =RV *YGV +V Figure 1. Block diagram of the digital controller and its application Z = ZO oc 1+ FDHGvd = R load F = FDHGvd C 1+ FDHG 9R vd X = 1 ;V Figure. The small signal model of the system 9 UHI For digital implementation, F(S) is the product of the transfer function of the DPWM and the ADC, 1 Vrange _ adc FS ( ) = ndpwm nadc (3) where ndpwm and nadc is the resolution of DPWM and ADC respectively and V range_adc is the full-range of the ADC. D(S) is the transfer function of the system delay, Ds () = e st. D(S) can be transformed to zero-pole format by Pade approximation. To achieve AVP, the close loop impedance should be equal to the required AVP load line. The equation (4) is required. VO = Vref -Rload IO (4) Where R load is the load line required by AVP. From Fig., the output voltage may be expressed as (5). FDHG Z V vd - O O= XVref IO (5) 1 + FDHGvd 1 + FDHGvd Comparing (4) with (5), the following equation can be gotten: Where Z oc is the close loop output impedance, F C is the close loop transfer function of the output voltage to the reference voltage. Transfer function of filter H and X can be calculated from (6), ZO R O 1 H = RO FDGvd (7) Z X = O ZO RO Substituting (1), (), (3) and D(S) for (7), the accurate forms of filter H and X are gotten as follows: as as () + as 1 + a Hs = bs 1 + b (8) cs () + cs 1 + c Xs = ds + ds 1 + d where, C( R ) 3 C R a = load, f sw + R ( ) RCC RRloadC RCRloadC a = C RC Rload +, f sw R R a1 R R C R R C R R C = + load C load C load +, f sw (6) 564

3 a = R R, load b1 = R R FV C, C load in b = R FV, load in c = CR, C c1 = + R R C, C c = R, d = C( R R ), C load d1 = + R R C R R C R R C, C load C load d = R R load When R C =R load, (8) can be simplified further. If (8) is realized, the system can achieve AVP. However, it is difficult to implement those equations without any simplification even when R C =R load using analog circuits. But digital circuits have potential ability to realize such complex filter. MATAB is used for the algorithm design. For example, let R C =R load =mω, Fig. 3 shows the simulation results of the open loop output impedance Zo and the close loop output impedance Zoc. Obviously, the close loop output impedance is a constant with the value of 54dB (mω). The frequency response of Fc is equal to 1, so the system is stable. Vo(V) Io(A) Ti me(s) x A/uS 8mV Ti me(s) x 1-3 Figure 4. Simulation results for the transient IV. DC-DC CONTROER IC A digital controller IC with above architecture is implemented in CSM P4M.35 m CMOS process. Verilog HD is used to design the chip. The die photo is shown in Fig. 5. The die area is about 4 mm. -3 Bode Diagram -35 Zo Magnitude (db) Zoc Zoc Phase (deg) -3 Zo Figure 5. Die photo of the IC in.35 m CMOS process Frequency (Hz) Figure 3. Output impedance with open and closed loops Using backward Euler method, the discrete equations of filter H and X are gotten. dn [ ] = ken 1 [ ] ken [ 1] + k3en [ ] k4en [ 3] + k5dn [ 1] (9) VID [ n] = l VID[ n] l VID[ n 1] + l VID[ n ] + l VID [ n 1] l VID [ n ] (1) ' ' ' MATAB/Simulink is used to model the digital controller. Fig. 4 is the simulation waveform of the output voltage during the load current changes between and 4A with a slew rate of 5A/µS. The load line is equal to mω. The simulation results agree with the theoretical analysis. A. Overview of the IC schemes A block diagram of the IC is shown in Fig. 6, which consists of three units according to their different functions. The control unit, including input filter, filter H and the DPWM, generates PWM signals according to the algorithms stored in filter X and register bank to adjust the output voltage. The communication unit includes an I C slave interface and some control logic to write or read filter X and registers. The auxiliary unit, including clock and reset logic, generates clock signal and reset signal for each circuit. The following sections will introduce them respectively. 565

4 VID Auxiliary Unit Clock Generator Reset ogic Filter X SDA SC IC Slave Registers Filter H DPWM PWM_ PWM_9 PWM_18 PWM_7 address Communication Unit Input Filter Control Unit B. The control unit The object of the input filter is to calculate the average value of the output voltage during one period. The input filter uses an average filter, which can reach the aim and reject the noise. Filter H and X should realize (1) and (11) respectively. Programmable look-up table or shift-adder architecture can be used to implement them. Obviously, when the value of filter X equal to the input VID code, the IC acts as a voltage mode controller. The experimental results of different control mode will be given in section IV.E. To avoid limit cycle [5], the resolution of DPWM should be bigger than ADC. In the design the resolution of ADC is 6.5mV/bit, so 11-bit DPWM with the resolution of 5.9mV/bit is used to avoid limit cycle. DPWM circuit is implemented using a dither architecture introduced by [5]. C. The communication unit The IC includes an I C slave interface to communicate with the master. The communication unit receives the bit data to form the data flow according to the defined protocol. Filter X and registers can be programmed and monitored by I C master. The I C master can be designed based on FPGA or GUI software. A timing register is used to store open and close delay time used for open and close sequencing control. A flag register which includes power good bit, over voltage bit and under voltage bit for monitor and soft start bit and default data selecting bit to control the IC. 9R Figure 6. Block diagram of the digital controller IC D. The auxiliary unit The clock source includes two ring oscillators working at 18MHz and 56MHz respectively. The clock logic generates different clock for each circuit. The timing relationship of those clocks is shown in Fig. 7. fclk_adc is used as ADC sampling clock with 16MHz sampling rate. fclk_pre_process is the clock of input filter, which control the unit to output the average value at the speed of 1MHz at the rising edge. fclk is the clock of filter H, which makes filter H output control value to DPWM with speed of 1MHz at the rising edge. IFONBDGF IFON IFONBSUHBSURFHVV Figure 7. Timing relationship of clocks output by the auxiliary logic The reset logic is used to calculate time to start or stop the IC according to the value of the timing register. E. Experimental results The architecture of the testing circuit is like Fig. 1. ADP311 is used as the driver. AD98 is used as the ADC. PHD78NQ3T and PHD18NQ3T are used as the up and the down respectively. The inductor of each phase is 4nH. Eight 68µF OSCON capacitors are used with ten µf MCC paralleled. The ESR of each 7 566

5 OSCON is equal to 7mΩ. A DC electronic load instrument is used as load, which can provides 4A at A/ S at CC mode. A PC ATX power is used to supply all devices in the testing board. With an I C master based on a FPGA, the register and lookup-table can be programmed and monitored. The algorithms used at the following testing is gotten at the condition of Rc=Rload=1mΩ. The input voltage of the DC-DC is 1V and the output voltage can be adjusted by 8-bit VID code range from to 1.6V. The maximum set point error is less than 15mV. The value is mainly determined by the performance of ADC. Table I shows the set point error testing from 1.V to 1.3V, where Vref is the reference voltage set by VID, Vo is the output voltage. TABE I Set Point Error (From 1.V to 1.3V) Vref(V) Vo(V) Vref Vo(V) (a) (b) Figure 8. Experimental results for the transient, (a) AVP mode, (b) voltage control mode oad transient waveforms are shown in Fig. 8, where the load current changes periodically between 5A and 4A with a slew rate of A/ S. Fig.8 (a) is the output voltage at AVP control mode. When the value of filter X is programmed to equal to the input VID corresponding, the IC will works in voltage control mode. Fig.8 (b) shows the output voltage when the IC works in voltage control mode. The testing condition is same as Fig.8 (a). Fig.9 shows the output voltage during start-up. ine 1 is the waveform of the output voltage. ine is the waveform of the start control signal. The value of the timing register is set to 63. The frequency of the count clock is about 5K. We can see from the figure, the output voltage is delayed about.56ms. Figure 9. Output voltage during start-up V. CONCUSIONS 567

6 This paper describes a novel architecture which dose not need load current information to achieve AVP. A digital DC- DC controller IC using the architecture is introduced. Two control modes can be alternated by program. The experimental results are given to prove the design methods. ACKNOWEDGMENT The authors greatly thank Ming Kong for his help in PCB layout. We also thank Jian-Min Guo for his help in DRC and VS. Shanghai Research Center for Integrated Circuit Design (ICC) provides MPW service. REFERENCES [1] J. Xiao, S. R. Sanders, and A. V. Peterchev, Architecture and IC implementation of a digital VRM controller, in IEEE Transactions on Power Electronics, vol.18, 3. [] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, Highfrequency digital PWM controller IC for DC-DC converters, in IEEE Transactions on Power Electronics, vol.18, 3. [3] A. Prodic, D. Maksimovic, Mixed-signal simulation of digitally controlled switching converters, in IEEE Workshop on Computers in Power Electronics,. [4] S. Saggini, M. Ghioni, and A. Geraci, An innovative digital control architecture for low-voltage, high-current DC-DC converters with tight voltage regulation, in IEEE Transactions on Power Electronics, vol.19, 4. [5] A. V. Peterchev, S. R. Sanders, Quantization resolution and limit cycling in digitally controlled PWM converters, in IEEE Transactions on Power Electronics, vol.18, 3. [6] Intel Corp., Intel Document, Voltage Regulator-Down 11. Processor Power Delivery Design Guidelines, June 6. [7] K. Yao,.K. ee,.m. Xu,.and F.C. ee, Optimal design of the active droop control method for the transient response, in IEEE APEC, 3. [8] X. Zhang, G. Yao, A.Q. Huang, A novel VRM control with direct load current feedback, in IEEE APEC, 4. [9] K. Yao, Y. Ren, J. Sun, K. ee, M. Xu, J. Zhou,.and F.C. ee, Adaptive voltage position design for voltage regulators, in IEEE APEC, 4. [1] W.k. Huang, The design of a high-frequency multiphase voltage regulator with adaptive voltage positioning and all ceramic capacitors in IEEE APEC, 5. [11] J.. Sun, J. H. Zhou, M. Xu; and F.C. ee, A novel input-side current sensing method to achieve AVP for future VRs, in IEEE APEC, 5. [1] G. Garcea, S. Saggini, D. Zambotti, M. Ghioni, Digital auto-tuning system for inductor current sensing in VRM applications, in IEEE APEC, 6. [13] Hassan Pooya Forghani-Zadeh, A. Gabriel, and Rincon-Mora, Current-sensing techniques for DC-DC converters, in IEEE IECON, 5. [14] Y. Zhang, R. Zane, D. Maksimovic, A. Prodic, On-line calibration of lossless current sensing, in IEEE APEC, 4 [15] Pit-eong Wong, Fred C. ee, P.Xu, and wei Yao, Critical inductance in voltage regulator modules, in IEEE Transactions on Power Electronics, vol.17,. 568