Digitally controlled voltage mode schemes provide equivalent performance to current mode control

Transcription

1 The World Leader in High Performance Signal Processing Solutions Digitally controlled voltage mode schemes provide equivalent performance to current mode control IBM Power and Cooling Technology Symposium Analog Devices Inc th September, 2006

2 Abstract Increased demand for system management and the availability of inexpensive submicron CMOS processes have started the inevitable migration to digital power. Implementation of Current mode control adds cost to a digital control loop because requirements on the current sensing ADC Using digital techniques - offering alternative approaches and enhancements to counter problems normally associated with voltage mode control method Achieving similar performance to current mode control 2

3 3 Why use Digital Power?

4 Why use Digital Power? Circuit Complexity Increased Functionality Pressure to improve power density Achieved through increased efficiency & cooling techniques Confounded by the slow rate of capacitor size reduction and magnetic material improvements High Power 3-Stage Topology Ref: M. Jovanovic Delta APEC 2006 Logic and Drives required for ~ 9 FETs (incl.pfc) Ref: M. Jovanovic Delta APEC 2006 Improving efficiency through functional integration Designing around the slow improvements in passives 4

5 Why use Digital Power? Circuit Complexity Efficiency Improvement Intelligent Power Supplies ZVS Bridge Example Standby modes become programmable Trimming efficiency on-the-fly Frequency and timing delays can be changed to optimise efficiency PWM to PFM in standby mode Improving EMI Dithering techniques Frequency is modulated within a narrow band Reduction in emissions measured 5

6 Why use Digital Power? Reliability Component Count Reduction Component Count Reduction Electronic Trimming ADM1041 facilitates large component count reduction on a typical server ACDC Power supply ADM1041 is a digitally managed solution 6

7 Why use Digital Power? Circuit Design Flexibility Adaptive Loop Control If ESR of output cap changes due to temperature or aging, control loop pole can be adapted accordingly Less margins are needed => Higher bandwidth, smaller output caps Adaptive Timing When using ZVS (Zero-Voltage-Switching) in a full-bridge topology the ideal timing is dependent on the output current With adaptive timing efficiency can be improved 7

8 Why use Digital Power? Digital Management and Interfacing Monitoring Currents, voltages and temperatures are available through a digital bus interface Programmability OCP, OVP, UVP, OTP Soft-Start, Fault Response Trimming Vout, Current-Sense Margining, Testing Inventory Control, Software-based Customization Reduced PCB re-spins Calibration Reduces test cost Margining Reduces test cost 8

9 Why use Digital Power? Digital Cost Trends Ref: Y Borodovsky Intel SPIE Microlithography

10 Why use Digital Power? Digital and Analog Cost trends Moore s Law is different for Analog and Digital $ $10.00 $1.00 $0.10 $0.01 Digital ($/kgate) Analog ($/nf) Ref: Anton Bakker Analog Devices Inc. The area of digital is cut in half with every new generation The area of analog is reduced by 20~30% with every new generation The cost of digital is cut in half every 2~3 years The cost of analog is cut in half every 4~8 years In 90nm CMOS, 8051 core is the size of a bondpad 10

11 Implementations in Digital Layout comparison in 0.25um CMOS Bondpad + ESD 12-bit ADC 10pF 11

12 12 Implementations in Digital

13 Implementations in Digital Analog Control Loop power stage controller pwm filter Vref Error amplifier has two functions: 1. DC accuracy 2. AC response Typical specs 1. Low offset: ~1mV 2. High bandwidth: ~1MHz 13

14 Implementations in Digital Digital Control Loop (1) power stage controller pwm digital filter REF ADC ADC has two functions: 1. DC accuracy 2. AC response Typical specs 1. High resolution: ~12 bits 2. High bandwidth: ~1Msample/s 14

15 Implementations in Digital Digital Control Loop (2) power stage controller pwm digital filter ADC REF DAC ADC is for AC response DAC and amplifier are for DC accuracy Typical specs 1. ADC: 6 bits, 1Msample/s 2. DAC: 10 bits, 1ksample/s 15

16 Implementations in Digital Digital Control Loop (3) power stage controller summer PWM & filter REF ADC1 ADC2 HPF Patent Pending ADC1 is for DC accuracy ADC2 is for AC response Typical specs 1. ADC1: 12 bits, 1ksample/s 2. ADC2: 6 bits, 1Msample/s 16

17 Implementations in Digital Current Mode and Voltage Mode Current Mode Advantages Single pole in the control loop simple compensation Good input line response Pulse by Pulse Limiting auto flux balancing Disadvantages High bandwidth loop sensitive to noise - leading edge current ringing Unstable at duty >50% without added slope compensation (VM always requires a slope) Voltage Mode Advantages Large ramp provides noise immunity Single Feedback loop Relatively easy to design and analyze Disadvantages Possibility of imbalance and saturation in symmetrical circuits No cycle-cycle current limit Input voltage response CCM-DCM response change Double pole in the control loop complicates compensation Current Mode would require high B/W, high resolution ADC Digital implementations tend to be voltage mode 17

18 Implementations in Digital Voltage Mode and Current Mode Volt-Second Balance (a) V IN OUTA OUTC OUTB OUTD CS1 INPUT ADC COUNTER CS1 ERROR PWM COUNTER 2 ADP

19 Implementations in Digital Voltage Mode and Current Mode Volt-Second Balance (b) V IN OUTA OUTC OUTB OUTD CS1 INPUT ADC COUNTER CS1 ERROR PWM COUNTER 2 ADP

20 Implementations in Digital Voltage Mode and Current Mode Volt-Second Balance Timing Example PWM1 (OUTA) PWM3 (OUTC) PWM1 (OUTB) PWM4 (OUTD) CS1 ERROR CS1 Input CYCLE COMMENTS INITIAL ERROR (eg DUE TO FET IMBALANCE) PWMS ARE ADJUSTED TO BALANCE CS1 SIGNALS PWMS ARE ADJUSTED TO BALANCE CS1 SIGNALS APPROX 50 CYCLES CS1 SIGNALS ARE BALANCED CS1 SIGNALS ARE BALANCED 20

21 Implementations in Digital Voltage Mode and Current Mode Volt Second Balance Results 21

22 Implementations in Digital Voltage Mode and Current Mode Primary Side Over Current Protection (OCP) V IN OUTA OUTC OUTB OUTD CS1 ADC 250 S/sec SLOW OCP (AVERAGE) REF PWM VREF FAST OCP COMPARATOR (20 nsec) FAST OCP (PEAK) ADP1043 Fast OCP performed using analog circuitry 22

23 Implementations in Digital Voltage Mode and Current Mode VM Control Loop Issues (1): Input Line Response Voltage mode system gain changes with input voltage High-end systems work from regulated input voltage from Power Factor Stage Slow changing transients Line response issues become less relevant 23

24 Implementations in Digital Voltage Mode and Current Mode VM Control Loop Issues (2) Loop Compensation k 10k 100k 1M f [Hz] Type 3 Compensation is necessary to resolve control loop stabilization k 10k 100k 1M f [Hz] Courtesy of Richard Redl

25 Implementations in Digital Voltage Mode and Current Mode VM Control Loop Issues (3) CCM DCM Transitions Current mode loop response changes when moving from continuous conduction mode to discontinuous mode Magnitude [db] Current Mode DCM Frequency [Hz] Current Mode CCM CMC DCM the peak current does not change when the input voltage changes, therefore the input-voltage rejection remains essentially the same as in CCM. Phase [degrees] Current Mode DCM Current Mode CCM 25 Frequency [Hz] Courtesy of Richard Redl

26 Implementations in Digital Voltage Mode and Current Mode VM Control Loop Issues (3) CCM DCM Transitions Voltage mode loop response changes when moving from continuous conduction mode to discontinuous mode Magnitude [db] Phase [degrees] 26 Voltage Mode DCM Voltage Mode DCM Frequency [Hz] Voltage Mode CCM Voltage Mode CCM Frequency [Hz] Courtesy of Richard Redl VMC CCM with open regulating loop the output voltage is proportional to the input voltage. VMC DCM the simple proportionality changes into a steeper function because the change in the input voltage leads to a linear change in the peak current Using dynamic adjustment of the digital filter, it is possible to change the loop response for CCM and DCM conditions

27 Summary and Conclusions Complexity of power supplies to meet energy efficiency and power density demands requires higher levels of integration and intelligence Digital approaches are becoming cost competitive as semiconductor geometries continue to shrink Current mode control implementation in digital can be expensive high resolution, high speed ADC Intelligent digital design approaches can counter many of the traditional problems associated with voltage mode without adding significant cost to the design 27