Agenda. Digital Today Smart Power Management Tomorrow. Brief History of transistor development. Analog PWM controllers. CMOS Historical perspective

Transcription

1 6-Sep-06 Digital Today Smart Power Management Tomorrow September 2006 Stephen Pullen Vice President System Engineering Primarion Corporation Agenda o o o o o o Brief History of transistor development Analog PWM controllers CMOS Historical perspective System Requirements Digital PWM controllers True Digital Power Management solutions 6-Sep-06 p. 2

2 In the Beginning 1953 Man created the transistor 1965 Moore s law postulated K transistors on a die 1976 Silicon General introduces the industry's first PWM controller IC, the SG1524,designer, Bob Mammano National Semiconductor introduces the first threeterminal linear regulator designed by Bob Dobkin GM introduced its computer-controlled closed-loop carburetor system using a micro-processor. 6-Sep-06 p. 3 In the Middle 1970 s-as of the close of the 70 s, the first PC has not been announced st PC is released- Model 5150 by IBM SGS introduces the L296, the first monolithic switching regulator BiMOS- The power transistor was a bipolar device and the smarts were in CMOS transistors initially developed at Motorola Vicor released 1Mhz full brick with custom analog chip. Design only had about 90 parts total. 6-Sep-06 p. 4

3 Into the Present 1990 s- Bi-CMOS becomes a preferred choice of analog PWM controllers. CMOS is changing PWM internal architecture Linear Technology introduces the first synchronous switching regulator Semtech release first monolithic multiphase controller Volterra announces a mixed signal controller for creating multiphase circuits Primarion releases its first digital multiphase controller CMOS One billion transistors on a die 6-Sep-06 p. 5 SG3525 Functionality Current mode and voltage modes Up to 500Khz operation State of the Art 50nsec propagation delays to output Analog Bandwidth? 1.5 amp totem pole drivers Wide bandwidth amplifier- 10Mhz Latched logic for double pulse suppression 5 GHz Pulse by Pulse current limiting Soft start and max duty cycle control Under voltage lockout 1.1mA start up current Trimmed band gap +/-1 % 6-Sep-06 p. 6

4 SG3525 Block Diagram 6-Sep-06 p s functionality Similar to 1985 PWM control- Current and Voltage mode control Internal reference OVP, OCP fault conditions Current sharing CMOS begins to Up to 1 MHz operation change inside architecture Wide 10MHz bandwidth of the analog control chip Soft Start, Max duty cycle In the 90 s Power good Under voltage lockouts Synchronous timing drives- high current output drivers 6-Sep-06 p. 8

5 Analog Product Exploded Analog PWM for power supply applications Specific chips for varied topologies Half bridge drivers, high side drivers Sync FET drivers, synchronous FET timing Peak and average current mode control Resonant PWM Buck- Multiphase, dual phase, single phase Battery charging applications Cell phones Camera, video, and handheld products 6-Sep-06 p. 9 Present Analog Architecture Changed by CMOS CMOS circuitry- replaces large portions of the analog design Comparators for power good, OVP,UV etc Clocks- Timing and logic PWM signal processing Analog circuitry- provides interface to the CMOS circuitry Error Amplifier, compensation, current sense, and voltage sense are still analog circuits Analog circuits connect the outside circuitry to the internal CMOS functions 6-Sep-06 p. 10

6 SG3525 Block Diagram CMOS Today 6-Sep-06 p. 11 CMOS Historical Advancements CMOS Driven by lithography advances: 1981 to u to.25u 1999 to u to 45 nm Maximum die size relatively constant 100 gates fit inside the diameter of a human blood cell Moore s law strongly in force since Transistor: 1 dollar in Transistor: 1 penny in K per die 1 Transistor: 1/10,000 penny billion per die 6-Sep-06 p. 12

7 The Future of CMOS Intel is developing 3D dimensional die stacking By Hundreds of cores per processor die. The cores will support 100 s to 1000 s of simultaneous execution threads. Memory to processor connections from 100 s or 1000 s of pins to million to 10 million connections. Bandwidth is still increasing All while the cost per gate is decreasing All the while the speed is increasing 6-Sep-06 p. 13 Where are We Headed If steel was the raw material for the 20th century, silicon is for the 21st century. And the silicon semiconductor industry led in large part by Intel s technology advances has delivered a dramatic spiral of rapid cost reduction and exponential value creation that is unequalled in history. Because of the cumulative impact of these spiraling increases in capability, silicon the raw material of the microprocessor powers today s economy and the Internet, running everything from digital phones and PCs to stock markets and spacecraft and enables today s information-rich, converged, digital world. Technology@Intel Magazine April 2005 From Moore s Law to Intel Innovation Prediction to Reality Radhakrishna Hiremane Technical Marketing Engineer Intel Corporation 6-Sep-06 p. 14

8 Process and Price for PWM Controllers Year Process Size Gates ASP Cent/gate CMOS 1980's Analog 3u to 7u 100 $ % 1990's Bi-Cmos 1u 400 $ % Present Bi-Cmos 0.35u 3000 $ % Present CMOS.25u 100,000 $ % Future CMOS.18u 200,000 $ % 6-Sep-06 p. 15 Digital Trends for Power Management I2C communication bus definition - ex. PMbus Transistor cost still going downward Each CMOS process improvement step can give 2x real-estate reduction Functionality constant at approximately half the cost Future digital power management will take advantage of low cost high volume CMOS processor roadmaps System costs with digital power management will continue downward 6-Sep-06 p. 16

9 System Power Management Requirements System Power management complexity continues to increase-up to 16 POL modules on system board required in various applications. Timing, delays, sequencing, tracking, hot swap functionality System characterization of processors and ASICS needs simplification Communication of faults to system Fault reporting of each power device Communication with other power devices and load IC Optimization of power consumption on system boards, dynamic phasing Reporting of voltage, power, current, temperature parameters to system Diagnostics- Anticipation of faults, monitoring and correcting parameter drifts Idle modes- Management of power to meet Green Power requirements High Transient load environments- smaller windows of deviation High speed bus communication adaptability 6-Sep-06 p. 17 Analog and Digital Difference? Today's PWM controllers: First process signals in the analog domain and then process PWM logic in the digital domain. Process internal information externally by digitizing signals with another device or add on digital wrappers More costly system implementation True digital controllers: Convert signals immediately into the digital domain The digitized signals are placed into registers All subsequent signal processing is done digitally Information can be directly communicated to the system Less costly system implementation 6-Sep-06 p. 18

10 Digital Power Management Since all information is digitized: One can multiply, divide, filter, compensate, compare, calibrate, store and communicate each piece of information I2C flexibility built in- PMBus, SST, Future Bus choices easily adapted Specific algorithms define total functionality for power device Asynchronous and non-linear control loop algorithms can be easily implemented for optimal fast transient response or advance functions Digital power management can enable system communication and control of power delivery to the load IC 6-Sep-06 p. 19 True Digital implementation Provides design Flexibility Compensation can be optimized for each rails capacitance and inductance All design parameters are programmable No discrete components for design implementation Component calibration and drift monitoring Provides Personalization for each power stage Each rail can be uniquely defined for its requirements One chip can provide multi-faceted design options Full telemetry of power stage is available to system Full custom programmability with one standard part 6-Sep-06 p. 20

11 Typical Block Diagram Digital Power Management controller SYNC_IN FSET VSET VTRIM VSENP VSENN V12SEN TEMPSEN Voltage Sense Temp Sense MUX Reference & Oscillator ADC DAC PID/PWM Controller SYNC_OUT IOUT/ISH ISH_GND PWM ISENP ISENN IMAXSET Current Sense VCC SCLK SDATA SADDR OUTEN SMBus Non-Volatile Memory (NVM) State Machine Fault Handler SMB_AL_N FAULT1 FAULT2 PWRGD 6-Sep-06 p. 21 Basic Buck Circuit Block +5V to +12V +5V R1 PMBus I/F SDATA SCLK SMB_ALRT_N V12SEN VCC Power Management I/F Multiphase Operation Fault Outputs I-share PWRGD OUTEN PX7510 SYNC_IN SYNC_OUT FAULT1 FAULT2 IOUT/ISH ISH_GND GND PWM TEMPSEN ISENN ISENP VSENP VSENN SADDR VSET FSET VTRIM IMAXSET R2 6-Sep-06 p UGATE 2 BOOT 3 PWM 4 GND 4.7µF PHASE EN VCC LGATE RCM D1 RSENSE RB CB VOUT RTN LOAD Very Few Parts - Driver, FETS, inductor capacitors, snubbers and current sense: enable high density power solutions

12 Multiphase VRM Circuit Digital provides key Solutions with Low Part Content 6-Sep-06 p. 23 System Implementation 12 volt Bus System Management Digital Manager Local Control Bus (i.e. PMBus) System Supervisor System Bus POL 5.0V POL 3.3V POL 1.5V POL 1.5V POL 1.8V POL 1.8V Multiphase VRD Chip 1 Chip 2 Memory Memory Memory Memory Processor Analog Digital Analog Systems Systems with Tomorrow Digital Today Manager 6-Sep-06 p. 24

13 Summary Analog power management has been central to power management growth in the past but must adapt to the future. Digital power management solutions will continue to take advantage of the CMOS lithography advancements using low cost, high volume processes. Digital power management has the scalability and flexibility to innovate future system solutions Smart digital power management will enable lower cost system implementation with intelligence that will grow with the increased complexity of power delivery 6-Sep-06 p. 25