UCD9240 Digital Synchronous Buck Controller

Transcription

1 UCD940 Digital Synchronous Buck Controller FEATURES Controls up to 8 power stages and up to 4 voltage feedback control loops. Flexible configuration, device can control: o Four single or dual power stages, o Two 4-phase power stages, or o One,4,, or 8-phase power stage. Supports switching frequencies up to MHz. Supports conversion ratio of 0 to at MHz with better than 0.% duty-cycle resolution +-mv feed-back resolution Hardware accelerated digital 3-pole/3-zero compensator Internal regulator controller allows for external pass element and Vin from 4. V to V Low power consumption: ma at 3.3 V Power supply monitoring with better than 0.mV resolution used for reporting: o Vin, o Vout, each rail, o Iout, each power stage (phase), o External Temperature, each stage. Fast analog comparators monitor analog current sense voltage for each control loop. Eight Synchronous Rectifier Enable () outputs. Able to synchronize clocks between multiple UCD940 devices. On-chip temperature sensor. Supports PMBus version.. Programmable soft start and soft stop ramps under closed loop control. Supports voltage tracking. Supports current sharing on multi-phase power stages. Supports phase shedding on multi-phase power stages based on average current. Programmable voltage, current and fault data-logging. Programmable fan control outputs. Programmable margining and sequencing. Intuitive PC based Design Tool to simulate, configure, and measure power supply performance. APPLICATIONS Industrial / ATE Networking Equipment Servers Storage Systems Telecommunications Equipment DESCRIPTION The UCD940 is a digital synchronous buck controller that can control up to 8 power stages in multi-phase configuration or up to 4 feedback outputs with two phases per output. This device provides enhanced configurability and control for point of load (POL) applications. The device is configured using a serial interface that conforms to the PMBus version. protocol. A PC based Design Tool program is provided to configure the controller. The switching frequency, output configuration and feedback compensation are programmed through the Design Tool's graphical user interface (GUI). This allows one part to support multiple converter arrangement and to meet dynamic converter performance for a broad range of POL applications. Each control loop consists a very high speed digital control loop with individual digital 3-pole/3-zero compensators and a high resolution digital s. In addition to implementing a digital control loop, the UCD940 is able to monitor and manage power supply operating conditions and report the status to the host system through the PMBus. The management parameters are configurable through the PC Design Tool. The Design Tool also allows the power supply designer to easily configure the digital control loop characteristics and generate the expected performance by displaying Bode plots for each controlled power stage. On multi-phase power stage outputs, the UCD940 incorporates digital current balancing. The average current in each phase is monitored and the duty cycle for each phase adjusted to balance the average current. In addition, the UCD940 supports "shedding" one or more phases (ganged power stages) based on the average current demand. When a phase is dropped or added the UCD940 automatically adjusts the phase of each output to minimize output ripple as well as any needed change in loop compensation. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright 007, Texas Instruments Incorporated

2 FUNCTIONAL BLOCK DIAGRAM EAP4 EAN4 Error ADC Compensator 3P/3Z IIR Digital High Res D-4A D-4B FAULT-4A FAULT-4B EAP3 EAN3 Error ADC Compensator 3P/3Z IIR Digital High Res D-3A D-3B FAULT-3A FAULT-3B EAP EAN Error ADC Compensator 3P/3Z IIR Digital High Res D-A D-B FAULT-A FAULT-B EAP EAN Diff Amp Error ADC Ref EA ADC bit Compensator IIR 3P/3Z Coeff. Regs Digital High Res D-A D-B FAULT-A FAULT-B CLK-Out SYNC-In AD-00 AD-0 AD-0 AD-4 ADCREFIN PWR GND BPCAP ADC bit 00 ksps Analog Comparators TRIP Ref TRIP Ref TRIP3 Ref 3 TRIP4 Ref 4 ARM-7 based digital Superviser Vreg Osc POR/BOR control PMBus PMBus-Clk PMBus-Data PMBus-Alert PMBus-Cntl PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright 007, Texas Instruments Incorporated

3 4-PIN AND 80-PIN I/O ASSIGNMENTS EAp EAn EAp EAn EAp3 EAn3 EAp4 EAn4 AD-00 (AddrSen/Vin) AD-0 (AddrSen/Vtrack) AD-0/COMP AD-03/COMP AD-04/COMP3 AD-0/COMP4 AD-0 AD-07 AD-08 AD-09 AD-0 (Temperature) PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood -RESET UCD940-4pin D-A D-B D-A D-B D-3A D-3B D-4A D-4B -A -B -A -B -3A -3B -4A -4B FAULT- FAULT- FAULT-3 FAULT-4 TMU- (TMS) TMU- (TCK) TMU-3 (TDI) SYNC-IN (TDO) SYNC-OUT -TRST RCK EAp EAn EAp EAn EAp3 EAn3 EAp4 EAn4 AD-00 (PMBus AddrSen) AD-0 (PMBus AddrSen) AD-0/COMP AD-03/COMP AD-04/COMP3 AD-0/COMP4 AD-0 AD-07 AD-08 AD-09 AD-0 (Tempurature) AD- (V-in) AD-(Vtrack) AD-3 AD-4 ADCref TMU- TMU- 0 TMU PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood -RESET UCD940-80pin D-A D-B D-A D-B D-3A D-3B D-4A D-4B -A -B -A -B -3A -3B -4A -4B FAULT-A FAULT-B FAULT-A FAULT-B FAULT-3A FAULT-3B FAULT-4A FAULT-4B SYNC-IN SYNC-OUT FAN- FAN-TACH Diag LED -TRST TMS TDI TDO TCK RCK The UCD940 is available in a plastic 80-pin TQFP package, and a 4-pin QFN package (RHB). 3

4 TYPICAL APPLICATION SCHEMATIC Vin FC49A +3.3V TLV7-0 Vin Vout +V UCD730 Driver Commutation logic -rail0a Vsens-rail0 -Vsens-rail0 +Vsens-rail -Vsens-rail +Vsens-rail -Vsens-rail +Vsens-rail3 -Vsens-rail4 -rail0a -raila -raila -rail3a -rail0b -railb CD-railB -rail3b Temp-com +3.3V EAp EAn EAp EAn EAp3 EAn3 EAp4 EAn4 V33FB V33A V33D V33DIO- V33DIO- BPCap AD-00 (AddrSen/Vin) AD-0 (AddrSen/Vtrack) AD-0/COMP AD-03/COMP AD-04/COMP3 AD-0/COMP4 AD-0 AD-07 AD-08 AD-09 AD-0 (Temperature) PMBus-Clk PMBus-Data 7 PMBus-Alert 8 PMBus-Ctrl 9 PowerGood 9 -RESET Agnd- Agnd- Agnd-3 Dgnd- Dgnd- Agnd D-A D-B D-A D-B D-3A D-3B D-4A D-4B -A -B -A -B -3A -3B -4A -4B FAULT- FAULT- FAULT-3 FAULT-4 TMU- (TMS) TMU- (TCK) TMU-3 (TDI) SYNC-IN (TDO) SYNC-OUT -TRST RCK Sync-in Sync-out CD74HC3 -rail0b -raila -railb -raila -railb +Vsens-rail0 -Vsens-rail0 +Vsens-rail -Vsens-rail +Vsens-rail -Vsens-rail Temp-rail0A Temp-rail0B Temp-railA Temp-railB Temp-railA Temp-railB Temp-rail3A Temp-rail3B Com S S S0 -EN +3.3V CD74HC40 Temp-com -rail3a -rail3b +Vsens-rail3 -Vsens-rail3 The diagram above shows the UCD940 Power Supply Controller working in a system which requires the regulation of four independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding into the Error ADC differential inputs, and completed by D outputs feeding into four separate UCD730 drivers 4

5 PIN DESCRIPTION (80-PIN) SIGNAL PIN NUMBER I/O DESCRIPTION ADCREFin ADC Decoupling Cap Ground reference. AD-0 I Current sense ADC Input #0 and analog comparator #4 Input. AD-04 3 I Current sense ADC Input #04 and analog comparator #3 Input. AD-03 4 I Current sense ADC Input #03 and analog comparator # Input. AD-08 I Current sense ADC Input #08. AD-09 I Current sense ADC Input #09. AD-0 7 I Temperature Mux ADC Input. V33DIO 8 I Digital I/O 3.3V supply. DGND 9 I Digital Ground. TMU-3 0 O Temerature multiplexer select S0 TMU- O Temerature multiplexer select S TMU- O Temerature multiplexer select S Reset~ 3 I Low Active device reset input. RCK 4 O JTAG Return TCLK FAULT-A I Gate driver fault A input. FAULT-B I Gate driver fault B input. FAULT-A 7 I Gate driver fault A input. FAULT-B 8 I Gate driver fault B input. PMBus-Clk 9 I/O PMBus Clk (Must have pull-up to 3.3V) PMBus-Data 0 I/O PMBus Data (Must have pull-up to 3.3V) D-A O D A output. D-B O D B output. D-A 3 O D A output. D-B 4 O D B output. D-3A O D 3A output. D-3B O D 3B output. D-4A 7 O D 4A output. D-4B 8 O D 4B output. FAULT-3A 9 I Fault 3A input. SYNC-OUT 30 O Sync output from D #?. SYNC-IN 3 I Sync input to D #?. FAN-TACH 3 I Fan tachometer input -4B 33 O Synchronous Rectifier Enable 4B DGND 34 I Digital Ground. PMBus-Alert 3 O PMBUS Alert PMBus-Ctrl 3 I PMBUS Cntl -A 37 O Synchronous Rectifier Enable A -B 38 O Synchronous Rectifier Enable B -A 39 O Synchronous Rectifier Enable A

6 -A 40 O Synchronous Rectifier Enable A FAULT-3B 4 I Fault 3A input. FAULT-4A 4 I Fault 4A input. FAULT-4B 43 I Fault 4B input. TCK 44 I JTAG TCK input. TDO 4 O JTAG TDO output. TDI 4 I JTAG TDI Input. TMS 47 I/O JTAG TMS Input. TRST 48 I/O JTAG TRST input. PowerGood 49 O Power Good signal -4A 0 O Synchronous Rectifier Enable 4A -4B O Synchronous Rectifier Enable 4B -3A O Synchronous Rectifier Enable 3A LED 3 O Diagnostic LED FAN- 4 O Fan control output. DGND I Digital Ground. V33DIO I Digital I/O 3.3V supply. V33D 7 I Digital Core 3.3V supply V33A 8 I Analog 3.3 V supply BPCAP 9 I Bypass Capacitor Connection. AGND 0 I Analog Ground. AGND I Analog Ground. EAP I Error Analog, differential voltage, Positive channel # input. EAN 3 I Error Analog, differential voltage, Negative channel # input. EAP 4 I Error Analog, differential voltage, Positive channel # input. EAN I Error Analog, differential voltage, Negative channel # input. EAP3 I Error Analog, differential voltage, Positive channel #3 input. EAN3 7 I Error Analog, differential voltage, Negative channel #3 input. EAP4 8 I Error Analog, differential voltage, Positive channel #4 input. EAN4 9 I Error Analog, differential voltage, Negative channel #4 input. V33FB 70 I 3.3V linear regulator Feedback connection. AD4 7 I ADC analog Input #4. AD3 7 I ADC analog Input #3. AD 73 I Voltage Tracking ADC analog Input #. AD 74 I Vin sense ADC analog Input #. AD0 7 I ADC analog Input #0 0 and analog comparator # Input. AD0 7 I PMBus address sense input #0. AD00 77 I PMBus address sense input #00. AD07 78 I Current sense ADC analog Input #07. AD0 79 I Current sense ADC analog Input #0. AGND 80 I Analog Ground.

7 Recommended operating conditions ELECTRICAL SPECIFIACTIONS SYMBOL PARAMETER MIN NOM MA UNIT V33D,V33DIOV Supply voltage during operation V 33A Supply during configuration changes V T A Operating free-air temperature range C Absolute Maximum Ratings Voltage applied at V33D to DGND -0.3 V to 3.V Voltage applied at V33A to AGND Voltage applied to any pin (see NOTE) Diode current at any device terminal Storage temperature, T STG -0.3 V to 3. V -0.3 V to V 33D V -C to 0C -40C to C Electrical Characteristics SYMBOL PARAMETER TEST CONDITION MIN NOM MA UNIT Supply Current I 33d I 33dio I 33a Supply current during configuration Supply current during configuration Supply current during configuration V 33d = 3.3V 3 mα V33dio = 3.3V mα V33a = 3.3V mα Analog Inputs/Outputs EAP,EAN, Error Differential EAP,EAN Voltage EAP3,EAN3, EAP4,EAN4 AD00 AD4 Generic ADC Input Voltage range AD0 AD0 Analog Comparator - 4 Voltage range V 0 3. V 0.0 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to V SS. 7

8 Vreg BPCap Bypass Capacitor.8 V Voltage V33FB 3.3V linear Reg Feedback V C I Input capacitance Only one terminal can be 7 pf selected at a time. V CC =. V ADCRefIn External Reference 3. V Miscellaneous T retention Reset~ t (reset) Retention of configuration parameters Digital Inputs/Outputs Pulse length needed at Reset~ pin to accept reset internally V33D=.V / 3V T J = C 00 Years μs GPIO 0 3. V V OH V OL I lkg High-level output voltage Low-level output voltage High-impedance leakage current I OH (max)= -. ma 3 V 33DIO = 3 V I OH (max) = - ma 4 V 33DIO = 3 V I OH (max)= -. ma V 33DIO = 3 V V 33dio 0. V 33dio 0. Dgnd V 33dio V 33dio Dgnd + 0. V 33DIO =. V / 3 V ±0 na V V Not production tested. Limits verified by design. 3 The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ± ma to hold the maximum voltage drop specified. 4 The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 ma to hold the maximum voltage drop specified The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ± ma to hold the maximum voltage drop specified. 8

9 FUNCTION OVERVIEW Controller The UCD940 contains four controllers. Each controller can be multiplexed to drive from one to eight power stages. Each controller consists of a Setpoint DAC, a difference amplifier, an error ADC, a digital compensator and a digital engine. Setpoint DAC and Difference Amplifier The reference for each control loop is set by a 0-bit DAC. The DAC is programmed by issuing VOUT_COMMAND, VOUT_TRIM or VOUT_MARGIN commands on the PMBus. The DAC produces a differential output voltage that ranges from 0 to.v. This reference voltage is applied to the difference amplifier which subtracts the differential output sense voltage from the DAC reference. Error ADC The output of the difference amplifier is applied to the error ADC. The error ADC is a -bit flash converter with a resolution of from mv to 8mV. The resolution of the error ADC is adjusted depending on the operation of the power supply. Digital Compensator The output of the error ADC feeds the compensator. The compensator is a digital filter consisting of a second order infinite impulse response (IIR) filter section cascaded with a first order IIR filter section. The coefficients of the filter sections are fully programmable through the PMBus. Several banks of filter coefficients can be downloaded to the device which automatically switches them in depending on the operation of the power stage. y n PER PER d signal error ADC b 0 b z - z - e n e n- e n- b y"' n K shift nd order filter stage Clip y" y" n- y" n- z - z - z - a x n x n- a b y' n Clip st order filter stage y n z - y' n- a A PC based Design Tool program is provide to assist in defining the compensator coefficients. The Design Tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop. In addition, the Design Tool can be used to characterize the power stage so that the compensator coefficients can be chosen based on the total loop gain for each feedback system. The compensator also allows the minimum and maximum duty cycle to be programmed. This again is done by issuing a PMBus command to the device. Engine The output of the compensator feeds the high resolution engine. The engine produces the pulse width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle 9

10 as a -bit number representing a value from 0.0 to.0. This duty cycle value is multiplied by the period to generate the ramp threshold. Inside the engine a digital ramp is produced continually. The resolution of that ramp is 0 psec. When the digital ramp values cross the threshold calculated by the compensator the gate drive signal is brought inactive. When the UCD940 is configured to drive multiple power stage circuits from one compensator, each gate drive output pulse width is adjusted to correct for current imbalance between the connected power stage sections. This is done by monitoring the current using the -bit ADC and increasing the pulse width of the signal driving the power stage with the lowest current and decreasing the pulse width of the signal driving the power stage with the highest measured current. Each engine can be synchronized to another PMW engine or to an external sync signal. An input sync signal causes a ramp timer to reset. Sync signal outputs from each of the four engines occur when the ramp timer crosses a programmed threshold. In this way the phase of multiple power stage drive signals can be tightly controlled. The synchronization behavior is programmed through a MFR_SPECIFIC PMBus command. Engine ( of 4) SysClk SyncIn Clk reset high res ramp counter Switch period Current balance adj Compensator output S R gate drive output EADC trigger threshold EADC trigger SyncOut phase SyncOut The switching frequency is set by issuing the FREQUENCY_SWITCH PMBus command. Current and Temperature Measurement The UCD940 contains a -bit ADC that is used to measure current and temperature in the controlled power stage. Channel 0 of the ADC, pin 7 on the 80-pin package, is dedicated to measuring temperature. It can be programmed to accept the output from either a linear device such as an LM0 temperature sensor or a diode forward voltage. The UCD940 also has three dedicated pins that can be used to select an eight to one analog multiplexer so that the temperature of each of the possible eight power stages can be monitored by the device. Channels through 9 are used to measure output or inductor current in each of the controlled power stages. MFR_SPECIFIC PMBus commands are used to calibrate each measurement. When the measured current exceeds either the overcurrent or undercurrent threshold a FAULT is declared the UCD940 performs the PMBus programmed fault recovery. ADC current measurements are digitally filtered (averaged) before compared against the FAULT threshold. In response to a PMBus request for a current reading, the device will return the filtered current measurements that are derived from the ADC. When the UCD940 is configured to drive a multi-phase power converter, the device will add the filtered current measurement for each of the power stages tied to a power rail. 0

11 Fault Handling The UCD940 has several fault handling features. The following faults are handled.. Vin is monitored by the over-voltage or under-voltage.. A logic high signal from an external source, such as the gate driver IC will cause a fault and immediately shut down the engine. The response to the event is programmed through a PMBus command. 3. The device contains programmable internal analog comparators that monitor the current sense inputs. If this voltage exceed the programmed threshold the signal is shut down. 4. The internal ADC monitors and digitally filters the combined current sense for each multiphase power stage that makes up an output rail. Over current and under current (negative) thresholds are programmed via PMBus for each rail. The response to the event is also programmed through a PMBus command. PMBus Interface The PMBus is an emerging serial interface specifically designed to support power management. It is based on the SMBus interface, which is built on I C signaling. The UCD940 supports the interface through dedicated firmware in the ARM-7 digital supervisory processor. By implementing the interface in firmware the UCD940 can be updated to respond to new revisions of the PMBus standard. Currently, the UCD940 supports revision. of the PMBus standard. Wherever possible, standard PMBus commands are used to support the function of the device. For unique features of the UCD940 MFR_SPECIFIC commands are defined to configure or activate those features. The firmware for the UCD940 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The firmware is also compliant with the SMBus. specification, including support for the SMBus ALERT function.